TWI588886B - Method of fabricating a semiconductor device - Google Patents

Description

Method of manufacturing a semiconductor device

The present invention relates to a method of providing a thin layer of semiconductor material on a receiving structure for use in a process for fabricating a semiconductor device, and is directed to structures and devices fabricated using such methods.

In a semiconductor device fabrication process, a semiconductor material is provided on an acceptor structure for various purposes including, for example, fabrication of a semiconductor-on-insulator (SeOI) type substrate and vertical stacking of semiconductor materials and devices in a so-called "three-dimensional (3D) integration process) Thin layer.

In such processes, it may be desirable to provide a layer of semiconductor material on the receiving structure with an average layer thickness as small as hundreds of nanometers or hundreds of nanometers or less, and in some applications even 100 nanometers (100 nm) or 100 nm. the following. Furthermore, the layer of semiconductor material preferably has a uniform thickness (e.g., the heterogeneity is less than 5% of the thickness of the layer of semiconductor material). In addition, it may be desirable for the layer of semiconductor material to be extremely smooth. For example, it may be desirable to form a layer of semiconductor material such that the surface roughness (Ra) of the predominantly exposed surface of the layer of semiconductor material is as low as five nanometers (5 nm) or less.

Various methods of providing this thin and smooth layer of semiconductor material on the receiving structure have been proposed in the art. However, there remains a need in the art for improved methods of providing a thin, uniform, and smooth layer of semiconductor material on the receiving structure.

This Summary is provided to introduce selected concepts in a simplified form. These concepts are described in more detail in the following detailed description of the exemplary embodiments of the invention. This Summary is not intended to identify key features or essential features of the claimed subject matter, and is not intended to limit the scope of the claimed subject matter.

In some embodiments, the invention includes a method of fabricating a semiconductor device. According to the methods, a crystalline germanium layer is provided on the receiving structure, a metal germanide is formed in a portion of the main exposed surface of the crystalline germanium layer adjacent to the crystalline germanium layer, and an etchant selective to the metal germanide is used with respect to the crystalline germanium. Etching metal halides.

In other embodiments, the invention includes a method of forming a substrate-on-insulator (SOI) substrate. In such methods, a crystalline germanium layer can be provided on the base substrate, wherein the crystalline germanium oxide layer has a dielectric material between the base substrate and the crystalline germanium layer can be thinned to a thickness of about 500 nm or less. In order to thin the crystalline germanium layer, a substantially flat metal germanide layer is formed in a portion of the crystalline germanium layer adjacent to the main exposed surface of the crystalline germanium layer, and a selective etching of the metal germanide layer relative to the crystalline germanium is used. The agent etches the metal halide layer.

Other embodiments of the invention include semiconductor structures and devices fabricated using such methods.

100‧‧‧Semiconductor structure

102‧‧‧ Crystallization layer/crystallization

102'‧‧‧ Section

103‧‧‧ exposed surface/main exposed surface

104‧‧‧Substrate

106‧‧‧Intermediate

108‧‧‧ pointing arrow

109‧‧‧ plane

110‧‧‧Semiconductor structure

112‧‧‧Metal Telluride/Metal Telluride Layer

114‧‧‧metal layer

120‧‧‧Semiconductor structure

122‧‧‧Active device structure

124A‧‧‧Additional layer

124B‧‧‧Additional layer

124C‧‧‧Additional layer

130‧‧‧Semiconductor structure

140‧‧‧Semiconductor structure

200‧‧‧donor structure

202‧‧‧Ion implantation plane

204‧‧‧ pointing arrow

300‧‧‧Semiconductor structure

310‧‧‧Semiconductor structure

320‧‧‧Semiconductor structure

D‧‧‧Selected depth

T _F ‧‧‧final average layer thickness

T _I ‧‧‧ initial average layer thickness

While the specification has been described with particular reference to the scope of the claims of the embodiments of the invention, the advantages of the embodiments of the invention may be described by the accompanying drawings. It is easy to determine, wherein: Figures 1 to 4 illustrate an exemplary embodiment of a method that can be used to thin a crystalline germanium layer in the fabrication of a semiconductor device; Figure 1 is a simplified cross-sectional view of a crystalline germanium layer on a substrate, wherein the crystalline germanium layer There is a dielectric material between the substrate and the substrate; FIG. 2 is a simplified view of the structure of FIG. 1 after smoothing the main exposed surface of the crystalline germanium layer. 3 is a simplified cross-sectional view showing the structure of FIG. 2 after forming a metal telluride material in a portion of the crystalline germanium layer; FIG. 4 is a view illustrating the removal of the metal telluride material shown in FIG. A simplified cross-sectional view of the remainder of the crystallization crucible; FIG. 5 is a simplified cross-sectional view showing the structure of the active device that can be fabricated in the thinned crystalline germanium layer of FIG. 4 and/or thinned crystalline germanium layer; FIG. 6 is an illustration A simplified cross-sectional view of other active device structural layers formed on the structure of FIG. 5 in a 3D integration process; FIG. 7 is a cross-sectional view similar to FIG. 2 and illustrating the implantation of metal ions into the crystalline germanium layer to illustrate that One embodiment of a method of forming a metal telluride material in the portion of the crystalline germanium layer shown in FIG. 3; FIG. 8 is a cross-sectional view similar to FIG. 2 and illustrating a metal layer deposited on the crystalline germanium layer prior to the annealing process To illustrate another embodiment of a method that can be used to form a metal telluride material in the portion of the crystalline germanium layer shown in FIG. 3; FIGS. 9 and 10 illustrate an example of a method that can be used to provide the structure shown in FIG. Embodiment, the structure is included on the substrate FIG. 9 is a simplified cross-sectional view illustrating the implantation of ions into a donor structure comprising bulk crystalline germanium to define a weak ion implantation plane therein; FIG. 10 illustrates the acceptance of bonding to a substrate comprising FIG. The donor structure of Figure 9 of the structure; Figures 11 through 15 illustrate other exemplary embodiments of the method similar to that described with reference to Figures 1 through 10, but wherein the crystalline germanium layer includes a previously fabricated active device structure; A simplified cross-sectional view of a crystalline germanium layer on a substrate having a dielectric material between the semiconductor material and the substrate, the crystalline germanium layer including at least partially formed active device structures; and FIG. 12 is a view illustrating a major exposed surface of the crystalline germanium layer Simplified structure of Figure 11 after smoothing FIG. 13 is a simplified cross-sectional view showing the structure of FIG. 12 after forming a metal halide material in a portion of the crystalline germanium layer; FIG. 14 is a view illustrating the removal of the metal germanide material shown in FIG. A simplified cross-sectional view of the remainder of the crystallization crucible; and FIG. 15 is a simplified cross-sectional view illustrating other active device structural layers formed on the structure of FIG. 14 in a 3D integration process.

The illustrations provided herein are not intended to be an actual view of any particular semiconductor material, structure, device, or method, but are merely idealized for describing embodiments of the present invention.

Any headings used herein are not to be construed as limiting the scope of the embodiments of the invention as defined by the scope of the following claims. The concepts described in any particular heading generally apply to the rest of the specification.

A number of references are cited herein, and are not related to how the representations are made herein, and the cited references are not to be considered as prior art to the invention of the subject matter claimed herein.

The term "Group III-V semiconductor material" as used herein means and includes at least one or more elements from Groups IIIA (B, Al, Ga, In, and Ti) of the Periodic Table and one or more from the periodic table. Any semiconductor material of the elements of Group VA (N, P, As, Sb, and Bi). For example, Group III-V semiconductor materials include, but are not limited to, GaN, GaP, GaAs, InN, InP, InAs, AlN, AlP, AlAs, InGaN, InGaP, GaInN, InGaNP, GaInNAs, and the like.

Embodiments of the methods disclosed herein can be used to thin a layer of material in the fabrication of a semiconductor device to provide a layer of crystalline germanium having a selected suitable average layer thickness.

1 illustrates a semiconductor structure 100 comprising a crystalline germanium layer 102 comprising crystalline germanium, a substrate 104, and an intermediate layer 106 between the crystalline germanium layer 102 and the substrate 104. In this configuration, the semiconductor structure 100 can comprise a silicon-on-insulator (SOI) type substrate. The substrate 104 can include the above The accepting structure for the crystalline germanium layer 102.

The crystalline germanium layer 102 contains crystalline germanium. In some embodiments, the crystalline germanium layer 102 can comprise a single crystal germanium. In other words, the crystalline germanium may comprise single crystal germanium. The portion of the crystalline germanium layer 102 above and/or within which the active device structure is to be fabricated (or fabricated) may be referred to as the "active" portion, and another portion of the crystalline germanium layer 102 that is not intended to include such active device structures may constitute a sacrifice. section. For example, a portion of the crystalline germanium layer 102 below the plane 109 (perspective view of FIG. 1) may constitute the active portion of the crystalline germanium layer 102, and the crystalline germanium layer 102 is above the plane 109 (perspective view of FIG. 1). Portions may form a sacrificial portion of the crystalline germanium layer 102.

The substrate 104 on which the crystalline germanium layer 102 is disposed may comprise a semiconductor material (eg, germanium, antimony, a III-V semiconductor material, etc.); a ceramic material such as an oxide (eg, aluminum oxide, hafnium oxide, zirconium oxide, etc.), a nitride (such as tantalum nitride) or carbide (such as tantalum carbide). In other embodiments, the substrate 104 can comprise a metal substrate. For example, substrate 104 can comprise one or more metals or metal alloys such as copper, molybdenum or stainless steel. In other embodiments, the substrate 104 can comprise a graphene plate or a diamond substrate. In some embodiments, substrate 104 can comprise a multilayer substrate (eg, a semiconductor-on-insulator (SeOI) type substrate, such as a germanium-on-insulator (SOI) substrate or a germanium-on-insulator (GeOI) substrate). Other suitable substrates are known in the art and can be used in embodiments of the invention. In some embodiments, substrate 104 can comprise at least partially fabricated semiconductor devices (eg, dies or wafers), and can include one or more integrated circuits (eg, electronic signal processor circuits, memory device circuits, etc.). By way of example and not limitation, substrate 104 may be thicker than crystalline germanium layer 102, and the average layer thickness may be, for example, about one micron (1 μm) or more, about ten micrometers (10 μm) or more, or even about one hundred micrometers. (100 μm) or 100 μm or more.

The intermediate layer 106 may comprise, for example, an oxide such as yttrium oxide (SiO ₂ ). In such embodiments, the intermediate layer 106 can comprise what is commonly referred to in the art as a "buried oxide" layer. May be used for other suitable dielectric material of the intermediate layer 106 comprises a nitride (e.g., silicon nitride (Si ₃ N ₄₎₎ and nitrogen oxides (e.g., silicon oxynitride (SiO _x N _y)). In some embodiments, the intermediate layer 106 can include an adhesive layer for bonding the crystalline germanium layer 102 to the substrate 104. In such embodiments, the intermediate layer 106 may comprise a dielectric material such as the dielectric material described above, a metal layer (eg, a layer of copper, silver, aluminum, titanium, tungsten, etc.) or a layer of semiconductor material different from the crystalline germanium layer 102. . The intermediate layer 106 can comprise a continuous layer of material layers deposited on one or both of the substrate 104 and the crystalline germanium layer 102. In other embodiments, the intermediate layer 106 may be discontinuous and may be patterned to include voids therein or through the voids at different locations of the intermediate layer 106.

By way of example and not limitation, the intermediate layer 106 can be thinner than the crystalline germanium layer 102, and the average layer thickness can be, for example, about one hundred nanometers (100 nm) or less, about fifty nanometers (50 nm) or less. Even about ten nanometers (10 nm) or less.

In accordance with an embodiment of the present invention, the crystalline germanium layer 102 can be thinned to have a selected final thickness as discussed in more detail below. In some embodiments, the exposed surface 103 of the crystalline germanium layer 102 can be relatively rough (as shown in enlarged view in FIG. 1). Therefore, before the crystallization layer 102 is thinned, the main exposed surface 103 of the crystallization layer 102 can be smoothed as shown in FIG. 2, and then the crystallization layer 102 is thinned. The primary exposed surface 103 can be smoothed using one or more of, for example, a mechanical grinding or polishing process, a chemical etching process, a chemical-mechanical polishing (CMP) process, or an ion conditioning process (eg, using a cluster ion beam).

In some embodiments, the crystalline germanium layer 102 can have an initial average layer thickness T _I prior to thinning (as described below), which can be about five hundred nanometers (500 nm) or less, about two hundred nanometers (200 nm). Or below 200 nm or even about 100 nanometers (100 nm) or less.

In accordance with an embodiment of the present invention, the crystalline germanium layer 102 can be self-initial average layer thickness T by forming a metal telluride material in a portion 102' of the crystalline germanium layer 102 and subsequently removing the metal germanide material from the crystalline germanium layer 102. _I (Fig. 2) is thinned to the final average layer thickness T _F (Fig. 4). For example, referring to FIG. 3, a portion 102' of the predominantly exposed surface 103 of the crystalline germanium adjacent to the crystalline germanium layer 102 can be converted to a metal germanide 112 (presented by stippling in FIG. 3) to form the semiconductor structure 110. The metal telluride 112 can constitute a metal telluride layer 112 having an average layer thickness of from about two nanometers (2 nm) to about ninety nanometers (90 nm). More specifically, the metal halide layer 112 may have an average layer thickness of from about five nanometers (5 nm) to about seventy nanometers (70 nm). Moreover, more specifically, the metal telluride layer 112 may have an average layer thickness of from about ten nanometers (10 nm) to about fifty nanometers (50 nm).

An example of a method that can be used to form the metal telluride layer 112 is described below with reference to FIGS. 7 and 8. In general, metal ions can be introduced into the crystalline germanium layer, and in the crystalline germanium layer, the metal ions can react with the phosphonium ions to form a metal telluride 112 compound.

Referring to Figure 7, in some embodiments, as represented by the pointing arrow 108, metal ions can be implanted through the major surface 103 into the portion 102' of the crystalline germanium layer 102 to convert the crystalline germanium in the portion 102' to metal. Telluride 112. The energy of the metal ions can be selectively set such that metal ions are implanted from the primary surface 103 into the crystalline germanium layer 102 for a selected depth D. The depth D can be selected to be positioned above, but close to, the boundary of the desired active layer within the crystalline germanium of the crystalline germanium layer 102. In addition, the energy of the implanted metal ions and the dose of implanted metal ions experienced by portion 102' of crystalline germanium layer 102 can be selected to reduce or minimize the so-called "range end" or "EOR" in crystalline germanium layer 102. "defect. Thus, a metal telluride layer 112 having a selected layer thickness less than the initial layer thickness T _I (FIG. 2) of the crystalline germanium layer 102 can be formed adjacent to its major surface 103 within the crystalline germanium layer 102.

The metal ions implanted in the crystalline germanium layer 102 may contain elemental metal ions. The elemental metal ions may comprise an element that forms a metal telluride 112 together with the germanium atoms in the crystalline germanium layer 102. For example, if the metal telluride 112 comprises nickel telluride (eg, Ni ₂ Si), the metal ion can comprise nickel ions. If the metal silicide 112 comprises a titanium silicide (e.g. TiSi _2), the metal ions comprise titanium ions. If the metal telluride 112 comprises tungsten telluride (eg, WSi ₂ ), the metal ion may comprise tungsten ions. ] As another example, if the metal silicide comprises COSI 112 (e.g., CoSi _2), the metal ion may comprise cobalt ions. Metal telluride 112 can be formed when metal ions are implanted into crystalline germanium layer 102 without further processing to form metal germanide 112. In other embodiments, after metal ions are implanted into portion 102' of semiconductor material layer 102, the structure can be annealed (eg, at a high temperature) to form metal telluride 112.

Referring to FIG. 8, in other embodiments, a metal layer 114 may be deposited over the crystalline germanium layer 102 to form the structure 116, followed by annealing the structure 116 at elevated temperatures to diffuse metal elements or elements of the metal 114 into the crystalline germanium layer 102. A metal halide 112 is formed whereby metal halide 112 (Fig. 3) is formed in portion 102' of crystalline germanium layer 102.

For example, metal layer 114 can comprise a layer of one or more of titanium, nickel, tungsten, and cobalt. The average layer thickness of the metal layer 114 may be, for example, about ten nanometers (10 nm) to several micrometers or more.

The annealing process can be carried out in a furnace. In some embodiments, the annealing process can include a rapid thermal annealing (RTA) process, a rapid annealing process, or a laser annealing process. The annealing process can be performed at a selected temperature for a selected time to control the diffusion depth of the metal element in the crystalline germanium layer 102 and thereby control the thickness of the resulting metal germanide layer 112 formed therein. It should be noted that deuteration can be slowed by highly doped enthalpy. Thus, in some embodiments, a portion of the crystalline germanium layer 102 can be highly doped (eg, N-doped or P-doped) and the doped portion can act as a barrier to the deuteration process. The thickness of the doped portion, or at least the location of the doped germanium region in the crystalline germanium layer 102, can be selectively controlled to selectively control the depth of formation of the metal germanide 112 in the crystalline germanium layer 102.

If any metal layer 114 remains after the annealing process, the remainder of the metal layer 114 can be removed using, for example, a polishing process, an etching process, an ion trim process, or a combination of such processes, followed by further processing.

In some embodiments, the process for forming the metal telluride 112 can be performed at relatively low temperatures to avoid unintentional destruction of other portions of the crystalline germanium layer 102 and/or any active device structure therein. For example, it may be in a portion of about seven degrees Celsius (700 ° C) or less than 700 ° C, about five degrees Celsius (500 ° C) or less than 500 ° C or even about three degrees Celsius (300 ° C) or less than 300 ° C. Metal halide 112 is formed in 102'. For example, nickel telluride (e.g., Ni ₂ Si) can be formed at a temperature of about 300 ° C, and titanium telluride (e.g., TiSi ₂ ) can be formed at a temperature between about 400 ° C and about 500 ° C.

Referring to FIG. 4, after the metal halide 112 (FIG. 3) is formed in the portion 102' (FIG. 2) of the crystalline germanium layer 102, it can be etched and removed using an etchant selective to the metal germanide 112 relative to the crystalline germanium. The metal halide 112 forms a semiconductor structure 120. In other words, an etchant that etches the metal germanide 112 in the portion 102' at a first etch rate may be selected that is higher than a second etch rate at which the etchant will etch the crystalline germanium layer 102. The first etch rate can be at least about ten (10) times the second etch rate, at least about one hundred (100) times the second etch rate, or in some embodiments at least about one thousand of the second etch rate ( 1,000) times. In this configuration, the crystalline germanium layer 102 can serve as an etch stop layer in an etch process for removing the overlying metal germanide 112. In other words, as the metal telluride 112 is gradually removed from the primary exposed surface 103 at a first etch rate, the etch process will effectively stop when the metal telluride 112 is at least substantially removed and the underlying crystalline ruthenium surface is exposed. Because the etch rate will drop significantly to the slower second etch rate.

The etching process for etching the metal germanide 112 may include a wet etching process, a dry etching process (such as a plasma etching process), or an electrochemical etching process.

The composition of the etchant used in the etching process will depend on the composition of the metal halide 112 and the crystalline germanium. A wide variety of suitable etchants for crystallizing ruthenium are known in the art and such etchants can be used in embodiments of the present invention. As a non-limiting example, the etchant can comprise hydrofluoric acid (HF). In such embodiments, HF may or may not be diluted and may be in a liquid or gaseous state. In some embodiments, the etchant can comprise buffered hydrofluoric acid (BHF).

In some embodiments, the etching process for removing the metal telluride 112 can be at about one hundred degrees Celsius (100 ° C) or below, below about fifty degrees (50 ° C) or below 50 ° C or even about two degrees Celsius It is carried out at a temperature of fifteen degrees (25 ° C) or below 25 ° C. Thus, the etching process can be performed at room temperature or in some embodiments even below room temperature. These embodiments may be special The case where the crystalline germanium layer 102 comprises a pre-fabricated active device structure is discussed in more detail below with reference to Figures 11-15.

With continued reference to FIG. 4, after the crystalline germanium layer 102 is thinned by converting a portion 102' of the crystalline germanium layer 102 (FIG. 2) to the metal germanide 112 (FIG. 3) and subsequently removing the metal germanide 112, the germanium is crystallized. The final average layer thickness T _{F of} layer 102 will be less than the initial average layer thickness T _{I of} crystalline germanium layer 102 (Fig. 2). In some embodiments, the removal of the metal telluride 112 may form a crystalline germanium layer 102 having a final average layer thickness T _F of about five hundred nanometers (500 nm) or less, about one hundred nanometers (100 nm) or 100 nm. Below or even about 50 nm (50 nm) or below 50 nm.

In some embodiments, after removal of the metal halide 112, the average exposed surface roughness (Ra) of the predominantly exposed surface 103 of the crystalline germanium layer 102 can be about five nanometers (5 nm) or less, or even about two nanometers ( 2 nm) or less. Optionally, after thinning the crystalline germanium layer 102, the major exposed surface 103 of the crystalline germanium layer 102 can be smoothed to reduce the surface roughness of the primary exposed surface 103 to the desired or desired value.

For example, the primary exposed surface 103 can be smoothed using one or more of a wet cleaning process, a chemical-mechanical polishing (CMP) process, a plasma cleaning process, and an ion conditioning process. As a non-limiting example, the primary exposed surface 103 may undergo a cleaning process known in the art as the "SC-1" cleaning process and/or a cleaning process referred to in the art as the "SC-2" cleaning process. In the SC-1 process, ammonium hydroxide (NH ₄ OH), hydrogen peroxide (H ₂ O ₂ ) can be used at temperatures ranging from about 75 degrees Celsius (75 ° C) to about 80 degrees Celsius (80 ° C). And the water (H ₂ O) 1:1:5 solution cleans the semiconductor structure 120, and then uses hydrofluoric acid (HF) and water (H ₂ O) at a temperature of about 25 degrees Celsius (25 ° C) 1:50 solution cleaning. The semiconductor structure 120 can be rinsed with deionized water before and after each cleaning step. In the SC-2 process, hydrochloric acid (HCl), hydrogen peroxide (H ₂ O ₂ ) and water can be used at temperatures ranging from about 75 degrees Celsius (75 ° C) to about 80 degrees Celsius (80 ° C). The semiconductor structure 120 is cleaned by a 1:1:6 solution of H ₂ O). Likewise, the semiconductor structure 120 can be rinsed with deionized water before and after each cleaning step. In other embodiments, the major surface 103 of the crystalline germanium layer 102 can be cleaned using ozone.

As previously described, the semiconductor structure 120 shown in FIG. 4 can comprise a silicon-on-insulator (SOI) type substrate. The semiconductor structure 120 can be used to fabricate any of a variety of different types of semiconductor devices, including one or more portions of the crystalline germanium layer 102. Such semiconductor devices include, for example, electronic signal processors, memory devices, light emitting diodes, laser diodes, photovoltaic cells, and the like.

Referring to FIG. 5, to fabricate the semiconductor devices, an active device structure 122 can be fabricated on the crystalline germanium layer 102 and/or the crystalline germanium layer 102 to form the semiconductor structure 130. The active device structures 122 can include one or more of, for example, a PN junction, a transistor, a wire, and a conductive channel.

Various additional layers of the active device structure 122 may be provided on the active device structure 122 formed in the crystalline germanium layer 102 and/or the crystalline germanium layer 102, as appropriate. For example, FIG. 6 illustrates another semiconductor structure 140 that includes two additional layers 124A, 124B provided on the active device structure 122 formed in the crystalline germanium layer 102 and/or the crystalline germanium layer 102. The additional layers 124A, 124B may be formed by depositing or epitaxially growing additional layers of crystalline germanium and forming additional active device structures 122 in the respective crystalline germanium layers. In other embodiments, the additional layers 124A, 124B can be separately fabricated and subsequently transferred and bonded to the crystalline germanium layer 102 using a 3D integrated process.

Referring again to FIG. 1, in some embodiments, the initial semiconductor structure 100 can be provided by transferring the crystalline germanium layer 102 from the donor structure to a receiving structure comprising the substrate 104. By way of example and not limitation, the crystalline germanium layer 102 can be transferred from the donor structure to the substrate 104 using a process known in the art as the SMART-CUT® process. The SMART-CUT® process is described in, for example, U.S. Patent No. RE39, 484, issued to Bruel, issued on Feb. 6, 2007, issued to U.S. Patent No. 6,303,468, issued to Aspar et al. U.S. Patent No. 6,335,258 (issued Jan. 1, 2002), U.S. Patent No. 6,756,286 to Moriceau et al. (issued on June 29, 2004), and U.S. Patent No. 6,809,044 to Aspar et al. No. 6,946,365 (September 20, 2005) to Aspar et al.

The SMART-CUT® process is briefly described below with reference to FIGS. 9 and 10. Referring to FIG. 9, a plurality of ions (eg, one or more of hydrogen, helium or inert gas ions) can be implanted into the donor structure 200 along the ion implantation plane 202. The donor structure 200 can comprise bulk crystalline germanium (eg, single crystal germanium). Ion implantation is presented in Figure 9 by pointing arrow 204. Ions implanted along the ion implantation plane 202 define a weak plane within the donor structure 200 along which the donor structure 200 can then rupture or otherwise break. As is known in the art, the depth of implantation of ions in the donor structure 200 varies, at least in part, with the energy used in ion implantation of the donor structure 200. In general, ions implanted with less energy will be implanted at a relatively shallow depth, while ions implanted with higher energy will be implanted at a relatively deeper depth.

Referring to Figure 10, the donor structure 200 is bonded to another receiving structure comprising the substrate 104, after which the donor structure 200 is broken or otherwise broken along the ion implantation plane 202. To bond the donor structure 200 to the substrate 104, the bonding surface of the donor structure 200 and the substrate 104 can be oxidized to provide an oxide material layer thereon, and the oxide layer can be directly in physical contact between the substrate 104 and the donor structure. An oxide-oxide direct molecular bond is established between 200. As shown in FIG. 10, the bonded oxide layers together form an intermediate layer 106. In other embodiments, the intermediate layer 106 can comprise a metal or semiconductor material formed by establishing a direct molecular bond between two layers of the materials.

After the bonding process, the bonded donor structure 200 can be broken or otherwise broken along the ion implantation plane 202 to form the structure shown in FIG. For example, the donor structure 200 and the receiving structure can be heated to break the donor structure 200 along the ion implantation plane 202. Mechanical forces may be applied to the donor structure 200 to assist in rupturing the donor structure 200 along the ion implantation plane 202, as appropriate.

After the donor structure 200 has been broken or otherwise broken along the ion implantation plane 202, a portion of the donor structure 200 remains bonded to the substrate 104 of the receiving structure, which portion defines The crystalline germanium layer 102 shown in FIG. The remainder of the donor structure 200 can be reused in other SMART-CUT® processes to transfer other portions of the donor structure 200 to the receiving structure.

After the rupture process, the major exposed surface 103 of the crystallization layer 102 includes the fracture surface of the donor structure 200 and may include ionic impurities and defects in the crystal lattice of the crystallization layer 102. The crystalline germanium layer 102 can be treated to attempt to reduce the impurity content in the crystalline germanium layer 102 and to improve the lattice quality (i.e., reduce the number of defects in the crystal lattice near the primary exposed surface 103). Such treatments may include one or more of grinding, polishing, etching, and thermal annealing.

In other embodiments, the crystalline germanium layer 102 can be epitaxially grown or otherwise deposited on the substrate 104 and the intermediate layer 106, or by blocking the bulk crystalline germanium on the substrate 104 and the intermediate layer 106 and then using abrading. One or more of the process, the polishing process, and the etching process (eg, a chemical-mechanical polishing process) thin the bulk crystalline germanium to an initial average layer thickness T _I to provide a crystalline germanium layer 102 on the substrate 104.

In some embodiments, the crystalline germanium layer 102 can be selected to include the active device structure 122 therein, followed by performing the thinning process described above with reference to FIGS. 3 and 4. These methods are described below with reference to FIGS. 11 through 15.

11 illustrates a semiconductor structure 300 including a crystalline germanium layer 102 and an active device structure 122 formed on crystalline germanium 102 and/or crystalline germanium 102. The active device structure 122 can include one or more of, for example, a PN junction, a transistor, a wire, and a conductive channel. In some embodiments, the active device structure 122 can be embedded within the crystalline germanium layer 102. In some embodiments, the crystalline germanium layer 102 having the active device structure 122 therein can be transferred and bonded to the substrate 104 in a layer transfer process.

As shown in FIG. 12, prior to thinning the crystalline germanium layer 102, the primary exposed surface 103 of the crystalline germanium layer 102 can be smoothed as previously described with reference to FIG. The primary exposed surface 103 can be smoothed using one or more of, for example, a mechanical grinding or polishing process, a chemical etching process, and a chemical-mechanical polishing (CMP) process.

A portion 102' of the crystalline germanium layer 102 can be converted to a metal germanide 112 to form Figure 13. The semiconductor structure 300 is shown. By way of example, but not limitation, metal telluride 112 can be formed using the methods previously described with reference to Figures 7 and 8. In an embodiment in which the crystalline germanium layer 102 includes the active device structure 122, it may be about seven hundred degrees Celsius (700 ° C) or less, less than five degrees Celsius (500 ° C) or less than 500 ° C or even about three degrees Celsius (300 degrees Celsius). The metal telluride 112 is formed in the portion 102' at a temperature of or below 300 °C to avoid damaging the previously formed active device structure 122.

After the metal germanide 112 is formed in the semiconductor material layer 102, the metal germanide 112 can be removed using an etching process as previously described with reference to FIG. 4 to form the semiconductor structure 310 shown in FIG. Therefore, the crystallization layer 102 can be thinned from the initial average layer thickness T _I shown in FIG. 12 to the selected final average layer thickness T _F shown in FIG.

Various additional layers of the active device structure 122 may be provided on the active device structure 122 and the crystalline germanium layer 102, as appropriate. For example, FIG. 15 illustrates another semiconductor structure 320 that includes three additional layers 124A, 124B, 124C provided on active device structure 122 and crystalline germanium layer 102. The additional layers 124A, 124B, 124C may be formed by depositing or epitaxially growing additional layers of crystalline germanium and forming additional active device structures 122 in the respective crystalline germanium layers. In other embodiments, the additional layers 124A, 124B, 124C can be fabricated separately and subsequently transferred and bonded to the crystalline germanium layer 102 using a 3D integrated process.

Other non-limiting, exemplary embodiments of the invention are set forth below:

Embodiment 1 : A method of fabricating a semiconductor device, comprising: providing a crystalline germanium layer on a receiving structure; forming a metal telluride in a portion of a main exposed surface of the crystalline germanium adjacent to the crystalline germanium layer; and using a pair of crystalline germanium The metal telluride has a selective etchant to etch the metal halide.

Embodiment 2: The method of Embodiment 1, wherein providing the crystalline germanium layer on the accepting structure comprises transferring the crystalline germanium layer from the donor structure to the accepting structure.

Embodiment 3: The method of Embodiment 2, further comprising selecting the crystalline germanium layer to comprise the active device structure.

Embodiment 4: The method of Embodiment 3, further comprising selecting the crystalline germanium layer to include one or more of a PN junction, a transistor, a wire, and a conductive channel.

The method of any one of embodiments 1 to 4, further comprising selecting the crystalline ruthenium to comprise a single crystal ruthenium.

The method of any one of embodiments 1 to 5, wherein the forming of the metal telluride in the portion of the crystalline germanium adjacent to the predominantly exposed surface of the crystalline germanium layer comprises: depositing a metal on the predominantly exposed surface of the crystalline germanium layer And annealing the deposited metal and the crystalline germanium layer to form a metal telluride.

The method of any one of embodiments 1 to 5, wherein forming a metal halide in a portion of the crystalline germanium adjacent to the predominantly exposed surface of the crystalline germanium layer comprises implanting metal ions into the crystalline germanium to form a metal germanium Things.

Embodiment 8. The method of Embodiment 7, further comprising selecting a metal ion to comprise at least one of titanium, nickel, cobalt, and tungsten.

The method of any one of embodiments 1 to 8, wherein the forming of the metal halide in the portion of the crystalline germanium comprises forming a metal in the portion of the crystalline germanium at a temperature of about 700 ° C or less. Telluride.

Embodiment 10: The method of Embodiment 9, wherein the forming of the metal halide in the portion of the crystalline germanium at a temperature of about 700 ° C or less comprises crystallization at a temperature of about 500 ° C or less. A metal halide is formed in this portion.

Embodiment 11: The method of Embodiment 10, wherein the forming of the metal halide in the portion of the crystalline germanium at a temperature of about 500 ° C or less comprises crystallization at a temperature of about 300 ° C or less. A metal halide is formed in this portion.

The method of any one of embodiments 1 to 11, wherein etching the metal halide comprises etching the metal halide using one or more of a wet etching process, a dry etching process, and an electrochemical etching process.

Embodiment 13: The method of any one of embodiments 1 to 12, wherein the metal is etched The object comprises a surface that at least substantially removes the metal halide and exposes the crystalline germanium.

Embodiment 14: The method of Embodiment 13, further comprising smoothing the surface of the crystalline crucible using one or more of a wet cleaning process, a chemical-mechanical polishing process, a plasma cleaning process, and an ion conditioning process.

The method of any one of embodiments 1 to 14, wherein etching the metal telluride comprises etching the metal telluride at a temperature of about one hundred degrees Celsius (100 ° C) or less.

The method of any one of the preceding embodiments, wherein the etching of the metal halide at a temperature of about one hundred degrees Celsius (100 ° C) or less is comprised at about twenty-five degrees Celsius (25 ° C) or 25 The metal telluride is etched at a temperature below °C.

The method of any one of embodiments 1 to 16, wherein etching the metal halide using an etchant selective to the metal telluride relative to the crystalline germanium comprises etching the metal germanide with HF.

The method of any one of embodiments 1 to 17, further comprising forming an SOI-type substrate comprising a crystalline germanium, a receiving structure, and a dielectric layer therebetween.

The method of any one of embodiments 1 to 18, further comprising forming one of an electronic signal processor, a memory device, a light emitting diode, a laser diode, and a photovoltaic cell comprising crystalline germanium or More.

The method of any one of embodiments 1 to 19, further comprising forming a crystalline germanium layer to have an average layer thickness of about 500 nm or less after etching the metal germanide.

Embodiment 21. The method of Embodiment 20, further comprising forming a crystalline germanium layer to have an average layer thickness of about 100 nm or less after etching the metal telluride.

Example 22: The procedure of Example 1 to 21 any one of which further comprises, after etching of the metal silicide crystal silicon layer of the exposed major surface average surface roughness R _a is about 5.0nm 5.0nm or less.

Example 23: The procedure of Example 22 of the embodiment, further comprising, after etching a metal silicide layer of crystalline silicon so that the exposed major surface average surface roughness R _a is about 2.0nm 2.0nm or less.

Embodiment 24: A method of forming a substrate-on-insulator (SOI) substrate, comprising: providing a crystalline germanium layer on a substrate, wherein a dielectric material is provided between the crystalline polyoxynitride layer and the base substrate; and the crystalline germanium layer is changed Thin to a thickness of about 500 nm or less. Thinning the crystalline germanium layer comprises: forming a substantially planar metal germanide layer in a portion of the predominantly exposed surface of the crystalline germanium layer adjacent to the crystalline germanium layer; and etching selective to the metal germanide layer relative to the crystalline germanium layer The agent etches the metal halide layer.

Embodiment 25: The method of Embodiment 24, wherein forming a metal halide in a portion of the crystalline germanium adjacent to the predominantly exposed surface of the crystalline germanium layer comprises: depositing a metal on a predominantly exposed surface of the crystalline germanium layer; and depositing the metal And the crystalline germanium layer is annealed to form a metal telluride.

Embodiment 26: The method of Embodiment 24, wherein forming a metal halide in a portion of the crystalline germanium adjacent to the predominantly exposed surface of the crystalline germanium layer comprises implanting metal ions into the crystalline germanium to form a metal germanide.

Embodiment 27. The method of embodiment 26, further comprising selecting a metal ion to comprise at least one of titanium, nickel, cobalt, and tungsten.

The method of any one of embodiments 24 to 27, wherein the forming the metal halide in the portion of the crystalline germanium comprises forming a metal in the portion of the crystalline germanium at a temperature of about 700 ° C or less. Telluride.

Embodiment 29: The method of Embodiment 28, wherein the forming of the metal halide in the portion of the crystalline germanium at a temperature of about 700 ° C or less comprises crystallization at a temperature of about 500 ° C or less. A metal halide is formed in this portion.

Embodiment 30: The method of Embodiment 29, wherein the forming of the metal halide in the portion of the crystalline germanium at a temperature of about 500 ° C or less is included at about 300 ° C or 300 ° C. A metal telluride is formed in this portion of the crystalline germanium at a lower temperature.

The method of any one of embodiments 24 to 30, wherein etching the metal telluride comprises etching the metal telluride at a temperature of about one hundred degrees Celsius (100 ° C) or less.

Embodiment 32: The method of Embodiment 31, wherein the etching of the metal halide at a temperature of about one hundred degrees Celsius (100 ° C) or less is contained at a temperature of about 25 degrees Celsius (25 ° C) or below 25 ° C. The metal halide is etched under.

The method of any one of embodiments 24 to 32, further comprising forming a crystalline germanium layer to have an average layer thickness of about 100 nm or less after etching the metal telluride.

Example 34: The method of any one of embodiments 24-33, further comprising, after etching a metal silicide layer of crystalline silicon so that the exposed major surface average surface roughness R _a is about 5.0nm 5.0nm or less.

Example 35: The method of embodiment 34, further comprising, after etching a metal silicide layer of crystalline silicon so that the exposed major surface average surface roughness R _a is about 2.0nm 2.0nm or less.

The above-described exemplary embodiments of the present invention are not intended to limit the scope of the invention, and the scope of the invention is defined by the scope of the appended claims and their legal equivalents. Any equivalent embodiments are intended to fall within the scope of the invention. In fact, various modifications of the invention, such as alternative combinations of the elements described herein, are apparent to those skilled in the art. In other words, one or more features of one exemplary embodiment described herein can be combined with one or more features of another exemplary embodiment described herein to provide further embodiments of the invention. Such modifications and embodiments are also intended to fall within the scope of the appended claims.

100‧‧‧Semiconductor structure

102‧‧‧ Crystallization layer/crystallization

103‧‧‧ exposed surface/main exposed surface

104‧‧‧Substrate

106‧‧‧Intermediate

109‧‧‧ plane

Claims (15)

A method of fabricating a semiconductor device, comprising: providing a crystalline germanium layer on a receiving structure; and after providing the crystalline germanium layer on the receiving structure, reducing a thickness of the crystalline germanium layer, the thickness comprising: adjacent Forming a layer consisting essentially of metal telluride in a portion of the crystalline germanium layer of the predominantly exposed surface of the crystalline germanium layer, wherein forming the layer consisting essentially of metal germanide comprises implanting metal ions into the crystalline germanium layer Forming the layer consisting essentially of the metal telluride; and after forming the layer consisting essentially of the metal telluride, using a selective etching of the layer consisting essentially of the metal telluride relative to the crystalline germanium layer Etching the layer consisting essentially of a metal halide, the etchant being removed at an etch rate that is higher than any etch rate at which the layer consisting essentially of metal germanide removes the crystalline germanium layer A layer of metal halide. The method of claim 1, wherein providing the crystalline germanium layer on the accepting structure comprises transferring the crystalline germanium layer from the donor structure to the accepting structure. The method of claim 2, further comprising selecting the crystalline germanium layer to comprise an active device structure. The method of claim 1, wherein the forming of the layer consisting essentially of metal telluride in the portion of the crystalline germanium layer adjacent to the major exposed surface of the crystalline germanium layer comprises: depositing on the predominantly exposed surface of the crystalline germanium layer And annealing the deposited metal and the crystalline germanium layer to form the layer consisting essentially of metal germanide. The method of claim 1, further comprising selecting the metal ions to include at least one of titanium, nickel, cobalt, and tungsten. The method of claim 1, wherein the layer consisting essentially of the metal telluride is formed in the portion of the crystalline germanium layer at a temperature of about 700 ° C or less, at the portion of the crystalline germanium layer The layer consisting essentially of metal telluride is formed. The method of claim 1, wherein etching the layer consisting essentially of metal germanide comprises etching the layer consisting essentially of metal telluride using one or more of a wet etching process, a dry etching process, and an electrochemical etching process . The method of claim 1, wherein etching the layer consisting essentially of the metal telluride comprises at least substantially removing the layer consisting essentially of the metal telluride and exposing the surface of the crystalline germanium layer. The method of claim 8, further comprising smoothing the surface of the crystalline germanium layer using one or more of a wet cleaning process, a chemical-mechanical polishing process, a plasma cleaning process, and an ion conditioning process. The method of claim 1, wherein etching the layer consisting essentially of metal telluride comprises etching the layer consisting essentially of metal telluride at a temperature of about one hundred degrees Celsius (100 ° C) or less. The method of claim 1, wherein the etchant is selectively etched using the etchant with respect to the metal ruthenium layer to form the layer consisting essentially of a metal ruthenium comprising etching with HF to form substantially Layer. The method of claim 1, further comprising forming an SOI type substrate comprising the crystalline germanium layer, the accepting structure, and a dielectric layer therebetween. The method of claim 1, further comprising forming one or more of an electronic signal processor, a memory device, a light emitting diode, a laser diode, and a photovoltaic cell including the crystalline germanium layer. The method of claim 1, further comprising forming the crystalline germanium layer to have an average layer thickness of about 100 nm or 100 after etching the layer consisting essentially of metal germanide Below nm. The method of Paragraph 1 requests, further comprising, after etching the layer consists essentially of a metal silicide, so that the silicon layer is exposed principal crystalline average surface roughness R _a is about 2.0nm 2.0nm or less.