CN100561729C - Double mosaic structure manufacture method - Google Patents
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- CN100561729C CN100561729C CNB2006100299080A CN200610029908A CN100561729C CN 100561729 C CN100561729 C CN 100561729C CN B2006100299080 A CNB2006100299080 A CN B2006100299080A CN 200610029908 A CN200610029908 A CN 200610029908A CN 100561729 C CN100561729 C CN 100561729C
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Abstract
A kind of double mosaic structure manufacture method comprises: provide a surface to have the Semiconductor substrate of first dielectric layer; In described first dielectric layer, form metal interconnecting wires; Form cover layer at described first dielectric layer and described conductive structure laminar surface; Form second dielectric layer on the described cover layer and in described second dielectric layer, forming connecting hole; On described second dielectric layer, form bottom anti-reflection layer, barrier bed and photoresist layer; The described bottom anti-reflection layer of etching, barrier bed and photoresist layer, and described cover layer is until exposing described metal interconnecting wires; Fill metal material and form dual-damascene structure.The barrier bed of bottom anti-reflection layer surface deposition one deck densification that method of the present invention covers on second dielectric layer, this layer barrier bed can stop the nitrogen ion in the cover layer to contact with photoresist, thereby avoided the generation of photoresist intoxicating phenomenon.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, the manufacture method of particularly a kind of dual-damascene structure (dualdamascene structure).
Background technology
Current semiconductor device processing technology develop rapidly, semiconductor device has had the deep-submicron structure, comprises the semiconductor element of enormous quantity in the integrated circuit.In large scale integrated circuit like this, the high-performance between the element, highdensity connection not only interconnect in single interconnection layer, and will interconnect between multilayer.Therefore, provide multilayer interconnect structure usually, wherein a plurality of interconnection layers pile up mutually, and interlayer dielectric places therebetween, are used to connect semiconductor element.The multilayer interconnect structure that particularly utilizes dual damascene (dual-damascene) technology to form, it forms groove (trench) and connecting hole (via) in advance in interlayer dielectric, then with electric conducting material for example copper (Cu) described groove of filling and connecting hole.This interconnection structure is used widely in the integrated circuit manufacturing.
The technology of dual-damascene technics focuses on etching and fills the etching groove technology that conductor metal is used.In the leading portion etch process of dual-damascene technics, exist two kinds of methods to make the groove of double-embedded structure at present, first method is to define the lead groove on the top of dielectric layer earlier, utilizes another photoresist layer definition interlayer hole opening afterwards.Another kind method is at first to define the interlayer hole opening that penetrates dielectric layer fully in dielectric layer, utilizes another photoresist layer definition lead groove then.But no matter be which kind of method, all need between substrate surface and interlayer dielectric layer (ILD), form the nitrogenous cover layer of one deck.
Along with the characteristic size of device is constantly dwindled, the dense degree of device is more and more higher in the substrate, to the demands for higher performance of the high speed processing signal under the performance of integrated circuit especially radio frequency conditions.In order to reduce the delay of radiofrequency signal in circuit, generally adopt low-k (low k) material as interlayer dielectric layer (ILD) at present, postpone with the RC that reduces in the circuit.Yet because the density of low k material is lower, a large amount of uses of low-density dielectric material can bring some negative issues to making dual-damascene structure.For example, application number is to have described a kind of double mosaic structure manufacture method in 200510056297.4 the Chinese patent application.Fig. 1 to Fig. 5 is this existing generalized section of making the dual-damascene structure method of explanation.,, when forming dual-damascene structure, between substrate 10 surfaces with interconnection line 12a and 12b and ILD layer 14, form usually among Fig. 1 to shown in Figure 5 as Fig. 1 by SiCN or Si
3N
4The cover layer of forming 13.This cover layer can prevent that the metallic copper among the interconnection line 12a and 12b is diffused in the ILD layer 14 in the substrate, also can prevent that interconnection line 12a and 12b are not etched in the etching process.Among Fig. 2, in ILD layer 14, utilize technologies such as photoetching, etching to form connecting hole 15a and 15b, afterwards, in Fig. 3, cover bottom anti-reflection layer (BARC) 16 in ILD layer upper surface.Then, as shown in Figure 4,, and, form the photoresist 17a and the 17b of patterning by exposure, development at BARC layer 16 surface coated photoresist.In this process, especially in the process of subsequent etching BARC layer 16 with the formation groove, as shown in Figure 5, nitrogen ion in the cover layer 13 can pass low-density ILD layer 14 and BARC layer 16 reacts with photoresist 17a and 17b, form high molecular polymer " lump " 18a and the 18b of indissoluble on the photoresist sidewall, this paper is called this phenomenon " photoresist poisoning (resist poisoning) ".The photoresist intoxicating phenomenon can cause groove figure defective to occur.
Summary of the invention
Therefore, the object of the present invention is to provide a kind of double mosaic structure manufacture method, can eliminate the generation of photoresist intoxicating phenomenon.
For achieving the above object, the invention provides a kind of double mosaic structure manufacture method, comprising:
Provide a surface to have the Semiconductor substrate of first dielectric layer;
In described first dielectric layer, form metal interconnecting wires;
Form cover layer at described first dielectric layer and described conductive structure laminar surface;
Form second dielectric layer on the described cover layer and in described second dielectric layer, forming connecting hole;
On described second dielectric layer, form three-decker;
Described three-decker of etching and described cover layer are until exposing described metal interconnecting wires;
Fill metal material and form dual-damascene structure.
Described three-decker comprises bottom anti-reflection layer, barrier bed and photoresist layer, described bottom anti-reflection layer covers the surface of described second dielectric layer, described barrier bed is formed at described anti-reflecting layer surface, and described photoresist layer is patterned on described barrier bed surface.
Described barrier bed is to utilize plasma-reinforced chemical vapor deposition process deposit in 150 ℃～300 ℃ temperature range to form.
Described barrier bed is the Silicon-rich polymer, utilizes spin coating (spin-on) technology to form, and thickness is
Described barrier bed is a silica, and thickness is
Described second dielectric layer is silicon oxide carbide (SiCO), silica or fluorinated silica glass, and thickness is
Described cover layer is silicon nitride or silicon oxynitride or nitrogen silicon oxide carbide, and thickness is
The thickness that is positioned at the lip-deep described bottom anti-reflection layer of described second dielectric layer is
The thickness of described photoresist layer is
The present invention has the another kind of double mosaic structure manufacture method of identical or relevant art feature, comprising:
The Semiconductor substrate that provides a surface to have dielectric layer forms metal interconnecting wires in described dielectric layer;
Described dielectric layer of planarization and described metal interconnecting wires;
Form cover layer at described dielectric layer and described conductive structure laminar surface;
On described cover layer, form interlayer dielectric layer, in described interlayer dielectric layer, form connecting hole;
Cover bottom anti-reflection layer having on the interlayer dielectric layer of connecting hole;
Form barrier bed at described bottom anti-reflective laminar surface;
Described barrier bed surface-coated photoresist and the described light of patterning to resist with the definition groove opening;
The described light of etching is to resist and described barrier bed;
The described barrier bed of etching, bottom anti-reflection layer and interlayer dielectric layer;
Remove the cover layer of the corresponding described interconnection line of remaining bottom anti-reflection layer and channel bottom position;
In connecting hole and groove, fill metal then and just formed dual-damascene structure.
Described barrier bed utilizes plasma-reinforced chemical vapor deposition process to form in 150 ℃～300 ℃ temperature range.
Described barrier bed is that SHIN-ETSU HANTOTAI (Shinetzu) house mark is that the Silicon-rich polymer of SHB utilizes spin coating (spin-on) technology to form, and thickness is
Described barrier bed is a silica, and thickness is
Described interlayer dielectric layer is that Material Used (Applied Materials) house mark is silicon oxide carbide (SiCO), silica or the fluorinated silica glass of black diamond, and thickness is
Described cover layer is silicon nitride or silicon oxynitride or nitrogen silicon oxide carbide, and thickness is
The thickness that is positioned at the lip-deep described bottom anti-reflection layer of described second dielectric layer is
The thickness of described photoresist is
Compared with prior art, the present invention has the following advantages:
The barrier bed of BARC laminar surface deposit one deck densification that double mosaic structure manufacture method of the present invention covers on ILD.This layer barrier bed can stop the nitrogen ion in the cover layer to contact with photoresist, thereby prevented the generation of photoresist intoxicating phenomenon.Simultaneously, this barrier bed also can be used as the hard mask layer in the etching groove process, when utilizing the BARC layer as etching sacrificial layer, in conjunction with the effect of hard mask layer, can an etching form dual-damascene structure.And photoresist is removed in etching process, only need remove remaining BARC after the etching, has simplified manufacturing process.In addition, because the hard mask effect of above-mentioned barrier bed, it is very thick that photoresist need not to be coated with, and helps further improving etching resolution.
Description of drawings
Fig. 1 to Fig. 5 is the existing generalized section of making the dual-damascene structure method of explanation;
Fig. 6 to Figure 10 is the generalized section according to the dual-damascene structure manufacture method of the embodiment of the invention;
Figure 11 is the flow chart of dual-damascene structure manufacture method of the present invention.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, the specific embodiment of the present invention is described in detail below in conjunction with accompanying drawing.
The bottom anti-reflection layer surface deposition that double mosaic structure manufacture method of the present invention covers on interlayer dielectric layer the barrier bed of one deck densification, stoping the nitrogen ion in the cover layer to contact, thereby prevented the generation of photoresist intoxicating phenomenon with photoresist.
Fig. 6 to Figure 10 is the generalized section according to the dual-damascene structure manufacture method of the embodiment of the invention.At first, as shown in Figure 6, and with reference to Fig. 1, Fig. 2 and Fig. 3, described schematic diagram is an example, and it should excessively not limit the scope of protection of the invention at this.Utilize chemical vapor deposition (CVD) method to form first dielectric layer on Semiconductor substrate 10 surfaces, just metal intermetallic dielectric layer 11.The material of dielectric layer can be silica.In dielectric layer 11, form for example the conductive connecting line 12a and the 12b of copper conductor formation by photoetching, etching technics.Utilize cmp (CMP) technology with dielectric layer 11 and copper conductive connecting line 12a and 12b surface rubbing; Then, utilize CVD technology, at the cover layer 13 that above-mentioned dielectric layer 11 and copper conductive connecting line 12a and 12b surface deposition are made up of silicon nitride, cover layer 13 can be silicon nitride (Si
3N
4) or silicon oxynitride (SiON), or nitrogen silicon oxide carbide (SiOCN) thickness is
Above-mentioned cover layer 13 is taken as etching stopping layer on the other hand on the one hand as the diffusion cover layer of copper among conductive connecting line 12a and the 12b in the step of subsequent etching connecting hole.Then, form thickness at above-mentioned cover layer 13 surface depositions
Second dielectric layer, just interlayer dielectric layer 14, as shown in Figure 1.The interlayer dielectric layer 14 of above-mentioned deposition is that for example Material Used (Applied Materials) house mark is the silicon dioxide (SiO of black diamond (black diamond) by the inorganic silicon matrix layer (Inorganic silicon based layer) of the low-k of CVD (Chemical Vapor Deposition) method deposition
2), silicon oxide carbide (SiCO) or fluorinated silica glass (FSG).
Utilize technologies such as photoetching, etching in interlayer dielectric layer 14, to form connecting hole 15a and 15b, as shown in Figure 2.Then, in interlayer dielectric layer 14 surface-coated BARC layer 16, just bottom anti-reflection layer.This BARC layer 16 is filled among connecting hole 15a and the 15b, and described BARC layer at interlayer dielectric layer 14 lip-deep thickness is
Present embodiment is preferably
As shown in Figure 3.
Subsequently, the inventive method is at the barrier bed 19 of BARC layer 16 surface deposition one deck densification, and its thickness exists
Between, as shown in Figure 6.Described barrier bed 19 is to utilize plasma-reinforced chemical vapor deposition (PECVD) technology, carries out the low temperature deposition silica (LTO) of deposit under cryogenic conditions.The technological temperature scope of above-mentioned deposit low temperature deposition oxide barrier bed 19 need be controlled between 150 ℃-300 ℃, and present embodiment is preferably 200 ℃.In addition, barrier bed 19 also can be by the Silicon-rich polymeric material, and for example the trade mark of company of SHIN-ETSU HANTOTAI (Shinetzu) is the Silicon-rich polymeric material of SHB, forms in BARC layer 16 surperficial spin coating (spin on) technology, and thickness is
Next, as shown in Figure 7, at barrier bed 19 painting photoresists, and utilize photoetching process, for example expose, development etc. forms photoresist layer 17a and the 17b with groove opening pattern on the surface of photoresist.In the present embodiment, the thickness of photoresist layer 17a and 17b is
Above-mentioned photoresist layer 17a and 17b, barrier bed 19 and BARC layer 16 are formed three-decker.Barrier bed 19 can prevent that the nitrogen ion in the cover layer 13 from contacting with 17b with photoresist 17a, thereby has prevented the generation of photoresist intoxicating phenomenon.Simultaneously, this barrier bed 19 also can be used as the hard mask layer in the etching groove process, when utilizing BARC layer 16 as etching sacrificial layer, in conjunction with the mask effect of barrier bed 19, can an etching form dual-damascene structure.And photoresist 17a and 17b are removed in etching process, only need remove remaining BARC after the etching, have simplified manufacturing process.In addition, because the hard mask effect of above-mentioned barrier bed, it is very thick that photoresist need not to be coated with, and helps further improving etching resolution.
Next continuation, utilizes reactive ion etching process (reactive ion etching with reference to Fig. 8; RIE), utilize photoresist 17a and 17b and barrier bed 19, carry out etching via the opening figure that photoresist 17a and 17b limit as mask.Because the hard mask effect of barrier bed 19, photoresist need not to be coated with very thickly, helps further improving etching resolution.In etching process, etching agent comprises chlorine Cl
2, oxygen O
2, nitrogen N
2, helium He and oxygen O
2Mist, perhaps helium one oxygen He-O
2, and inert gas or its mist (such as hydrogen Ar, neon Ne, helium He or the like), or its combination.Flow is 40-80sccm, and plasma source power output 200-2000W, underlayer temperature are controlled between 20 ℃ and 80 ℃, and chamber pressure is 5-50mTorr.Utilize photoresist 17a and 17b to be mask etching barrier bed 19 and BARC layer 16.While RIE is etching photoresist 17a and 17b also.Certainly, the etch rate of RIE in barrier bed 19 and BARC layer 16, variant slightly with the etch rate among photoresist 17a and the 17b.When photoresist 17a and 17b are etched into the surface of barrier bed 19, when just photoresist 17a and 17b were etched away, RIE had etched into barrier bed 19 and BARC layer 16 surface of interlayer dielectric layer 14 through opening figure.
Then, as shown in Figure 9, while etching barrier bed 19 and BARC layer 16, barrier bed 19 has the effect of mask concurrently.Utilize the mask effect of barrier bed 19 to begin etching interlayer dielectric layer 14.Because barrier bed 19 is high dense film, the RIE etching is lower to the etch rate of barrier bed 19, and BARC layer 16 is a low density material, and interlayer dielectric layer 14 is a low k material, and density is lower and quality is softer, and RIE is higher to the etch rate of these two kinds of materials.Therefore, simultaneously when etching barrier bed 19, BARC layer 16 and interlayer dielectric layer 14, the amount that the amount that BARC layer 16 and interlayer dielectric layer 14 are etched is etched much larger than barrier bed 19, barrier bed 19 is etched away back BARC layer 16 and interlayer dielectric layer 14 fully and has been etched away half height of the interlayer dielectric layer 14 dark degrees of approach.
In ensuing processing step, as shown in figure 10, utilize wet corrosion technique or oxygen plasma cineration technics (ashing) to remove remaining BARC layer 16 in interlayer dielectric layer 14 surfaces and the groove, with the cover layer 13 that exposes channel bottom.At last, utilize pecvd process, the part of the cover layer 13 of conductive connecting line 12a and 12b correspondence in the dielectric layer 11 of substrate 10 is removed,, in connecting hole and groove, fill metal then and just formed dual-damascene structure so that expose conductive connecting line 12a and 12b.
Figure 11 is the flow chart of dual-damascene structure manufacture method of the present invention.As shown in figure 11, double mosaic structure manufacture method of the present invention comprises: the Semiconductor substrate that provides a surface to have dielectric layer forms metal interconnecting wires (S101) in described dielectric layer; Described dielectric layer of planarization and described metal interconnecting wires (S102); Form by silicon nitride (Si at described dielectric layer and described conductive structure laminar surface
3N
4) or the cover layer (S103) formed of silicon oxynitride (SiON) or fire sand (SiCN), thickness is
On described cover layer, form interlayer dielectric layer (S104), interlayer dielectric layer can be the silicon oxide carbide (SiCO) of black diamond by Material Used (AppliedMaterials) house mark, silica or fluorinated silica glass (FSG) are formed, and the thickness of interlayer dielectric layer is 1000-
In described interlayer dielectric layer, form connecting hole (S105); Cover bottom anti-reflection layer (S106) on the interlayer dielectric layer of connecting hole having; Form barrier bed (S107) at described bottom anti-reflection layer surface deposition, described barrier bed is to utilize plasma-reinforced chemical vapor deposition process deposit in 150 ℃～300 ℃ temperature range to form, or for SHIN-ETSU HANTOTAI (Shinetzu) house mark is that the Silicon-rich polymer of SHB utilizes spin coating (spin-on) technology to form, thickness is
Apply photoresist and the described photoresist of patterning with definition groove opening (S108); Described photoresist of etching and described barrier bed (S109); The described barrier bed of etching, bottom anti-reflection layer and interlayer dielectric layer (S110); Remove the cover layer (S111) of the corresponding described interconnection line of remaining bottom anti-reflection layer and channel bottom position, in connecting hole and groove, fill metal then and just formed dual-damascene structure.
Double mosaic structure manufacture method of the present invention can stop the nitrogen ion in the cover layer to contact with photoresist, thereby prevent the generation of photoresist intoxicating phenomenon by the barrier bed of BARC laminar surface deposit one deck densification of covering on ILD.Simultaneously, this barrier bed also can be used as the hard mask layer in the etching groove process, when utilizing the BARC layer as etching sacrificial layer, in conjunction with the effect of hard mask layer, can an etching form dual-damascene structure.
Though the present invention with preferred embodiment openly as above; but it is not to be used for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can make possible change and modification, so protection scope of the present invention should be as the criterion with the scope that claim of the present invention was defined.
Claims (8)
1, a kind of double mosaic structure manufacture method comprises:
The Semiconductor substrate that provides a surface to have dielectric layer forms metal interconnecting wires in described dielectric layer;
Described dielectric layer of planarization and described metal interconnecting wires;
Form cover layer at described dielectric layer and described metal interconnecting wires surface;
On described cover layer, form interlayer dielectric layer, in described interlayer dielectric layer, form connecting hole;
Cover bottom anti-reflection layer having on the interlayer dielectric layer of connecting hole;
Form barrier bed at described bottom anti-reflective laminar surface;
At described barrier bed surface-coated photoresist and the described photoresist of patterning with the definition groove opening;
With described photoresist of reactive ion etching process etching and barrier bed, then etching photoresist and bottom anti-reflection layer, and then the described barrier bed of etching, bottom anti-reflection layer and interlayer dielectric layer, etched away fully until barrier bed, this moment, the bottom anti-reflection layer and the interlayer dielectric layer of groove opening part were etched into the height of interlayer dielectric layer depth near half;
Remove remaining bottom anti-reflection layer with wet corrosion technique or oxygen plasma cineration technics;
Remove the cover layer of the corresponding described interconnection line of channel bottom position;
In connecting hole and groove, fill metal then and just formed dual-damascene structure.
2, the method for claim 1 is characterized in that: described barrier bed is to utilize plasma-reinforced chemical vapor deposition process deposit in 150 ℃～300 ℃ temperature range to form.
3, the method for claim 1 is characterized in that: described barrier bed is the Silicon-rich polymer, utilizes spin coating (spin-on) technology to form, and thickness is
4, method as claimed in claim 1 or 2 is characterized in that: described barrier bed is a silica, and thickness is
5, the method for claim 1 is characterized in that: described interlayer dielectric layer is silicon oxide carbide (SiCO), silica or fluorinated silica glass, and thickness is
6, the method for claim 1 is characterized in that: described cover layer is silicon nitride or silicon oxynitride or nitrogen silicon oxide carbide, and thickness is
7, the method for claim 1 is characterized in that: the thickness that is positioned at the lip-deep described bottom anti-reflection layer of described interlayer dielectric layer is
8, the method for claim 1 is characterized in that: the thickness of described photoresist layer is
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Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101625993B (en) * | 2008-07-08 | 2011-05-11 | 中芯国际集成电路制造(上海)有限公司 | Dual-damascene structure and manufacturing method thereof |
| CN101840858B (en) * | 2009-03-20 | 2012-05-23 | 中芯国际集成电路制造(上海)有限公司 | Method for removing anti-reflective coating in top-level metallic dielectric layer groove etching process |
| CN102087993B (en) * | 2009-12-04 | 2013-01-23 | 中芯国际集成电路制造(上海)有限公司 | Groove forming method |
| CN102201365B (en) * | 2010-03-22 | 2014-06-04 | 中芯国际集成电路制造(上海)有限公司 | Method for producing semiconductor device |
| CN102270601A (en) * | 2010-06-04 | 2011-12-07 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing dual damascene structure |
| CN102299099B (en) * | 2010-06-25 | 2014-11-05 | 上海华虹宏力半导体制造有限公司 | Forming method of semiconductor structure and semiconductor structure |
| CN104253038B (en) * | 2013-06-30 | 2017-05-10 | 无锡华润上华科技有限公司 | Method for improving isolation of interlayer dielectric layer of semiconductor device |
| CN111399098A (en) * | 2019-06-05 | 2020-07-10 | 江西师范大学 | Sunlight anti-reflector and preparation method thereof |
| CN112349650A (en) * | 2019-08-06 | 2021-02-09 | 芯恩（青岛）集成电路有限公司 | Damascus structure and preparation method thereof |
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