CN101840858B - Method for removing anti-reflective coating in top-level metallic dielectric layer groove etching process - Google Patents
Method for removing anti-reflective coating in top-level metallic dielectric layer groove etching process Download PDFInfo
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- CN101840858B CN101840858B CN2009100479513A CN200910047951A CN101840858B CN 101840858 B CN101840858 B CN 101840858B CN 2009100479513 A CN2009100479513 A CN 2009100479513A CN 200910047951 A CN200910047951 A CN 200910047951A CN 101840858 B CN101840858 B CN 101840858B
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Abstract
The invention provides a method for removing an anti-reflective coating in a top-level metallic dielectric layer groove etching process and a method for manufacturing a top-level metallic dielectric layer groove by utilizing the technology. The anti-reflective coating in the top-level metallic dielectric layer groove is removed by chlorine etching. The invention can effectively avoid barrier defects and facet defects appearing in the top-level metallic dielectric layer groove manufacturing process.
Description
Technical field
The present invention relates to semiconductor product and make the field, and be particularly related to the method for removing the method for ARC in a kind of top-level metallic dielectric layer groove etching process and utilizing this technology manufacturing top-level metallic dielectric layer groove.
Background technology
In recent years, along with the development of semiconductor integrated circuit manufacturing technology, the quantity of contained device constantly increases in the chip, and size of devices is also constantly dwindled because of the lifting of integrated level, and the line width that uses on the production line has got into the tiny scope of inferior micron.Yet no matter how downsizing of device size still must have suitably insulation or isolates between each device in chip, can obtain good device performance.This technology is commonly referred to as device separation (device isolation technology); Its main purpose is between each device, to form spacer; And under the situation of guaranteeing the good effect; Dwindle the zone of spacer as far as possible, hold more device to vacate more chip area.A kind of method that is used on semiconductor chip forming the structure that each electric conducting material is electrically insulated from each other out is a photoetching process.Photoetching technique comprises coating, exposure and step of developing.With positivity or negativity photoresistance coated wafers, in technology subsequently, immediately with defining the mask covering of waiting to keep or wait to remove pattern.With after the mask appropriate location, pass mask with the monochromatic radiation beam direction again, thereby the photoresist that makes exposure is prone to more or more is insoluble in the selected rinsing solution, said monochromatic radiation light beam is ultraviolet (UV) light or deep ultraviolet (DUV) light (250nm) for example.Then soluble photoresist is removed, or " development ", thereby stay the pattern identical with mask.Current, four kinds of radiation development wavelength that are used for the photoetching industry are arranged, 436nm, 365nm, 248nm and 193nm, people's effort recently focuses on the 157nm photoetching process.In theory, along with wavelength reduces, on semiconductor chip, can produce littler characteristic size.But owing to the reflectivity and the lithographic wavelength of semiconductor chip is inversely proportional to, thereby the photoresistance of interference and inhomogeneous exposure has limited the consistency of feature sizes of semiconductor devices.
For example when being exposed to the DUV radiation, the transmittance of photoresistance is added substrate and is caused the DUV radiation to be reflected back toward in the photoresistance to the highly reflective of DUV wavelength, thereby in photoresistance, produces standing wave.Standing wave causes further photochemical reaction in photoresistance, thereby causes the inhomogeneous exposure of photoresistance, comprises the mask exposure partly of not planning to be exposed to radiation, and this causes the variation of live width, spacing and other characteristic sizes.In order to solve transmission and reflection problems, people have developed bottom antireflective coating (BARC), before using photoresistance, this bottom antireflective coating are coated on substrate.BARC comprises silicon oxynitride, and it adopts the CVD deposition technique and deposits, thereby has realized that the conformal of substrate covers, and the BARC layer has good homogeneous thickness simultaneously.When photoresistance was exposed to the DUV radiation, BARC absorbed the DUV radiation of a great deal of, thereby had prevented the reflection and the standing wave of radiation.BARC has reduced transmittance and reflectivity through destructive interference, has wherein offset from the light of BARC-substrate interface reflection from the light of BARC-photoresistance boundary reflection.
The conventional method of removing BARC in the prior art comprises dry ecthing, for example adopts additive such as CF4, CHF3, C2F6, C4F8, O2, CO and Ar gas-plasma etching.Yet there is certain risk in this method, causes device to produce the defective of different situations easily.Fig. 1～shown in Figure 4 is each step sketch map of top-level metallic dielectric layer groove manufacturing approach in the prior art; With the fluorine silex glass top-level metallic dielectric layer groove in the 90nm technology (FSG TM trench) manufacturing process is example; It deposits the SiN layer as barrier layer 10 on Semiconductor substrate; Be formed with fsg layer 20 on the SiN layer; Wherein have intermediate barrier layers in the fsg layer 20 as etching stopping layer 30, fsg layer 20 has opening and forms groove 25, and deposits the SiON layer on the fsg layer 20 as passivation layer 40; At first on groove 25 and passivation layer 40, apply BARC layer 50 when making FSG TM trench; The etch-back of carrying out BARC layer 50 is afterwards removed the BARC layer 50 on the passivation layer 40 and groove 25 inner BARC layers 50 is reduced to certain altitude, utilizes the photoresistance 60 on the passivation layer 40 to carry out exposure imaging then, carry out again the top-level metallic dielectric layer etching remove do not covered by photoresistance 60 and etching stopping layer 30 on passivation layer 40, fsg layer 20 and BARC zone 50; Carry out etched linear removal of top-level metallic dielectric layer at last and handle, thereby remove the BARC layer 50 of groove 25 parts and the technological process that SiN layer 10 is accomplished whole FSG TM trench.Yet when using prior art to carry out the top-level metallic dielectric layer etching; Because the etch-rate of BARC layer 50 and the etch-rate of fsg layer 20 and inequality; Make the height of BARC layer 50 in groove 25 is difficult to control; When remaining the excessive height of BARC layer 50, can cause the barrier defective (to please refer to Fig. 5; Barrier defective sketch map for after the top-level metallic dielectric layer etching, producing in the prior art shown in Figure 5), spend and when the height of residue BARC layer 50 and to cause facet defective (please refer to Fig. 7, shown in Figure 7 is the facet defective sketch map that after the top-level metallic dielectric layer etching, produces in the prior art) when low easily; More than two kinds of defectives all can handle further aggravation of back etched linear removal of top-level metallic dielectric layer; Please refer to Fig. 6 and Fig. 8, shown in Figure 6 is that the barrier defective is removed the sketch map after handling in linearity in the prior art, and shown in Figure 8 is that the facet defective is removed the sketch map after handling in linearity in the prior art.
Summary of the invention
The present invention proposes in a kind of top-level metallic dielectric layer groove etching process to remove the method for ARC and utilizes this technology to make the method for top-level metallic dielectric layer groove, and it can effectively avoid the barrier defective and the facet defective that occur in the top-level metallic dielectric layer groove manufacturing process.
In order to achieve the above object, the present invention proposes to remove in a kind of top-level metallic dielectric layer groove etching process the method for ARC, and wherein, this method uses the chlorine etching to remove the ARC in the top-level metallic dielectric layer groove.
In order to achieve the above object; The present invention more proposes a kind of top-level metallic dielectric layer groove manufacturing approach, and the steps include: provides the device of handling through shallow trench isolation, and said device deposits the barrier layer on Semiconductor substrate; And on said barrier layer, be formed with the top-level metallic dielectric layer layer; Wherein have etching stopping layer in the middle of the top-level metallic dielectric layer layer, the top-level metallic dielectric layer layer is formed with groove simultaneously, and deposits passivation layer on the top-level metallic dielectric layer layer; Then on groove and passivation layer, apply ARC; Carry out the etch-back of ARC afterwards, remove the ARC on the passivation layer, and the ARC that groove is inner is reduced to certain altitude; Utilize the photoresistance on the passivation layer to carry out exposure imaging then; Carrying out the top-level metallic dielectric layer etching again removes and not to be covered by photoresistance and passivation layer, top-level metallic dielectric layer layer and the ARC of intermediate barrier layers top; Remove photoresistance and carry out the wet clean process device; Carry out etched linear removal of top-level metallic dielectric layer at last and handle, remove the ARC and the barrier layer of trench portions, wherein, use the chlorine etching to remove the ARC in the top-level metallic dielectric layer groove in the top-level metallic dielectric layer etching.
Remove the method for ARC in the top-level metallic dielectric layer groove etching process that the present invention proposes and utilize this technology to make the method for top-level metallic dielectric layer groove; Use the chlorine etching to remove the ARC in the top-level metallic dielectric layer groove; Because ARC is that oxide layer can be by the chlorine etching; And etching stopping layer be silicon nitride layer basically can be by the chlorine etching; Therefore adopt the method for removal ARC of the present invention to avoid barrier defective or facet generation of defects, improved the yield of device production, thereby increased output and reduced production cost.
Description of drawings
Fig. 1～shown in Figure 4 is each step sketch map of top-level metallic dielectric layer groove manufacturing approach in the prior art.
Barrier defective sketch map for after the top-level metallic dielectric layer etching, producing in the prior art shown in Figure 5.
Shown in Figure 6 is that the barrier defective is removed the sketch map after handling in linearity in the prior art.
Facet defective sketch map for after the top-level metallic dielectric layer etching, producing in the prior art shown in Figure 7.
Shown in Figure 8 is that the facet defective is removed the sketch map after handling in linearity in the prior art.
Shown in Figure 9 is the flow chart of the top-level metallic dielectric layer groove manufacturing approach of preferred embodiment of the present invention.
Embodiment
In order more to understand technology contents of the present invention, special act specific embodiment also cooperates appended illustrating as follows.
The present invention proposes in a kind of top-level metallic dielectric layer groove etching process to remove the method for ARC and utilizes this technology to make the method for top-level metallic dielectric layer groove, and it can effectively avoid the barrier defective and the facet defective that occur in the top-level metallic dielectric layer groove manufacturing process.
In order to achieve the above object, the present invention proposes to remove in a kind of top-level metallic dielectric layer groove etching process the method for ARC, and wherein, this method uses the chlorine etching to remove the ARC in the top-level metallic dielectric layer groove.
Please refer to Fig. 9, shown in Figure 9 is the flow chart of the top-level metallic dielectric layer groove manufacturing approach of preferred embodiment of the present invention.The present invention proposes a kind of top-level metallic dielectric layer groove manufacturing approach, the steps include:
Step S10: the device of handling through shallow trench isolation is provided;
Step S20: on groove and passivation layer, apply ARC;
Step S30: the etch-back of carrying out ARC;
Step S40: utilize the photoresistance on the passivation layer to carry out exposure imaging;
Step S50: carry out the top-level metallic dielectric layer etching;
Step S60: remove photoresistance and carry out the wet clean process device;
Step S70: carry out etched linear removal of top-level metallic dielectric layer and handle.
Among the step S10; The said device of handling through shallow trench isolation deposits the barrier layer on Semiconductor substrate; And on said barrier layer, be formed with the top-level metallic dielectric layer layer; Wherein have etching stopping layer in the middle of the top-level metallic dielectric layer layer, the top-level metallic dielectric layer layer is formed with groove simultaneously, and deposits passivation layer on the top-level metallic dielectric layer layer.Among the step S30, the etch-back of ARC is the ARC on the removal passivation layer, and the ARC that groove is inner is reduced to certain altitude.Among the step S50; Top-level metallic dielectric layer is etched to that removal is not covered by photoresistance and passivation layer, top-level metallic dielectric layer layer and the ARC of intermediate barrier layers top; Wherein, use the chlorine etching to remove the ARC in the top-level metallic dielectric layer groove in the top-level metallic dielectric layer etching.Among the step S60, use the wet clean process device can use ST250 equipment to carry out wet-cleaned, use washed with de-ionized water, and via IPA (isopropyl alcohol)/N
2Be rotated drying.Among the step S70, etched linear removal of top-level metallic dielectric layer is treated to the ARC and the barrier layer of removing trench portions.The preferred embodiment according to the present invention, said barrier layer and etching stopping layer are silicon nitride layer, and said top-level metallic dielectric layer layer is a fsg film, and said passivation layer is a silicon oxynitride layer.
Among the step S50; The flow of the employed chlorine of ARC in the top-level metallic dielectric layer etched trench is 100～200 mark condition milliliter per minutes; Said chlorine etch processes temperature is 55 ℃～65 ℃; The chlorine disposing time is 160s～200s, and specifically the height requirement with the ARC in the working control groove decides.Using chlorine to carry out the inner anti-radiation coating etching of groove is because the speed of its etching oxide layer is slower; Control the residual altitude of ARC easily; Make the height of the ARC in the top-level metallic dielectric layer groove can be not too high can be not low excessively yet; And use chlorine can not produce etch effect to silicon nitride layer as etching stopping layer; Can not produce silicon nitride layer and ARC and cause barrier defective and facet defective because etch-rate is inconsistent; Therefore can effectively avoid the barrier defective and the facet defective that occur in the top-level metallic dielectric layer groove manufacturing process, finally improve the yield of device production, thereby increased output and reduced production cost.
Though the present invention discloses as above with preferred embodiment, so it is not in order to limit the present invention.Have common knowledge the knowledgeable in the technical field under the present invention, do not breaking away from the spirit and scope of the present invention, when doing various changes and retouching.Therefore, protection scope of the present invention is as the criterion when looking claims person of defining.
Claims (7)
1. top-level metallic dielectric layer groove manufacturing approach; The steps include: to provide the device of handling through shallow trench isolation; Said device deposits the barrier layer on Semiconductor substrate, and on said barrier layer, is formed with the top-level metallic dielectric layer layer, wherein has etching stopping layer in the middle of the top-level metallic dielectric layer layer; The top-level metallic dielectric layer layer is formed with groove simultaneously, and deposits passivation layer on the top-level metallic dielectric layer layer; Then on groove and passivation layer, apply ARC; Carry out the etch-back of ARC afterwards, remove the ARC on the passivation layer, and the ARC that groove is inner is reduced to certain altitude; Utilize the photoresistance on the passivation layer to carry out exposure imaging then; Carrying out the top-level metallic dielectric layer etching again removes and not to be covered by photoresistance and passivation layer, top-level metallic dielectric layer layer and the ARC of intermediate barrier layers top; Remove photoresistance and carry out the wet clean process device; Carry out etched linear removal of top-level metallic dielectric layer at last and handle, remove the ARC and the barrier layer of trench portions, it is characterized in that using in the top-level metallic dielectric layer etching chlorine etching to remove the ARC in the top-level metallic dielectric layer groove.
2. top-level metallic dielectric layer groove manufacturing approach according to claim 1 is characterized in that, the flow of said chlorine is 100～200 mark condition milliliter per minutes.
3. top-level metallic dielectric layer groove manufacturing approach according to claim 1 is characterized in that, said chlorine etch processes temperature is 55 ℃～65 ℃.
4. top-level metallic dielectric layer groove manufacturing approach according to claim 1 is characterized in that, said chlorine disposing time is 160s～200s.
5. top-level metallic dielectric layer groove manufacturing approach according to claim 1 is characterized in that, said barrier layer and etching stopping layer are silicon nitride layer.
6. top-level metallic dielectric layer groove manufacturing approach according to claim 1 is characterized in that, said top-level metallic dielectric layer layer is a fsg film.
7. top-level metallic dielectric layer groove manufacturing approach according to claim 1 is characterized in that, said passivation layer is a silicon oxynitride layer.
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| CN2009100479513A CN101840858B (en) | 2009-03-20 | 2009-03-20 | Method for removing anti-reflective coating in top-level metallic dielectric layer groove etching process |
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| CN101840858B true CN101840858B (en) | 2012-05-23 |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1979813A (en) * | 2005-12-05 | 2007-06-13 | 旺宏电子股份有限公司 | Manufacturing method for phase change ram with electrode layer process |
| CN101123243A (en) * | 2006-08-10 | 2008-02-13 | 中芯国际集成电路制造(上海)有限公司 | Making method for dual enchasing structure |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1979813A (en) * | 2005-12-05 | 2007-06-13 | 旺宏电子股份有限公司 | Manufacturing method for phase change ram with electrode layer process |
| CN101123243A (en) * | 2006-08-10 | 2008-02-13 | 中芯国际集成电路制造(上海)有限公司 | Making method for dual enchasing structure |
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| JP特开2000-150477A 2000.05.30 |
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