CN101055421A - Method for forming double inserted structure - Google Patents
Method for forming double inserted structure Download PDFInfo
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- CN101055421A CN101055421A CN 200610025649 CN200610025649A CN101055421A CN 101055421 A CN101055421 A CN 101055421A CN 200610025649 CN200610025649 CN 200610025649 CN 200610025649 A CN200610025649 A CN 200610025649A CN 101055421 A CN101055421 A CN 101055421A
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Abstract
The present invention provides a forming method for dual damascene structure including: providing a semi-conductor substrate with conductive structures and forming an inner layer dielectric layer on the substrate; forming a first photoresist layer having contact hole graph on the inner layer dielectric layer; forming a second photoresist layer having groove hatch graph on the first photoresist layer; etching the graphs of the first photoresist layer and the second photoresist layer until exposing the conductive structures; and filling the dual damascene structure with metal materials. The forming method for the dual damascene structure of the invention omits the step of forming anti-reflection layer, improves the two to three times of etching technics in existing technology to only one etching clean in order to form the dual damascene structure. The forming method for the dual damascene structure of the invention can form excellent dual damascene structure, simplify the manufacturing technics and reduce the cost of manufacture.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, the formation method of particularly a kind of dual-damascene structure (dualdamascene structure).
Background technology
Along with the manufacturing develop rapidly of semiconductor devices, semiconductor devices CMOS has had the deep-submicron structure, comprises the semiconductor element of enormous quantity among the SIC (semiconductor integrated circuit) IC.In this large scale integrated circuit, the high-performance between the element, highdensity connection not only interconnect in single interconnection layer, and will interconnect between multilayer.Therefore, provide multilayer interconnect structure usually, wherein a plurality of interconnection layers pile up mutually, and interlayer dielectric places therebetween, are used to connect semiconductor element.When particularly utilizing dual damascene (dual-damascene) technology to form multilayer interconnect structure, in interlayer dielectric, form interconnected groove and connecting hole in advance, then with conductive material for example copper (Cu) fill described interconnected groove and connecting hole.
Dual-damascene technics is a kind of method that can form the stacked on top structure of plain conductor and connector (plug) simultaneously, with different elements and the lead that is used for connecting each interlayer in the semiconductor wafer, and utilize the core dielectric material (inter-layer dielectrics ILD) around it isolated with other element.The major technique of dual-damascene technics focuses on the lithographic technique that the groove that conductor metal uses is filled in etching, in the leading portion etch process of dual-damascene technics, exist two kinds of methods to make the groove of double-embedded structure at present, first method is to define the lead groove on the top of dielectric layer earlier, utilize another photoresist layer definition interlayer hole opening afterwards, this method is because the density of lead groove is quite high, make the surface irregularity of the photoresist layer be used to define the interlayer hole opening, had a strong impact on the branch pigtail rate of exposure imaging technology.
Another kind method is at first to define the interlayer hole opening that penetrates dielectric layer fully in dielectric layer, utilize another photoresist layer definition lead groove then, before the coating photoresist layer, can be coated with one deck anti-reflecting layer earlier, to improve the branch pigtail rate of exposure imaging technology.Fig. 1 to Fig. 5 is the dual damascene leading portion etch process synoptic diagram that forms the medium window earlier.As shown in Figure 1, have on the substrate of metal carbonyl conducting layer 10 one, the material that wherein is used to form metal carbonyl conducting layer 10 can be copper, below is to be that example describes with copper conductor layer 10.Then, on this copper conductor layer 10, form an overlayer 12, in order to avoid copper conductor layer 10 to be exposed in the oxygen or in other aggressive chemistry technology, the material of carrying out cap rock 11 can be silicon nitride, its formation method can be plasma-reinforced chemical vapor deposition method (PECVD), and its thickness is about about 300-1000 .Then, form an inner layer dielectric layer (ILD) 12 on overlayer 11, its material can be monox, fluorinated silicon oxide or silicon oxide carbide, and its thickness is about about 4000-12000 .Form an anti-reflecting layer 13 on ILD layer 12, its material can be SiON, TiN, TaN or other material, and its thickness is about about 200-900 .Then on anti-reflecting layer 13, form one deck photoresist layer 14, wherein have the pattern of dielectric layer window.As shown in Figure 2, be etching mask with photoresist layer 14, the dielectric layer pattern of windows of photoresist layer 14 is transferred in anti-reflecting layer 13 and the ILD layer 12.Formed dielectric layer window penetrates ILD layer 12 fully, and exposes the surface of the overlayer 11 of its below, promptly has complete dielectric layer window in the ILD layer 12, removes photoresist layer 14 then.As shown in Figure 3, cover one deck photoresist again on anti-reflecting layer 13, this photoresist might be inserted in the dielectric layer window, behind exposure imaging, forms the photoresist layer 20 of the pattern with lead groove.At this moment, come out in the surface of part anti-reflecting layer 13, and part photoresist layer 20 still fills in the dielectric layer window.As shown in Figure 4, carry out etch process, the lead channel patterns in the photoresist layer 20 is transferred to the top of anti-reflecting layer 13 and ILD layer 12, have the double-mosaic pattern of lead groove and dielectric layer window 22 with formation.But because in the dielectric layer window that antireflection material and photoresist material form before can inserting, and the anti-anti-envelope material of dielectric layer window sidewall can with dielectric layer etching agent reaction, on the sidewall of dielectric layer window 22, generate the attachment of organic material.When follow-up reactive ion etching (RIE) technology was removed photoresist layer 20, this attachment can hinder the etching of dielectric medium on every side, after etching away photoresist layer 20, can form so-called fence (fence) 24, as shown in Figure 5.
This fence can hinder inserting of metal material, and forms the irregularly shaped of plain conductor easily in double-mosaic pattern.In addition, the existence of fence can cause electric current in lead and the mobile obstacle of dielectric layer window connector (plug), and easily forms the electron transfer hole and reduce reliability.These problems all can have a strong impact on the quality of multi-layer conductor leads and dielectric layer window connector.
Summary of the invention
Therefore, the object of the present invention is to provide a kind of formation method of dual-damascene structure, removed the formation step of anti-reflecting layer, form dual-damascene structure, to solve problems of the prior art by an etching.
For achieving the above object, the formation method of dual-damascene structure of the present invention comprises:
The Semiconductor substrate that provides a surface to have conductive structure forms inner layer dielectric layer on substrate;
On described inner layer dielectric layer, form first photoresist layer with contact hole graph;
On described first photoresist layer, form second photoresist layer with groove opening figure;
The described figure of described first photoresist layer of etching and second photoresist layer is till exposing described conductive structure;
Fill metal material and form dual-damascene structure.
Described method also is included in and forms tectal step between described substrate surface and the described inner layer dielectric layer.
Described first photoresist layer is a negative photoresist, and described second photoresist layer is a positive photoresist.
Described first photoresist layer is a positive photoresist, and described second photoresist layer is a negative photoresist.
The thickness of described first photoresist layer is 1000-8000 .
The thickness of described second photoresist layer is 1000-8000 .
Described inner layer dielectric layer is black diamond (black diamond), silicon dioxide (SiO
2) or fluorinated silica glass (FSG).
The thickness of described inner layer dielectric layer is 2000-12000 .
Described overlayer is silicon nitride (Si
3N
4) or silicon oxynitride (SiON), or fire sand (SiCN) thickness is 200-1200 .
The technology of described etching is reactive ion etching (RIE) technology.
Compared with prior art, the present invention has the following advantages:
The formation method of dual-damascene structure of the present invention at first is being formed with formation one deck overlayer and inner layer dielectric layer on the Semiconductor substrate of conductive structure, apply the negative photoresist of the corresponding conductive structure connecting through hole of one deck opening then, on this negative photoresist, form the positive photoresist of the corresponding via openings conductive trench of one deck again.Subsequently, utilize primary first-order equation ion etching technology etching negative photoresist and positive photoresist, with the figure transfer of negative photoresist and positive photoresist in inner layer dielectric layer, continue the above-mentioned overlayer of etching, expose metallic conduction structure, in through hole and groove, fill metal material at last, thereby form the interconnection dual-damascene structure.The formation method of dual-damascene structure of the present invention has been saved the step that forms anti-reflecting layer, two to three etching cleanings in the prior art is improved to only to clean through an etching just form dual-damascene structure.The formation method of dual-damascene structure of the present invention can form good dual-damascene structure, and has simplified manufacturing process, has reduced production cost.
Description of drawings
Fig. 1 to Fig. 5 is the dual damascene leading portion etch process synoptic diagram that forms the medium window earlier;
Fig. 6 to Figure 13 is the process section of explanation dual-damascene structure formation method of the present invention;
Figure 14 is the process flow diagram of dual-damascene structure formation method of the present invention.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, the specific embodiment of the present invention is described in detail below in conjunction with accompanying drawing.
Fig. 6 to Figure 10 is the process section of explanation dual-damascene structure formation method of the present invention.As shown in Figure 6, utilize chemical vapour deposition (CVD) method to form dielectric layer 202 on surface, the semiconductor-based ends 200, the material of dielectric layer can be silicon oxide compounds.In dielectric layer 202, form for example conductive structure 203 of copper conductor formation by photoetching, etching technics.Utilize cmp (CMP) technology with dielectric layer 202 and copper conductive structure 203 surface rubbings; Then, utilize CVD technology, at the overlayer 204 that above-mentioned dielectric layer 202 and copper conductive structure 203 surface depositions are made up of silicon nitride, overlayer is silicon nitride (Si
3N
4) or silicon oxynitride (SiON), or fire sand (SiCN) thickness is 200-1200 .Above-mentioned overlayer 204 also is taken as etching stopping layer at subsequent step.Then, form the inner layer dielectric layer 206 of thickness 2000-12000 at above-mentioned overlayer 204 surface depositions.The inorganic silicon matrix layer that above-mentioned deposition inner layer dielectric layer 206 preferably is made of chemical vapour deposition technique (Inorganic silicon based layer) for example is black diamond (black diamond), silicon dioxide (SiO
2) or fluorinated silica glass (FSG).Note that the present invention does not form anti-reflecting layer on inner layer dielectric layer 206 surfaces.
In ensuing processing step, as shown in Figure 7, utilize traditional photoetching process (comprising photoresist coating, resist exposure, development step) to form photoresist layer 208 with contact hole opening 210 patterns on above-mentioned inner layer dielectric layer 206 surfaces.Above-mentioned photoresist is a negative photoresist, the about 1000-8000 of thickness.Then, as shown in Figure 8, utilize traditional photoetching process to form photoresist layer 212 again on the surface of above-mentioned photoresist pattern 208 with groove opening 216 patterns.The photoresist that the photoresist pattern is 212 layers is a positive photoresist, and its thickness is 1000-8000 .Certainly also can utilize positive photoresist to form photoresist layer 208 on inner layer dielectric layer 206 surfaces earlier, and then form photoresist layer 212 with negative photoresist with groove opening 216 patterns in the surface of photoresist pattern 208 with contact hole opening 210 patterns.The process fundamental purpose that adopts this positive photoresist and negative photoresist overlapping to form contact hole patterns of openings and groove opening pattern is to reduce contact hole patterns of openings and the mutually mutual interference of groove opening pattern when exposing with cleaning, make figure more clear, be convenient to follow-up etching technics and reach good etching effect.
Next continuation, utilizes rie process (reactive ion etching with reference to Fig. 8; RIE), utilize photoresist layer 208 and 212, via the contact hole opening figure 210 etching inner layer dielectric layers 206 of photoresist layer 208 qualifications as mask.In the process of etching inner layer dielectric layer 206, because the mask effect of photoresist layer 212, RIE is while etching photoresist layer 208 also.Certainly, the etch rate of RIE in inner layer dielectric layer 206 and photoresist layer 208 is variant slightly.When photoresist layer 208 was etched into inner layer dielectric layer 206 surperficial, RIE had etched the contact hole 218 that the degree of depth is essentially photoresist layer 208 thickness through contact hole opening figure 210 in inner layer dielectric layer 206, as shown in Figure 9.Then, continuation as mask, utilizes RIE technology etching contact hole 218 in inner layer dielectric layer 206 with photoresist layer 212.At this moment, when continuing etching contact hole 218, because the photoresist layer 208 that is not blocked by photoresist layer 212 has been etched, therefore, through the groove opening figure 216 of photoresist layer 212, RIE begins etching groove opening 219 in inner layer dielectric layer 206.RIE continues in inner layer dielectric layer 206 etching contact hole 218 and groove opening 219 simultaneously, has been etched into the surface of overlayer 204 until contact hole 218, as shown in figure 10.At this moment, the groove opening figure 216 of photoresist layer 208 contact hole graph 210 and photoresist layer 212 has been transferred in the inner layer dielectric layer 206 fully, forms contact hole 218 and opening 219.
In ensuing processing step, utilize chemical cleaning technology, for example cineration technics (ashing) is removed photoresist layer 208 and 212, the dual damascene figure that has obtained having contact hole 218 and groove opening 219, as shown in figure 11.Then along contact hole 218 downward etching overlayers 204, until exposing metal conducting layer 203, as shown in figure 12.
Method of the present invention also can continue downward etching overlayer 204 along contact hole 218, till exposing metal conducting layer 203 before photoresist layer 208 and 212 is removed.And then photoresist layer 208 and 212 removed.
At last, in contact hole 218 and groove opening 219, fill metal material, as copper (Cu), tantalum nitride (TaN) or tantalum (Ta) etc., just formed the metal interconnected dual-damascene structure 220 that links to each other with conductive layer 203, as shown in figure 13.
Figure 14 is the process flow diagram of dual-damascene structure formation method of the present invention.As shown in figure 14, the formation method of dual-damascene structure of the present invention comprises: the Semiconductor substrate that provides a surface to have dielectric layer forms metallic conduction structure (S101) in described dielectric layer; Described dielectric layer of planarization and described conductive structure (S102); Form by silicon nitride (Si at described dielectric layer and described conductive structure laminar surface
3N
4) or the overlayer formed of silicon oxynitride (SiON) or fire sand (SiCN), thickness is 200-1200 .Form inner layer dielectric layer (S103) on described overlayer, inner layer dielectric layer can be by black diamond (black diamond), silicon dioxide (SiO
2) or fluorinated silica glass (FSG) composition, the thickness of inner layer dielectric layer is 2000-12000 .On described inner layer dielectric layer, form first photoresist layer (S104) with contact hole graph; On described first photoresist layer, form second photoresist layer (S105) with groove opening figure; Utilize the described figure of described first photoresist layer of reactive ion etching process etching and second photoresist layer, until exposing described overlayer (S106); Remove described photoresist and described overlayer, until exposing described conductive structure (S107); Fill metal material such as copper (Cu), tantalum nitride (TaN) or tantalum (Ta) and form dual-damascene structure (S108).First photoresist layer is negative photoresist or positive photoresist.Second photoresist layer is positive photoresist or negative photoresist.Wherein the thickness of first photoresist layer is 1000-8000 , and the thickness of second photoresist layer is 1000-8000 .
Though oneself discloses the present invention as above with preferred embodiment, the present invention is defined in this.Any those skilled in the art without departing from the spirit and scope of the present invention, all can do various changes and modification, so protection scope of the present invention should be as the criterion with claim institute restricted portion.
Claims (20)
1, a kind of formation method of dual-damascene structure comprises:
The Semiconductor substrate that provides a surface to have conductive structure forms inner layer dielectric layer on substrate;
On described inner layer dielectric layer, form first photoresist layer with contact hole graph;
On described first photoresist layer, form second photoresist layer with groove opening figure;
The described figure of described first photoresist layer of etching and second photoresist layer is till exposing described conductive structure;
Fill metal material and form dual-damascene structure.
2, the method for claim 1 is characterized in that: described method also is included in and forms tectal step between described substrate surface and the described inner layer dielectric layer.
3, the method for claim 1 is characterized in that: described first photoresist layer is a negative photoresist, and described second photoresist layer is a positive photoresist.
4, the method for claim 1 is characterized in that: described first photoresist layer is a positive photoresist, and described second photoresist layer is a negative photoresist.
5, as claim 3 or 4 described methods, it is characterized in that: the thickness of described first photoresist layer is 1000-8000 .
6, as claim 3 or 4 described methods, it is characterized in that: the thickness of described second photoresist layer is 1000-8000 .
7, the method for claim 1 is characterized in that: described inner layer dielectric layer is black diamond (black diamond), silicon dioxide (SiO
2) or fluorinated silica glass (FSG).
8, method as claimed in claim 7 is characterized in that: the thickness of described inner layer dielectric layer is 2000-12000 .
9, method as claimed in claim 2 is characterized in that: described overlayer is silicon nitride (Si
3N
4) or silicon oxynitride (SiON), or fire sand (SiCN) thickness is 200-1200 .
10, the method for claim 1 is characterized in that: the technology of described etching is reactive ion etching (RIE) technology.
11, a kind of formation method of dual-damascene structure comprises:
The Semiconductor substrate that provides a surface to have dielectric layer forms metallic conduction structure in described dielectric layer;
Described dielectric layer of planarization and described conductive structure;
Form overlayer at described dielectric layer and described conductive structure laminar surface, on described overlayer, form inner layer dielectric layer;
On described inner layer dielectric layer, form first photoresist layer with contact hole graph;
On described first photoresist layer, form second photoresist layer with groove opening figure;
The described figure of described first photoresist layer of etching and second photoresist layer is until exposing described overlayer;
Remove described photoresist and described overlayer, until exposing described conductive structure;
Fill metal material and form dual-damascene structure.
12, method as claimed in claim 11 is characterized in that: described first photoresist layer is negative photoresist or positive photoresist.
13, method as claimed in claim 11 is characterized in that: described second photoresist layer is positive photoresist or negative photoresist.
14, as claim 12 or 13 described methods, it is characterized in that: the thickness of described first photoresist layer is 1000-8000 .
15, as claim 12 or 13 described methods, it is characterized in that: the thickness of described second photoresist layer is 1000-8000 .
16, method as claimed in claim 11 is characterized in that: described inner layer dielectric layer is black diamond (black diamond), silicon dioxide (SiO
2) or fluorinated silica glass (FSG).
17, method as claimed in claim 16 is characterized in that: the thickness of described inner layer dielectric layer is 2000-12000 .
18, method as claimed in claim 11 is characterized in that: described overlayer is silicon nitride (Si
3N
4) or silicon oxynitride (SiON), or fire sand (SiCN) thickness is 200-1200 .
19, method as claimed in claim 11 is characterized in that: the technology of described etching is reactive ion etching (RIE) technology.
20, method as claimed in claim 11 is characterized in that: the metal of described filling is copper (Cu), tantalum nitride (TaN) or tantalum (Ta).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200610025649 CN101055421A (en) | 2006-04-12 | 2006-04-12 | Method for forming double inserted structure |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200610025649 CN101055421A (en) | 2006-04-12 | 2006-04-12 | Method for forming double inserted structure |
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|---|---|
| CN101055421A true CN101055421A (en) | 2007-10-17 |
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|---|---|---|---|
| CN 200610025649 Pending CN101055421A (en) | 2006-04-12 | 2006-04-12 | Method for forming double inserted structure |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102097361A (en) * | 2009-12-15 | 2011-06-15 | 中芯国际集成电路制造(上海)有限公司 | Forming method of dual-damascene structure |
| CN102299097A (en) * | 2010-06-28 | 2011-12-28 | 中芯国际集成电路制造(上海)有限公司 | Method for etching metal connecting line |
| CN102314077A (en) * | 2010-07-08 | 2012-01-11 | 上海华虹Nec电子有限公司 | Method for performing planarization photoetching process on gate poly |
| CN103515299A (en) * | 2012-06-28 | 2014-01-15 | 中芯国际集成电路制造(上海)有限公司 | Low-k intermetallic dielectric (Low-k IMD) layer etching method |
| CN106032265A (en) * | 2015-03-12 | 2016-10-19 | 中芯国际集成电路制造(上海)有限公司 | A semiconductor device, a preparing method thereof and an electronic device thereof |
| CN106158726A (en) * | 2015-03-27 | 2016-11-23 | 中芯国际集成电路制造(上海)有限公司 | The manufacture method of semiconductor device |
| CN107359113A (en) * | 2017-07-28 | 2017-11-17 | 武汉光谷量子技术有限公司 | A kind of method and etching of InP material using RIE equipment etching of InP materials |
-
2006
- 2006-04-12 CN CN 200610025649 patent/CN101055421A/en active Pending
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102097361A (en) * | 2009-12-15 | 2011-06-15 | 中芯国际集成电路制造(上海)有限公司 | Forming method of dual-damascene structure |
| CN102299097A (en) * | 2010-06-28 | 2011-12-28 | 中芯国际集成电路制造(上海)有限公司 | Method for etching metal connecting line |
| CN102299097B (en) * | 2010-06-28 | 2014-05-21 | 中芯国际集成电路制造(上海)有限公司 | Method for etching metal connecting line |
| CN102314077A (en) * | 2010-07-08 | 2012-01-11 | 上海华虹Nec电子有限公司 | Method for performing planarization photoetching process on gate poly |
| CN103515299A (en) * | 2012-06-28 | 2014-01-15 | 中芯国际集成电路制造(上海)有限公司 | Low-k intermetallic dielectric (Low-k IMD) layer etching method |
| CN103515299B (en) * | 2012-06-28 | 2016-08-31 | 中芯国际集成电路制造(上海)有限公司 | Etching method of dielectric layer between a kind of low dielectric constant materials |
| CN106032265A (en) * | 2015-03-12 | 2016-10-19 | 中芯国际集成电路制造(上海)有限公司 | A semiconductor device, a preparing method thereof and an electronic device thereof |
| CN106158726A (en) * | 2015-03-27 | 2016-11-23 | 中芯国际集成电路制造(上海)有限公司 | The manufacture method of semiconductor device |
| CN106158726B (en) * | 2015-03-27 | 2019-05-31 | 中芯国际集成电路制造(上海)有限公司 | The manufacturing method of semiconductor devices |
| CN107359113A (en) * | 2017-07-28 | 2017-11-17 | 武汉光谷量子技术有限公司 | A kind of method and etching of InP material using RIE equipment etching of InP materials |
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