TW202324603A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

A semiconductor device includes a first dielectric layer, a first conductive structure, a second conductive structure, a first via, a second via, a polymer lining layer and a second dielectric layer. The first conductive structure is in the first dielectric layer. The second conductive structure is in the first dielectric layer and is spaced apart the first conductive structure. The first via is over the first conductive structure. The second via is over the second conductive structure. The polymer spacing layer laterally surrounds the second via. The second dielectric layer laterally surrounds the first via and the polymer lining layer and is separated from the second via from the polymer lining layer.

Description

Semiconductor device and manufacturing method thereof

Some embodiments of the present disclosure relate to semiconductor devices and methods of manufacturing the same.

In the back end of line (BEOL) of semiconductor devices, the interconnect structure is formed on the device layer of the wafer. Interconnect structures can be used to provide electrical interconnection between different components, such as transistors. The interconnection structure may include multiple metal layers and vias connecting different metal layers.

Some embodiments of the present disclosure provide a semiconductor device, including a first dielectric layer, a first conductive structure, a second conductive structure, a first via, a second via, a polymer liner layer, and a second dielectric layer. The first conductive structure is located in the first dielectric layer. The second conductive structure is located in the first dielectric layer and separated from the first conductive structure. The first via is located on the first conductive structure. The second via is located on the second conductive structure. A polymer liner layer laterally surrounds the second via. And, the second dielectric layer laterally surrounds the first via and the polymer liner layer, wherein the second dielectric layer contacts the first via and is separated from the second via by the polymer liner layer .

In some embodiments, the width of the first via is greater than the width of the second via.

In some embodiments, a width of the second via is different from that of the second conductive structure.

In some embodiments, the side surface of the polymer liner layer forms an included angle with the upper surface of the second conductive structure, and the included angle is between 65 degrees and 75 degrees.

In some embodiments, the polymer liner layer contacts the second conductive structure and the first dielectric layer.

Some embodiments of the present disclosure provide a method of manufacturing a semiconductor device, including forming a first conductive structure and a second conductive structure in a first dielectric layer. An etching stop layer is formed on the first conductive structure, the second conductive structure and the first dielectric layer. A second dielectric layer is formed on the etch stop layer. A photoresist layer is formed on the second dielectric layer, wherein the photoresist layer has a first opening and a second opening, the size of the first opening and the second opening are different, and the first opening is located above the first conductive structure, and the second opening is located above the first conductive structure. above the second conductive structure. Etching the second dielectric layer and the etch stop layer through the photoresist layer to form the first via opening and the second via opening in the second dielectric layer and the etch stop layer, the first via opening is exposed The first conductive structure, the second via opening exposes the second conductive structure, and the width of the first via opening is substantially the same as that of the first conductive structure, and the width of the second via opening is wider than the width of the second conductive structure Width. A polymer layer is formed on the upper surface of the second dielectric layer, the first via opening and the second via opening. performing an etching process to remove the upper surface of the second dielectric layer, the polymer layer in the first via opening and on the bottom surface of the second via opening, and partially remove the second via laterally A polymer layer on the sidewall of the opening to form a polymer liner layer on the sidewall of the opening of the second via. And, filling the metal material in the first via opening and the second via opening to form the first via in the first via opening and the second via in the second via opening. Hole pieces.

In some embodiments, when the polymer layer is formed, the polymer layer is thicker in the second via opening than in the first via opening.

In some embodiments, forming the polymer layer includes using a gas to deposit the polymer layer, the gas comprising hexafluorobutadiene, methane, nitrogen, octafluorocyclobutane, or combinations thereof.

In some embodiments, performing the etch process includes using a gas with a high fluorine ratio.

In some embodiments, the width of the first via is different from that of the second via.

In summary, some embodiments of the present disclosure can be used to form vias of different sizes in the same process. Specifically, a photoresist layer with openings of different sizes may be formed on the dielectric layer first, and then a polymer layer is deposited on the photoresist layer. When etching the dielectric layer, the polymer layer can be used to adjust the opening size to form via features of different sizes.

The following will disclose multiple implementations of the present disclosure with diagrams, and for the sake of clarity, many practical details will be described together in the following description. However, it should be understood that these practical details should not be used to limit the present disclosure. That is to say, in some embodiments of the present disclosure, these practical details are unnecessary. In addition, for the sake of simplifying the drawings, some well-known structures and components will be shown in a simple and schematic manner in the drawings.

Some embodiments of the present disclosure relate to methods of adjusting via size using deposited polymers. Specifically, a photoresist layer with openings of different sizes may be formed on the dielectric layer first, and then a polymer layer is deposited on the photoresist layer. When etching the dielectric layer, the polymer layer can be used to adjust the opening size to form via features of different sizes.

1 to 8 illustrate cross-sectional views of intermediate stages in the manufacturing process of a semiconductor device according to some embodiments of the present disclosure. Referring to FIG. 1 , a first conductive structure 112 , a second conductive structure 114 and a third conductive structure 116 are formed in the first dielectric layer 102 . The first dielectric layer 102 may be first formed on components of the semiconductor device (such as transistors, diodes, capacitors, resistors, or the like). Next, a plurality of openings are formed in the first dielectric layer 102 using an etching process, and a suitable conductive material is filled in the openings to form the first conductive structure 112 and the second conductive structure 114 in the first dielectric layer 102 and the third conductive structure 116 . The first conductive structure 112 , the second conductive structure 114 and the third conductive structure 116 are not interconnected with each other and are separated from each other by the first dielectric layer 102 . The first dielectric layer 102 can provide electrical isolation between the first conductive structure 112 , the second conductive structure 114 and the third conductive structure 116 . In some embodiments, the first conductive structure 112, the second conductive structure 114, and the third conductive structure 116 can be made of metal, such as copper, and the first dielectric layer 102 can be made of low dielectric constant or ultra-low dielectric constant. Made of electrical materials, such as dielectric materials with a dielectric constant lower than 3.0.

In some implementations, the first conductive structure 112, the second conductive structure 114, and the third conductive structure 116 can be metal wires in an interconnection structure in a semiconductor device respectively, so the first conductive structure 112, the second conductive structure 114 The bottom of the third conductive structure 116 can be connected to other components in the semiconductor device, such as transistors, diodes, capacitors, resistors or the like. Alternatively, the lower parts of the first conductive structure 112 , the second conductive structure 114 and the third conductive structure 116 may be connected to vias in the interconnection structure. The first conductive structure 112 , the second conductive structure 114 and the third conductive structure 116 may be respectively located in different areas of the wafer, for example, in different peripheral circuit areas. Since the resistance values required by the vias in different regions are different, the dimensions (eg, width) of the vias in different regions are also different, so as to meet the resistance values required by each region.

Referring to FIG. 2, an etch stop layer 122 is formed on the first conductive structure 112, the second conductive structure 114, the third conductive structure 116 and the first dielectric layer 102, so that the etch stop layer 122 completely covers the first conductive structure 112, The second conductive structure 114 and the third conductive structure 116 . In some embodiments, etch stop layer 122 may be formed using chemical vapor deposition, physical vapor deposition, atomic layer deposition, or the like. In some embodiments, the etch stop layer 122 may be formed of a suitable material, such as silicon nitride, silicon carbide, silicon carbonitride or the like.

Referring to FIG. 3 , a second dielectric layer 124 is formed on the etch stop layer 122 . In some embodiments, the second dielectric layer 124 may be formed using chemical vapor deposition, physical vapor deposition, atomic layer deposition, or the like. In some embodiments, the second dielectric layer 124 may be made of a dielectric material with a low dielectric constant, such as a dielectric material with a dielectric constant lower than 3.0. In some embodiments, the second dielectric layer 124 may be made of the same material as the first dielectric layer 102 .

Referring to FIG. 4 , a photoresist layer PR is formed on the second dielectric layer 124 , wherein the photoresist layer PR has a first opening O1 , a second opening O2 and a third opening O3 . Specifically, a layer of photoresist material can be formed on the second dielectric layer 124 first. Next, the photoresist material layer can be exposed to an opaque pattern, and the exposed photoresist material layer is developed to form a patterned photoresist layer PR on the second dielectric layer 124, and the pattern includes The first opening O1, the second opening O2 and the third opening O3. The first opening O1 is located above the first conductive structure 112 , the second opening O2 is located above the second conductive structure 114 , and the third opening O3 is located above the third conductive structure 116 . In some embodiments, the first opening O1 , the second opening O2 , and the third opening O3 of different sizes can be formed according to the width of the subsequently formed via. For example, the first opening O1 and the second opening O2 have different sizes, and the first opening O1 and the third opening O3 have the same size. Specifically, the second opening O2 may be larger than the first opening O1 and the third opening O3. Therefore, the sidewalls of the first opening O1 and the third opening O3 can be aligned with the edges of the upper surfaces of the first conductive structure 112 and the third conductive structure 116 respectively. The sidewalls of the second opening O2 are not aligned with the edge of the upper surface of the second conductive structure 114 , and the width of the second opening O2 is wider than the width of the upper surface of the second conductive structure 114 .

Referring to FIG. 5, the second dielectric layer 124 and the etch stop layer 122 are etched by the photoresist layer PR to form the first via hole VO1 and the second via in the second dielectric layer 124 and the etch stop layer 122. The hole opening VO2 and the third through hole opening VO3. In some embodiments, the first etching process may be performed to etch the second dielectric layer 124 through the photoresist layer PR first, and then the second etching process may be performed to etch the etch stop layer through the photoresist layer PR and the second dielectric layer 124 122 , to form a first via opening VO1 , a second via opening VO2 and a third via opening VO3 in the second dielectric layer 124 and the etch stop layer 122 . Then, the photoresist layer PR can be removed by using a suitable method, such as photoresist ashing. The first etching process and the second etching process may be dry etching, wet etching or a combined etching process.

The first via opening VO1 exposes the first conductive structure 112 , the second via opening VO2 exposes the second conductive structure 114 , and the third via opening VO3 exposes the third conductive structure 116 . The width of the first via opening VO1 is the same as that of the first conductive structure 112, and the width of the third via opening VO3 is the same as that of the third conductive structure 116, so that the first via opening VO1 is the same as the third via opening VO3 The sidewalls of the first via opening VO1 and the third via opening VO3 do not expose the first dielectric layer 102 respectively. The width of the second via opening VO2 is wider than the width of the second conductive structure 114 , so the second via opening VO2 exposes a portion of the first dielectric layer 102 .

Referring to FIG. 6 , the polymer layer 130 is formed on the upper surface of the second dielectric layer 124 , the first via opening VO1 , the second via opening VO2 and the third via opening VO3 . Specifically, a gas may be used to deposit the polymer layer 130 . In some embodiments, the gas used to deposit the polymer layer 130 includes hexafluorobutadiene, methane, nitrogen, octafluorocyclobutane, or combinations thereof.

When the polymer gas is deposited on the first via opening VO1 , the second via opening VO2 and the third via opening VO3 , the amount of polymer gas deposited in the openings is different due to different opening sizes. For example, when the openings are relatively small, such as the first via opening VO1 and the third via opening VO3 , the polymer gas is not easily deposited in the openings. Therefore, the polymer layer 132 formed on the first via opening VO1 and the third via opening VO3 is relatively thin. When the opening is relatively large, such as the second via opening VO2 , the polymer gas is easy to deposit in the opening, and also easy to accumulate at the corner formed by the sidewall of the opening and the upper surface of the first dielectric layer 102 below. In this way, when forming the polymer layer 130, the polymer layer 134 in the second via opening VO2 is thicker than the polymer layer 132 in the first via opening VO1 and the third via opening VO3. thick. The width of the second via opening VO2 also becomes smaller than that of the first via opening VO1 and the third via opening VO3 . In addition, since the polymer gas is easy to accumulate at the corner of the second via opening VO2 , the width of the polymer layer 134 becomes narrower along the direction away from the first dielectric layer 102 . In this way, after the polymer layer 130 is formed, the width of the second via opening VO2 is reduced, and an opening gradually widens along the direction away from the first dielectric layer 102 is formed. When forming the polymer layer 130, the polymer layer 134 in the second via opening VO2 covers the upper surface of the first dielectric layer 102, so that the bottom of the second via opening VO2 becomes more conductive than the second via opening VO2. The upper surface of structure 114 is also narrow.

Referring to FIG. 7, an etching process is performed to remove aggregates on the upper surface of the second dielectric layer 124, the bottom surfaces of the first via opening VO1, the second via opening VO2, and the third via opening VO3. layer 130, the polymer layer 132 on the sidewalls of the first via opening VO1 and the third via opening VO3, and partially laterally remove the polymer layer 134 on the sidewalls of the second via opening VO2 , to form the polymer liner layer 136 on the sidewall of the second via opening VO2.

Specifically, the etching process in FIG. 7 will undercut the polymer layer 130 on the sidewalls of the first via opening VO1 , the second via opening VO2 and the third via opening VO3 . Since the polymer layer 132 on the sidewalls of the first via opening VO1 and the third via opening VO3 is relatively thin, when the etching process in FIG. 7 is performed, the first via opening VO1 and the third via The polymer layer 132 on the sidewall of the hole opening VO3 is easily removed to expose the sidewall of the second dielectric layer 124 and the etch stop layer 122 . On the other hand, the polymer layer 134 in the second via opening VO2 is relatively thick, so the etching process only partially etches the polymer layer 134 on the sidewall of the second via opening VO2, and forms the polymer layer 134 on the sidewall of the second via opening VO2. Polymer liner layer 136 on the sidewall of orifice opening VO2. During the etching process, the polymer liner layer 136 still covers the upper surface of the first dielectric layer 102 , so that the second via opening VO2 still only exposes the second conductive structure 114 . In this way, the polymer layer 130 can be used to manufacture via openings of different sizes in the same process. In some embodiments, etching may be performed using a suitable etching gas, such as a gas with a high fluorine ratio, such as carbon tetrafluoride. Since the polymer layer 134 is a polymer layer stacked on the second via opening VO2 , the sidewall of the polymer layer 134 has an included angle a with the upper surface of the second conductive structure 114 . In some embodiments, the included angle a is between 65 degrees and 75 degrees.

Referring to FIG. 8, the metal material is filled in the first via opening VO1, the second via opening VO2 and the third via opening VO3 to form the first via hole in the first via opening VO1. 142 and the second via 144 in the second via opening VO2 and the third via 146 in the third via opening VO3.

In this way, the obtained semiconductor device is as shown in FIG. 8 . The semiconductor device may include a first dielectric layer 102, a first conductive structure 112, a second conductive structure 114, a third conductive structure 116, a first via 142, a second via 144, a third via 146, Polymer liner layer 136 and second dielectric layer 124 . The first conductive structure 112, the second conductive structure 114 and the third conductive structure 116 are located in the first dielectric layer 102, and the first conductive structure 112, the second conductive structure 114 and the third conductive structure 116 are connected to each other through the first dielectric layer. The electrical layer 102 is separated. The first via 142 , the second via 144 and the third via 146 are respectively located on the first conductive structure 112 , the second conductive structure 114 and the third conductive structure 116 . The polymer liner layer 136 laterally surrounds the second via 144 . The second dielectric layer 124 laterally surrounds the first via 142 , the third via 146 and the polymer liner 136 . The second dielectric layer 124 contacts the first via 142 and is separated from the second via 144 by the polymer liner layer 136 . In some embodiments, the semiconductor device further includes an etch stop layer 122 . The etch stop layer 122 is located under the second dielectric layer 124 and on the first dielectric layer 102 , and contacts the polymer liner layer 136 .

The polymer liner layer 136 may be used to adjust the width of the via opening. For example, the polymer liner layer 136 can be formed on the sidewall of the second via opening VO2, so that the polymer liner layer 136 contacts the second conductive structure 114 and the first dielectric layer 102, thereby narrowing the second via. The width of the hole opening VO2. Therefore, the widths of the first through hole 142 , the second through hole 144 , and the third through hole 146 are different. For example, the widths of the first through hole 142 and the third through hole 146 are greater than the width of the second through hole 144 . The polymer liner layer 136 makes the bottom of the second via opening VO2 narrower than that of the second conductive structure 114 , so the width of the bottom of the second via 144 is the same as the second conductive structure 114 . The upper surfaces of structures 114 vary in width. The first via opening VO1 and the third via opening VO3 do not have a polymer liner layer, and the sidewalls of the first via opening VO1 and the third via opening VO3 are substantially aligned with the first conductive structure respectively. 112 and the upper surface of the third conductive structure 116 . Therefore, the first via 142 and the third via 146 can be substantially aligned with the upper surface of the first conductive structure 112 and the upper surface of the third conductive structure 116 respectively. In this way, through-hole parts with different sizes can be manufactured in the same process, so that the complexity of the process can be reduced. Different sized vias are available for different areas of the wafer and provide specific resistance values for specific areas.

It should be noted that FIGS. 1 to 8 illustrate the manufacturing process of one layer of conductive structures and vias in the interconnection structure of the semiconductor device. After the process of FIG. 8 is completed, the processes shown in FIGS. 1 to 8 can be repeated to form conductive structures on the first via 142 , the second via 144 and the third via 146 . with through-hole parts. In this way, the formation of the interconnection structure of the semiconductor device can be completed.

In summary, using the process of the embodiments of the present disclosure, via openings of different sizes can be formed in the same process. Specifically, according to different opening sizes, the amount of polymer gas deposited in the openings will change accordingly. For example, polymer gas deposits easily in wider openings and less easily in narrower openings. Therefore, via openings of different sizes can be formed in the dielectric layer first, and then a polymer gas is deposited to form a polymer liner layer that can adjust the via openings. Then, vias of different sizes can be formed. In this way, vias with different sizes can be formed in the same process, which reduces the complexity of the process.

Although this disclosure has been disclosed in an implementation manner. As above, but it is not used to limit this disclosure. Anyone who is familiar with this technology can make various changes and modifications without departing from the spirit and scope of this disclosure. Therefore, the scope of protection of this disclosure should be regarded as the appended patent application. The scope defined shall prevail.

102: the first dielectric layer 112: the first conductive structure 114: second conductive structure 116: The third conductive structure 122: etch stop layer 124: second dielectric layer 130: polymer layer 132: polymer layer 134: polymer layer 136: polymer backing layer 142: the first through hole 144: the second through hole 146: The third through hole a: included angle O1: first opening O2: second opening O3: third opening PR: photoresist layer VO1: The opening of the first through hole VO2: The opening of the second through hole VO3: The opening of the third through hole

FIGS. 1-8 illustrate cross-sectional views of intermediate stages in the fabrication process of a semiconductor device according to some embodiments of the present disclosure.

Domestic deposit information (please note in order of depositor, date, and number) none Overseas storage information (please note in order of storage country, institution, date, and number) none

102: the first dielectric layer

112: the first conductive structure

114: second conductive structure

116: The third conductive structure

122: etch stop layer

124: second dielectric layer

136: polymer backing layer

142: the first through hole

144: the second through hole

146: The third through hole

a: included angle

Claims (10)

A semiconductor device comprising: a first dielectric layer; a first conductive structure located in the first dielectric layer; a second conductive structure located in the first dielectric layer and separated from the first conductive structure; a first via located on the first conductive structure; a second via located on the second conductive structure; a polymer liner layer laterally surrounding the second via; and a second dielectric layer laterally surrounding the first via and the polymer liner, wherein the second dielectric layer contacts the first via and is connected to the polymer liner through the polymer liner The second through hole is separated. The semiconductor device as claimed in claim 1, wherein the width of the first via is greater than the width of the second via. The semiconductor device as claimed in claim 1, wherein a width of the second via is different from that of the second conductive structure. The semiconductor device as claimed in claim 1, wherein a side surface of the polymer liner layer forms an angle with an upper surface of the second conductive structure, and the angle is between 65 degrees and 75 degrees. The semiconductor device of claim 1, wherein the polymer liner layer contacts the second conductive structure and the first dielectric layer. A method of manufacturing a semiconductor device, comprising: forming a first conductive structure and a second conductive structure in a first dielectric layer; forming an etch stop layer on the first conductive structure, the second conductive structure and the first dielectric layer; forming a second dielectric layer on the etch stop layer; forming a photoresist layer on the second dielectric layer, wherein the photoresist layer has a first opening and a second opening, the first opening and the second opening are different in size, and the first opening is located at the first opening above a conductive structure, the second opening is located above the second conductive structure; etching the second dielectric layer and the etch stop layer through the photoresist layer to form a first via opening and a second via opening in the second dielectric layer and the etch stop layer, The first via opening exposes the first conductive structure, the second via opening exposes the second conductive structure, and the width of the first via opening is substantially the same as that of the first conductive structure, and the second via opening exposes the second conductive structure. The width of the via opening is wider than the width of the second conductive structure; forming a polymer layer on an upper surface of the second dielectric layer, the first via opening and the second via opening; performing an etching process to remove the upper surface of the second dielectric layer, the polymer layer in the first via opening and on a bottom surface of the second via opening, and partially laterally removing the polymer layer on the sidewall of the second via opening to form a polymer liner layer on the sidewall of the second via opening; and filling a metal material in the first via opening and the second via opening to form a first via in the first via opening and a first via in the second via opening A second through-hole member. The method of claim 6, wherein when forming the polymer layer, the polymer layer in the second via opening is thicker than the polymer layer in the first via opening. The method according to claim 6, wherein when forming the polymer layer, comprising using a gas to deposit the polymer layer, the gas comprises hexafluorobutadiene, methane, nitrogen, octafluorocyclobutane or a combination thereof . The method of claim 6, wherein performing the etching process includes using a gas with a high fluorine ratio. The method of claim 6, wherein the width of the first via is different from that of the second via.

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