CN113257737A - Semiconductor structure and manufacturing method thereof - Google Patents
Semiconductor structure and manufacturing method thereof Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 103
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 26
- 239000010410 layer Substances 0.000 claims abstract description 457
- 238000005530 etching Methods 0.000 claims abstract description 137
- 239000011229 interlayer Substances 0.000 claims abstract description 90
- 238000000034 method Methods 0.000 claims abstract description 73
- 239000000758 substrate Substances 0.000 claims abstract description 65
- 230000004888 barrier function Effects 0.000 claims abstract description 11
- 230000008569 process Effects 0.000 claims description 53
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 3
- 239000007789 gas Substances 0.000 description 9
- NBVXSUQYWXRMNV-UHFFFAOYSA-N monofluoromethane Natural products FC NBVXSUQYWXRMNV-UHFFFAOYSA-N 0.000 description 5
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 239000001301 oxygen Substances 0.000 description 4
- 229910052760 oxygen Inorganic materials 0.000 description 4
- 239000004020 conductor Substances 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 239000004341 Octafluorocyclobutane Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910052786 argon Inorganic materials 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
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- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- BCCOBQSFUDVTJQ-UHFFFAOYSA-N octafluorocyclobutane Chemical compound FC1(F)C(F)(F)C(F)(F)C1(F)F BCCOBQSFUDVTJQ-UHFFFAOYSA-N 0.000 description 2
- 235000019407 octafluorocyclobutane Nutrition 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
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- 230000003667 anti-reflective effect Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
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Abstract
The invention provides a semiconductor structure and a manufacturing method thereof. The manufacturing method comprises the following steps: providing a semiconductor substrate with a top conductive layer; forming an interlayer dielectric layer on a semiconductor substrate, wherein at least one buffer layer is clamped in the interlayer dielectric layer, and the buffer layer divides the interlayer dielectric layer into more than two sub-dielectric layers; and etching each sub-dielectric layer of the interlayer dielectric layer and the exposed buffer layer in a graded manner by using the buffer layer as an etching barrier layer of the sub-dielectric layers, and forming a through hole on the semiconductor substrate, wherein the through hole exposes the top conductive layer. In the method, the interlayer medium layer is etched in a grading manner to form a plurality of through holes, so that the etching depth of each etching can be reduced, and the buffer layer is used as the etching barrier layer of the sub-medium layer, so that the etching amount of each etching is conveniently controlled, the etching uniformity is improved, and the depth uniformity of the obtained through holes is improved. The semiconductor structure can be manufactured by the manufacturing method.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a semiconductor structure and a manufacturing method thereof.
Background
As semiconductor technology advances to Large Scale Integration (LSI) or Very Large Scale Integration (VLSI), semiconductor devices typically have multiple conductive layers. In order to reduce the interconnect resistance capacitance (RC delay) between conductive layers, conductive plugs including vias are commonly used in semiconductor devices such as logic devices (logic devices) to achieve interconnection between different conductive layers.
The conventional method for manufacturing the conductive plug comprises the following steps: first, an interlayer dielectric (ILD) layer is formed on a semiconductor substrate (e.g., a wafer); then, etching the interlayer dielectric layer to form a through hole (via hole), wherein the through hole penetrates through the interlayer dielectric layer and exposes the top conductive layer on the semiconductor substrate; then, filling a conductive material in the through hole to form a conductive plug; and forming a new conductive layer on the interlayer dielectric layer, wherein the conductive plug enables the two conductive layers connected with the conductive plug to be electrically connected.
Fig. 1 to 3 are cross-sectional views of through holes formed at different positions of a semiconductor substrate by the same etching process. Research finds that in the process of etching an interlayer dielectric layer to form a through hole, due to the influence of loading effect (loading effect), selection of etching gas, gas pressure and other factors, the Etching Rates (ER) of different areas of a semiconductor substrate are different, when the depth of the through hole is larger, the depth uniformity of the through hole at different positions formed by etching on the same substrate is poorer, so that a part of area (for example, the middle area of a wafer) of the semiconductor substrate is etched to a target position (as shown in fig. 1), a part of area (for example, the edge area of the wafer) is not etched to the target position (as shown in fig. 2), and the other part of area is over-etched and damages a conductive layer at the bottom (as shown in fig. 3), thereby affecting the performance of a manufactured semiconductor device.
Disclosure of Invention
The invention provides a semiconductor structure and a manufacturing method thereof, aiming at improving the depth uniformity of a through hole and improving the performance of a semiconductor device.
One aspect of the present invention provides a method for fabricating a semiconductor structure, the method comprising:
forming an interlayer dielectric layer on the semiconductor substrate, wherein at least one buffer layer is clamped in the interlayer dielectric layer, and the buffer layer divides the interlayer dielectric layer into more than two sub-dielectric layers; and
and etching each sub-dielectric layer of the interlayer dielectric layer and the exposed buffer layer in a graded manner by using the buffer layer as an etching barrier layer of the sub-dielectric layer, and forming a through hole on the semiconductor substrate, wherein the through hole exposes the top conductive layer.
Optionally, the etching each sub-dielectric layer of the interlayer dielectric layer and the exposed buffer layer in a graded manner, and the forming a through hole on the semiconductor substrate includes:
executing a first etching process to etch the sub-dielectric layer at the top to form a plurality of openings, wherein the openings expose the buffer layer below the sub-dielectric layer at the top, and the etching rate of the first etching process to the sub-dielectric layer is greater than that of the buffer layer;
executing a second etching process to remove the buffer layer exposed from the opening, wherein the etching rate of the second etching process to the buffer layer is greater than that of the sub-dielectric layer;
and repeatedly executing the first etching process to etch downwards other sub-dielectric layers and executing the second etching process to etch downwards other buffer layers until a through hole exposing the top conducting layer is formed, wherein the through hole penetrates through the sub-dielectric layers and the buffer layers which are superposed on the semiconductor substrate.
Optionally, the depth of the through hole is more than 1 micron.
Optionally, the thickness of the sub-dielectric layer is 300nm to 500 nm.
Optionally, the thickness of the buffer layer is 30nm to 50 nm.
Optionally, the interlayer dielectric layer includes three sub-dielectric layers and two buffer layers respectively located between the sub-dielectric layers; or the interlayer dielectric layer comprises five sub-dielectric layers and four buffer layers respectively positioned between the sub-dielectric layers.
Optionally, the thicknesses of the sub-dielectric layers are the same, or the thickness of the sub-dielectric layer at the lowermost layer is the smallest.
Optionally, the thickness of the buffer layer is smaller than that of the adjacent sub-dielectric layer.
Optionally, the interlayer dielectric layer is silicon oxide, and the buffer layer is silicon nitride.
In another aspect of the present invention, a semiconductor structure manufactured by the above manufacturing method includes:
a semiconductor substrate having a top conductive layer thereon;
the semiconductor substrate comprises an interlayer dielectric layer, a semiconductor substrate and a buffer layer, wherein the interlayer dielectric layer is formed on the semiconductor substrate, at least one buffer layer is clamped in the interlayer dielectric layer, and the buffer layer divides the interlayer dielectric layer into more than two sub-dielectric layers;
and the through hole penetrates through the interlayer dielectric layer and exposes the top conducting layer.
In the manufacturing method of the semiconductor structure, an interlayer dielectric layer is formed on a semiconductor substrate, at least one buffer layer is clamped in the interlayer dielectric layer, the buffer layer divides the interlayer dielectric layer into more than two sub-dielectric layers, then the buffer layer is used as an etching barrier layer of the sub-dielectric layers, each sub-dielectric layer and the exposed buffer layer are etched in a grading mode, and through holes are formed in the semiconductor substrate. Compared with the prior method that the interlayer dielectric layer is not clamped with the buffer layer and is etched through at one time, the manufacturing method divides the interlayer dielectric layer into a plurality of sub-dielectric layers and etches each sub-dielectric layer and the buffer layer in a grading way, can reduce the etching depth of each etching, and the buffer layer is used as the etching barrier layer of the sub-dielectric layers, is convenient to control the etching amount of each sub-dielectric layer, is beneficial to improving the etching uniformity of the interlayer dielectric layer, ensures that the depth uniformity of through holes formed at different positions of the semiconductor substrate is better, and can improve the performance of a semiconductor device.
Further, the sub-medium layer is etched by the first etching process with the etching rate of the sub-medium layer being greater than that of the buffer layer, the etching can be stopped on the surface of the buffer layer, and the sub-medium layer below the buffer layer is not easy to remove, so that the sub-medium layer on the buffer layer can be fully etched and removed, and a plurality of openings with consistent depths are formed in the sub-medium layer; and etching and removing the buffer layer exposed from the opening by adopting a second etching process with the etching rate of the buffer layer larger than that of the sub-dielectric layer, and stopping etching on the sub-dielectric layer, so that the buffer layer exposed from the opening can be removed. That is to say, when the interlayer dielectric layer is etched to form the through holes, the etching of the sub-dielectric layer can be stopped on the buffer layer, and the etching of the buffer layer can be stopped on the sub-dielectric layer, so that each sub-dielectric layer and each buffer layer can be fully etched without over-etching, the depth uniformity of a plurality of through holes formed by etching the interlayer dielectric layer is improved, and the performance of a semiconductor device is improved.
The invention also provides a semiconductor structure, which comprises a semiconductor substrate and an interlayer dielectric layer formed on the semiconductor substrate, wherein at least one buffer layer is clamped in the interlayer dielectric layer, the buffer layer divides the interlayer dielectric layer into more than two sub-dielectric layers, so that a plurality of through holes formed in the interlayer dielectric layer can be formed by etching in multiple times, the control of each etching step is convenient, the depth uniformity of the through holes at different positions on the semiconductor substrate is good, and the performance of a semiconductor device is improved.
Drawings
Fig. 1 to 3 are cross-sectional views of through holes formed at different positions of a semiconductor substrate by the same etching process.
Fig. 4-5 are schematic cross-sectional views of a conventional method for forming a via in an ild layer.
FIG. 6 is a flow chart of a method of fabricating a semiconductor structure according to an embodiment of the invention.
Fig. 7-12 are multi-step cross-sectional views illustrating a method of fabricating a semiconductor structure according to one embodiment of the present invention.
Description of reference numerals:
100-a semiconductor substrate; 101-a top conductive layer; 102-interlayer dielectric layer; 1021-a first sub-media layer; 1022 — a first buffer layer; 1023-a second sub-media layer; 1024 — a second buffer layer; 1025-third sub-medium layer; 103-a mask layer; 2011-first opening; 2012-a second opening; 2013-a third opening; 2014-fourth opening; 202-through holes.
Detailed Description
The semiconductor structure and the method for fabricating the same according to the present invention will be described in detail with reference to the accompanying drawings and embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Fig. 4-5 are schematic cross-sectional views of a conventional method for forming a via in an ild layer. The method for manufacturing the through hole on the interlayer dielectric layer by using the existing method comprises the following steps:
as shown in fig. 4, an interlayer dielectric layer 102 is formed on the semiconductor substrate 100, and a patterned mask layer 103 is formed on the interlayer dielectric layer 102;
as shown in fig. 5, the patterned mask layer 103 is used as a mask to etch through the interlayer dielectric layer 102 in one step, so as to form a plurality of through holes 202, wherein the through holes 202 expose the top conductive layer 101 on the semiconductor substrate 100.
In the process of forming the through hole 202 by etching the interlayer dielectric layer 102, due to the influence of factors such as a load effect, selection of etching gas, gas pressure and the like, the etching rates of different areas of the semiconductor substrate are different, and when the depth of the through hole is large, the uniformity of the depth of the through hole formed by etching and located at different positions of the semiconductor substrate is poor, and the performance of a semiconductor device is influenced.
In order to solve the above problem, the present embodiment provides a method for manufacturing a semiconductor structure. FIG. 6 is a flow chart of a method of fabricating a semiconductor structure according to an embodiment of the invention. As shown in fig. 6, the manufacturing method includes:
s01: providing a semiconductor substrate, wherein the semiconductor substrate is provided with a top conducting layer;
s02: forming an interlayer dielectric layer on a semiconductor substrate, wherein at least one buffer layer is clamped in the interlayer dielectric layer, and the buffer layer divides the interlayer dielectric layer into more than two sub-dielectric layers;
s03: and etching each sub-dielectric layer of the interlayer dielectric layer and the exposed buffer layer in a graded manner by using the buffer layer as an etching barrier layer of the sub-dielectric layer, and forming a through hole on the semiconductor substrate, wherein the through hole exposes the top conductive layer.
Fig. 7-12 are multi-step cross-sectional views illustrating a method of fabricating a semiconductor structure according to one embodiment of the present invention. The method for fabricating the semiconductor structure of the present embodiment is described below with reference to fig. 6 to 12.
As shown in fig. 7, the semiconductor substrate 100 has a top conductive layer 101 thereon; an interlayer dielectric layer 102 is formed on a semiconductor substrate 100, the interlayer dielectric layer 102 is formed on the semiconductor substrate 100, at least one buffer layer (such as a first buffer layer 1022 and a second buffer layer 1024) is clamped in the interlayer dielectric layer 102, and the buffer layer divides the interlayer dielectric layer into more than two sub-dielectric layers (such as a first sub-dielectric layer 1021, a second sub-dielectric layer 1023 and a third sub-dielectric layer 1025).
The semiconductor substrate 100 may be a silicon substrate. In another embodiment, the semiconductor substrate may be a Germanium substrate, a Silicon On Insulator (SOI), a Germanium On Insulator (GOI), or the like, and a certain amount of doping particles may be implanted into the semiconductor substrate according to design requirements to change electrical parameters.
In this embodiment, the interlayer dielectric layer 102 may include three sub-dielectric layers and two buffer layers respectively located between the sub-dielectric layers. In another embodiment, the interlayer dielectric layer includes five sub-dielectric layers and four buffer layers respectively located between the sub-dielectric layers. But not limited thereto, the number of the buffer layers may be set according to the thickness of the interlayer dielectric layer.
In this embodiment, the thickness of the through hole may be 1 μm or more. The thickness of the sub-dielectric layer can be 300 nm-500 nm. The thickness of the buffer layer may be smaller than the thickness of the adjacent sub-dielectric layer, for example, the thickness of the buffer layer may be 30nm to 50 nm.
The thicknesses of the sub-dielectric layers can be equal, or the thicknesses of the sub-dielectric layers are sequentially decreased from top to bottom. In one embodiment, the thickness of the sub-dielectric layer at the lowest layer is the smallest. Because the top conducting layer is arranged below the sub-medium layer at the lowest layer and no buffer layer is used as an etching barrier layer, the etching time of the sub-medium layer is short due to the fact that the thickness of the sub-medium layer at the lowest layer is small, and therefore side etching and over-etching can be avoided.
The interlayer dielectric layer, i.e., the sub-dielectric layer, may be silicon oxide, and the buffer layer may be silicon nitride. The sub-dielectric layer can be formed by adopting a Chemical Vapor Deposition (CVD) process or a furnace tube process; the buffer layer may be formed using a Chemical Vapor Deposition (CVD) process or an Atomic Layer Deposition (ALD) process. But not limited thereto, the sub-dielectric layer and the buffer layer may be formed using other deposition processes known in the art.
In this embodiment, as shown in fig. 7, the interlayer dielectric layer 102 may include a first sub-dielectric layer 1021, a first buffer layer 1022, a second sub-dielectric layer 1023, a second buffer layer 1024, and a third sub-dielectric layer 1025, which are sequentially stacked.
A patterned mask layer 103 is formed on the interlevel dielectric layer 102 (e.g., on the third sub-dielectric layer 1025), the patterned mask layer 103 serving as a mask for a subsequent etching process. In this embodiment, the interlayer dielectric layer is divided into a plurality of sub-dielectric layers, the buffer layers are arranged between the sub-dielectric layers, and the interlayer dielectric layer is etched in multiple times, so that the etching amount of each etching is small, and the requirement on the mask layer 103 is reduced. For example, the mask layer 103 may be a photoresist layer, which may reduce process complexity, reduce production cost, and improve production efficiency, compared to using a mask layer including an anti-reflective layer + a hard mask layer + a photoresist layer.
Next, step S03 is executed, the sub-dielectric layers (e.g., the first sub-dielectric layer 1021, the second sub-dielectric layer 1023, and the third sub-dielectric layer 1025) of the interlayer dielectric layer 102 and the exposed buffer layers (e.g., the first buffer layer 1022 and the second buffer layer 1024) are etched in several times by using the buffer layers as the etching barrier layers of the sub-dielectric layers, so as to form a through hole 202 on the semiconductor substrate 100, where the through hole 202 exposes the top conductive layer.
Etching each sub-dielectric layer of the interlayer dielectric layer 102 and the exposed buffer layer in a graded manner, and forming the through hole 202 on the semiconductor substrate 100 may include: executing the first etching process, etching the sub-dielectric layer at the top to form a plurality of openings, wherein the openings expose the buffer layer below the sub-dielectric layer at the top, and the etching rate of the first etching process to the sub-dielectric layer is greater than that of the buffer layer; executing the second etching process to remove the buffer layer exposed by the opening, wherein the etching rate of the second etching process to the buffer layer is greater than that of the sub-dielectric layer; and repeatedly executing the first etching process to etch downwards other sub-dielectric layers and executing the second etching process to etch downwards other buffer layers until a through hole exposing the top conducting layer is formed, wherein the through hole penetrates through the sub-dielectric layers and the buffer layers superposed on the semiconductor substrate 200.
In the first etching process, the etching selection ratio of the sub-dielectric layer to the buffer layer can be 20-50. In the second etching process, the etching selection ratio of the buffer layer to the sub-dielectric layer can be 20-50.
Specifically, as shown in fig. 8, the first etching process is performed to etch the top sub-dielectric layer (i.e., the third sub-dielectric layer 1025), and a plurality of first openings 2011 are formed in the third sub-dielectric layer 1025, where the first openings 2011 expose the second buffer layer 1024 under the third sub-dielectric layer 1025.
The etching rate of the sub-medium layer by the first etching process is greater than that of the buffer layer, so that when the third sub-medium layer 1025 is etched by the first etching process, the second buffer layer 1024 can be used as an etching stop layer, the third sub-medium layer 1025 can be fully etched, other sub-medium layers and buffer layers below the second buffer layer 1024 are not easily damaged, the etching uniformity of the third sub-medium layer 1025 can be improved, the formation of the first openings 2011 with the consistent depth in different regions of the semiconductor substrate is facilitated, and preferably, all the first openings penetrate through the third sub-medium layer 1025, and the area and the shape of the second buffer layer 1024 exposed out of each first opening 2011 are the same.
As shown in fig. 9, a second etching process is performed to remove the second buffer layer 1024 exposed by the first opening 2011, so as to form a second opening 2012, and the second sub-dielectric layer 1023 is exposed by the second opening 2012.
The etching rate of the second etching process to the buffer layer is greater than that of the sub-dielectric layer, so that when the second etching process is used for etching the second buffer layer 1024, the second sub-dielectric layer 1023 can be used as an etching stop layer, the second buffer layer 1024 can be etched sufficiently, other sub-dielectric layers and buffer layers below the second sub-dielectric layer 1023 are not damaged easily, the etching uniformity of the second buffer layer 1024 can be improved, and the formation of second openings 2012 with consistent depths in different regions of the semiconductor substrate 100 is facilitated.
As shown in fig. 10, the first etching process is repeatedly performed to remove the second sub-dielectric layer 1023 exposed from the second opening 2012, the first buffer layer 1022 is used as an etching stop layer, a third opening 2013 is formed at the position of the second opening 2012, and the third opening 2013 exposes the first buffer layer 1022.
As shown in fig. 11, the second etching process is repeatedly performed to remove the first buffer layer 1022 exposed by the three openings 2013, the first sub-dielectric layer 1021 is used as an etching stop layer, a fourth opening 2014 is formed at the position of the third opening, and the fourth opening 2014 exposes the first sub-dielectric layer 1021.
As shown in fig. 12, a first etching process is performed again to remove the first sub-dielectric layer 1021 exposed by the fourth opening 2014, a through hole 202 is formed at the position of the fourth opening 2014, and the through hole 202 penetrates through the sub-dielectric layer and the buffer layer stacked on the semiconductor substrate and exposes the top conductive layer 101.
The first opening 1021, the second opening 1022, the third opening 1023 and the fourth opening 1024 are formed in the sub-medium layers and the buffer layers of the interlayer medium layer 102 in a multi-time etching mode in sequence, and the etching uniformity of each sub-medium layer and each buffer layer is good, so that the depth uniformity of each opening formed in different areas of the semiconductor substrate is good, and the depth uniformity of the obtained through holes is improved.
In this embodiment, the first etching is performedThe process and the second etching process may be a reactive ion etching process (RIE). The gas used in the first etching process may include octafluorocyclobutane (C)4F8) And oxygen (O)2) In order to accelerate the etching speed, the gas used in the first etching process may further include argon (Ar). The gas used in the second etching process may include monofluoromethane (CH)3F) And oxygen (O)2)。
Specifically, in the first etching process, the flow rate of the octafluorocyclobutane may be 15sccm to 18sccm, the flow rate of the oxygen may be 5sccm to 6sccm, and the flow rate of the argon may be 450sccm to 550sccm (e.g., 500 sccm). In the second etching process, the flow rate of the fluoromethane may be 20sccm to 40sccm (e.g., 28sccm), and the flow rate of the oxygen may be 75sccm to 100sccm (e.g., 80 sccm).
When the first etching process and the second etching process are performed, the semiconductor substrate is located in a chamber of an etching machine, the pressure in the chamber can be 40mTorr to 60mTorr (for example, 50mTorr), the center-edge gas ratio of the gas introduced into the chamber can be 40% to 50% (for example, 44%), and the power of the radio frequency can be 500W to 1100W (for example, 600W or 1000W).
In this embodiment, after forming the through hole, the manufacturing method may further include: and filling a conductive material in the through hole to form a conductive plug. If desired, a second conductive layer may also be formed on the interlevel dielectric layer 102, and the second conductive layer may be electrically connected to the top conductive layer through the conductive plug.
In the method for manufacturing the semiconductor structure of this embodiment, an interlayer dielectric layer 102 is formed on a semiconductor substrate 100, at least one buffer layer (e.g., a first buffer layer 1022 and a second buffer layer 1024) is sandwiched in the interlayer dielectric layer 102, the buffer layer divides the interlayer dielectric layer 102 into two or more sub-dielectric layers (e.g., a first sub-dielectric layer 1021, a second sub-dielectric layer 1023 and a third sub-dielectric layer 1025), and then the buffer layer is used as an etching barrier layer of the sub-dielectric layers to etch each sub-dielectric layer and the exposed buffer layer in a sub-etching manner, so as to form a through hole 202 on the semiconductor substrate 100. Compared with the existing method in which the interlayer dielectric layer is not clamped with the buffer layer and is etched through at one time, the manufacturing method divides the interlayer dielectric layer into a plurality of sub-dielectric layers and etches each sub-dielectric layer and the buffer layer in a grading manner, can reduce the etching depth of each etching, and the buffer layer is used as an etching barrier layer of the sub-dielectric layer, so that the etching amount of each etching can be conveniently controlled, the etching uniformity of the interlayer dielectric layer 102 can be improved, the depth uniformity of the through holes 202 formed at different positions of the semiconductor substrate 100 is better, and the performance of a semiconductor device can be improved.
Further, the sub-medium layer is etched by the first etching process with the etching rate of the sub-medium layer being greater than that of the buffer layer, the etching can be stopped on the surface of the buffer layer, and the sub-medium layer below the buffer layer is not easy to remove, so that the sub-medium layer on the buffer layer can be fully etched and removed, and a plurality of openings with consistent depths are formed in the sub-medium layer; and then, etching and removing the buffer layer exposed from the opening by adopting a second etching process with the etching rate of the buffer layer larger than that of the sub-dielectric layer, wherein the etching can be stopped on the sub-dielectric layer, so that the buffer layer exposed from the opening can be removed. That is to say, when the interlayer dielectric layer is etched to form the through holes, the etching of the sub-dielectric layer can be stopped on the buffer layer, and the etching of the buffer layer can be stopped on the sub-dielectric layer, so that each sub-dielectric layer and each buffer layer can be fully etched, side etching and over-etching are not easy to occur, the depth uniformity of a plurality of through holes formed by etching the interlayer dielectric layer is improved, and the performance of a semiconductor device is improved.
The embodiment also provides a semiconductor structure, which can be manufactured by the manufacturing method. As shown in fig. 12, the semiconductor structure includes: the semiconductor substrate 100 is provided with a top conducting layer 101, the interlayer dielectric layer 102 is formed on the semiconductor substrate 100, at least one buffer layer is clamped in the interlayer dielectric layer 102, the buffer layer divides the interlayer dielectric layer 102 into more than two sub-dielectric layers, and the through holes 202 penetrate through the interlayer dielectric layer 102 and expose the top conducting layer 101.
Specifically, the interlayer dielectric layer 102 may include three sub-dielectric layers and two buffer layers respectively located between the sub-dielectric layers, for example, the interlayer dielectric layer 102 includes a first sub-dielectric layer 1021, a first buffer layer 1022, a second sub-dielectric layer 1023, a second buffer layer 1024, and a third sub-dielectric layer 1025, which are sequentially stacked. In another embodiment, the interlayer dielectric layer includes five sub-dielectric layers and four buffer layers respectively located between the sub-dielectric layers. The number of the buffer layers can be set according to the thickness of the interlayer dielectric layer or the depth of the through hole.
In this embodiment, the through hole 202 may be filled with a conductive material to form a conductive plug.
Because at least one buffer layer is clamped in the interlayer dielectric layer 102 of the semiconductor structure, the buffer layer divides the interlayer dielectric layer into more than two sub-dielectric layers, a plurality of through holes formed in the interlayer dielectric layer can be formed by etching in multiple times, and each etching step is convenient to control, so that the depth uniformity of the through holes at different positions on the semiconductor substrate is good, and the performance of a semiconductor device is improved.
The above description is only for the purpose of describing the preferred embodiments of the present invention and is not intended to limit the scope of the claims of the present invention, and any person skilled in the art can make possible the variations and modifications of the technical solutions of the present invention using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention, and therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention belong to the protection scope of the technical solutions of the present invention.
Claims (10)
1. A method for fabricating a semiconductor structure, comprising:
providing a semiconductor substrate, wherein the semiconductor substrate is provided with a top conducting layer;
forming an interlayer dielectric layer on the semiconductor substrate, wherein at least one buffer layer is clamped in the interlayer dielectric layer, and the buffer layer divides the interlayer dielectric layer into more than two sub-dielectric layers; and
and etching each sub-dielectric layer of the interlayer dielectric layer and the exposed buffer layer in a graded manner by using the buffer layer as an etching barrier layer of the sub-dielectric layer, and forming a through hole on the semiconductor substrate, wherein the through hole exposes the top conductive layer.
2. The method of fabricating a semiconductor structure of claim 1, wherein etching each sub-dielectric layer of the inter-dielectric layer and the exposed buffer layer in a fractional manner, and forming a via hole in the semiconductor substrate comprises:
executing a first etching process to etch the sub-dielectric layer at the top to form a plurality of openings, wherein the openings expose the buffer layer below the sub-dielectric layer at the top, and the etching rate of the first etching process to the sub-dielectric layer is greater than that of the buffer layer;
executing a second etching process to remove the buffer layer exposed from the opening, wherein the etching rate of the second etching process to the buffer layer is greater than that of the sub-dielectric layer;
and repeatedly executing the first etching process to etch downwards other sub-dielectric layers and executing the second etching process to etch downwards other buffer layers until a through hole exposing the top conducting layer is formed, wherein the through hole penetrates through the sub-dielectric layers and the buffer layers which are superposed on the semiconductor substrate.
3. The method of claim 1, wherein the via has a depth of 1 micron or more.
4. The method of claim 1, wherein the sub-dielectric layer has a thickness of 300nm to 500 nm.
5. The method of claim 1, wherein the buffer layer has a thickness of 30nm to 50 nm.
6. The method for fabricating a semiconductor structure according to any one of claims 1 to 5, wherein the interlayer dielectric layer comprises three sub-dielectric layers and two buffer layers respectively located between the sub-dielectric layers; or the interlayer dielectric layer comprises five sub-dielectric layers and four buffer layers respectively positioned between the sub-dielectric layers.
7. The method for fabricating a semiconductor structure according to any one of claims 1 to 5, wherein the thicknesses of the sub-dielectric layers are all the same or the thickness of the sub-dielectric layer at the lowest layer is the smallest.
8. The method for fabricating the semiconductor structure according to any one of claims 1 to 5, wherein the thickness of the buffer layer is smaller than the thickness of the adjacent sub-dielectric layer.
9. The method of any one of claims 1 to 5, wherein the interlayer dielectric layer is silicon oxide and the buffer layer is silicon nitride.
10. A semiconductor structure, wherein the semiconductor structure is manufactured by the manufacturing method of any one of claims 1 to 9, and comprises:
a semiconductor substrate having a top conductive layer thereon;
the semiconductor substrate comprises an interlayer dielectric layer, a semiconductor substrate and a buffer layer, wherein the interlayer dielectric layer is formed on the semiconductor substrate, at least one buffer layer is clamped in the interlayer dielectric layer, and the buffer layer divides the interlayer dielectric layer into more than two sub-dielectric layers; and
and the through hole penetrates through the interlayer dielectric layer and exposes the top conducting layer.
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