CN115938926A - Preparation method of semiconductor structure and semiconductor structure - Google Patents
Preparation method of semiconductor structure and semiconductor structure Download PDFInfo
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Abstract
The application relates to a preparation method of a semiconductor structure and the semiconductor structure. The preparation method of the semiconductor structure comprises the following steps: providing a substrate; forming an electrode lamination on the surface of the substrate, wherein the electrode lamination comprises a first protective layer, an electrode layer and a second protective layer which are arranged in a lamination mode; forming a plurality of openings which are arranged at intervals in the electrode lamination layer by adopting an etching process; and forming an interlayer dielectric layer in the opening and on the surface of the electrode lamination far away from the substrate by adopting a high-density plasma deposition process, wherein the deposition etching ratio adopted in the high-density plasma deposition process is 3 to 3.5. The first protective layer and the second protective layer respectively protect the upper surface and the lower surface of the electrode layer, so that the electrode layer is prevented from being damaged to generate a cavity; the deposition etching ratio adopted in the high-density plasma deposition process is 3-3.5, so that the time for forming the interlayer dielectric layer is reduced, the stress is reduced, and the generation of electrode layer cavities is reduced.
Description
Technical Field
The present disclosure relates to the field of semiconductor technologies, and in particular, to a method for manufacturing a semiconductor structure and a semiconductor structure.
Background
With the development of Semiconductor technology, HV-CMOS (High Voltage-Complementary Metal Oxide Semiconductor) structures are widely used in Semiconductor products due to their advantages.
The MBIST (memory built-in-self test) is one of yield tests of the HV-CMOS structure, and in the conventional process of preparing the HV-CMOS structure, due to the insufficiency of the preparation process, an electrode layer is not well protected, void (void) is easily generated in the electrode layer, and the yield of the MBIST test result is low.
Disclosure of Invention
In view of the above, it is desirable to provide a method for fabricating a semiconductor structure and a semiconductor structure.
In order to solve the above problems, in one aspect, the present invention provides a method for manufacturing a semiconductor structure, including:
providing a substrate;
forming an electrode lamination on the surface of the substrate, wherein the electrode lamination comprises a first protective layer, an electrode layer and a second protective layer which are arranged in a lamination mode;
forming a plurality of openings which are arranged at intervals in the electrode lamination layer by adopting an etching process;
and forming an interlayer dielectric layer in the opening and on the surface of the electrode lamination layer far away from the substrate by adopting a high-density plasma deposition process, wherein the deposition etching ratio adopted in the high-density plasma deposition process is 3-3.5.
According to the preparation method of the semiconductor structure, the electrode lamination is formed on the surface of the substrate and comprises the first protective layer, the electrode layer and the second protective layer which are arranged in a laminating mode, the first protective layer and the second protective layer respectively protect the upper surface and the lower surface of the electrode layer, and the electrode layer is prevented from being damaged to generate a cavity; an interlayer dielectric layer is formed in the opening of the electrode layer and on the surface of the electrode lamination layer far away from the substrate by adopting a high-density plasma deposition process, and in the process of forming the interlayer dielectric layer, if the time is too long, the stress of the semiconductor structure is increased, and the electrode layer generates a cavity, so that the deposition etching ratio adopted in the high-density plasma deposition process is 3 to 3.5, the time for forming the interlayer dielectric layer is reduced, the stress is reduced, and the generation of the cavity of the electrode layer is reduced.
In one embodiment, the forming an electrode stack on the surface of the substrate includes:
forming the first protective layer on the surface of the substrate;
forming the electrode layer on the surface of the first protective layer away from the substrate;
forming the second protective layer on the surface of the electrode layer far away from the first protective layer; the first protective layer, the electrode layer and the second protective layer are formed in the same vacuum environment.
In one embodiment, the materials of the first protection layer, the electrode layer and the second protection layer all include metals.
In one embodiment, the first protection layer comprises a first conductive layer and a first electrode dielectric layer; the second protective layer comprises a second conductive layer and a second electrode dielectric layer; forming the first protection layer on the surface of the substrate, including:
forming the first conductive layer on the surface of the substrate;
forming the first electrode dielectric layer on the surface of the first conducting layer far away from the substrate;
forming the second protection layer on the surface of the electrode layer far away from the first protection layer, including:
forming the second conducting layer on the surface of the electrode layer far away from the first electrode medium layer;
and forming the second electrode dielectric layer on the surface of the second conducting layer far away from the electrode layer.
In one embodiment, the first conductive layer is a titanium layer; the first electrode dielectric layer is a titanium nitride layer; the second conducting layer is a titanium layer; the second electrode dielectric layer is a titanium nitride layer.
In one embodiment, in the process of forming the plurality of openings arranged at intervals in the electrode stack by using the etching process, the temperature used in the etching process is 58 ℃ to 70 ℃.
In one embodiment, the method further comprises:
carrying out chemical mechanical polishing on the surface of the interlayer dielectric layer away from the electrode lamination;
and forming a plurality of through holes which are arranged at intervals in the interlayer dielectric layer.
The application also provides a semiconductor structure prepared by the preparation method of the semiconductor structure according to any one of the above schemes, wherein the semiconductor structure comprises:
a substrate;
the electrode lamination is positioned on the surface of the substrate and comprises a first protective layer, an electrode layer and a second protective layer which are arranged in a lamination mode; wherein the electrode lamination is internally provided with a plurality of openings which are arranged at intervals;
and the interlayer dielectric layer is positioned in the opening and on the surface of the electrode lamination layer far away from the substrate.
The semiconductor structure comprises an electrode lamination, wherein the electrode lamination comprises a first protective layer, an electrode layer and a second protective layer which are arranged in a lamination mode, the first protective layer and the second protective layer respectively protect the upper surface and the lower surface of the electrode layer, and the electrode layer is prevented from being damaged to generate a cavity; the semiconductor structure is prepared by the preparation method of the semiconductor structure, the high-density plasma deposition process is adopted to form the interlayer dielectric layer in the opening of the electrode layer and on the surface of the electrode lamination layer away from the substrate, and in the process of forming the interlayer dielectric layer, if the time is too long, the stress of the semiconductor structure is increased, and the electrode layer generates a cavity, so that the deposition etching ratio adopted in the high-density plasma deposition process is 3 to 3.5, the time for forming the interlayer dielectric layer is reduced, the stress is reduced, and the generation of the cavity of the electrode layer is reduced.
In one embodiment, the first protective layer is positioned on the surface of the substrate; the electrode layer is positioned on the surface of the first protective layer far away from the substrate; the second protective layer is located on the surface, far away from the first protective layer, of the electrode layer.
In one embodiment, the first protective layer comprises:
the first conducting layer is positioned on the surface of the substrate;
the first electrode dielectric layer is positioned on the surface of the first conducting layer, which is far away from the substrate;
the second protective layer includes:
the second conducting layer is positioned on the surface of the electrode layer, which is far away from the first electrode medium layer;
and the second electrode dielectric layer is positioned on the surface of the second conducting layer, which is far away from the electrode layer.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments or the conventional technologies of the present application, the drawings used in the descriptions of the embodiments or the conventional technologies will be briefly introduced below, it is obvious that the drawings in the following descriptions are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a flow chart of a method of fabricating a semiconductor structure provided in one embodiment;
fig. 2 is a schematic cross-sectional structure diagram of a structure obtained in step S102 of the method for manufacturing a semiconductor structure provided in an embodiment;
fig. 3 is a schematic cross-sectional structure diagram of a structure obtained in step S103 of the method for manufacturing a semiconductor structure provided in an embodiment;
fig. 4 is a schematic cross-sectional structure diagram of a structure obtained in step S104 of the method for manufacturing a semiconductor structure provided in an embodiment;
FIG. 5 is a schematic cross-sectional view of an electrode stack provided in an embodiment;
FIG. 6 is a cross-sectional structural diagram of a semiconductor structure provided in an embodiment;
FIG. 7 is a cross-sectional view of an embodiment of a structure formed by chemical mechanical polishing the surface of the interlevel dielectric layer away from the electrode stack;
fig. 8 is a schematic cross-sectional structure diagram of a structure obtained by forming a plurality of through holes arranged at intervals in an interlayer dielectric layer according to an embodiment.
Description of reference numerals:
1-a substrate; 2-electrode lamination; 20-opening; 21-a first protective layer; 211-a first conductive layer; 212-a first electrode dielectric layer; 22-an electrode layer; 23-a second protective layer; 231 — a second conductive layer; 232-second electrode dielectric layer; 3-a mask layer; 30-a mask window; 4-interlayer dielectric layer; 40-through holes; 5-a silicon-rich oxide layer.
Detailed Description
To facilitate an understanding of the present application, the present application will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present application are shown in the drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on, adjacent to, connected or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present.
Spatial relational terms, such as "under," "below," "under," "over," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations) and the spatial descriptors used herein interpreted accordingly.
As used herein, the singular forms "a", "an" and "the" may include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. Also, as used herein, the term "and/or" includes any and all combinations of the associated listed items.
With the development of Semiconductor technology, HV-CMOS (High Voltage-Complementary Metal Oxide Semiconductor) structures are widely used in Semiconductor products due to their advantages.
MBIST (memory built-in-self test) is one of yield tests of HV-CMOS structures, and in the conventional process of manufacturing HV-CMOS structures, void (void) may be generated in an electrode layer due to defects of a manufacturing process, such as that an electrode layer is not well protected, the process of forming the electrode layer and a protection layer is not in the same vacuum environment, the electrode layer is damaged in the process of forming an opening in the electrode layer, the inner wall of the opening of the electrode layer and the surface of the electrode layer are damaged in the process of subsequently depositing an interlayer dielectric layer, and the like, and the yield of the MBIST test result is low.
In view of the above, it is desirable to provide a method for fabricating a semiconductor structure and a semiconductor structure.
As shown in fig. 1, the present invention provides a method for manufacturing a semiconductor structure, which may include the following steps S101 to S104:
s101: a substrate 1 is provided.
The structure of the substrate 1 can be seen in fig. 2. Illustratively, the material of the substrate 1 may be any suitable material, for example, at least one of the following materials: silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbon (SiC), silicon germanium carbon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), gallium nitride (GaN), or other III/V compound semiconductors, and may be a multilayer structure formed of these semiconductors, or may be Silicon On Insulator (SOI), silicon on insulator (SSOI), silicon on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI), and germanium on insulator (GeOI), or may be a Double Side polished silicon wafer (DSP), and the like, and the present embodiment is not limited thereto.
S102: an electrode stack 2 is formed on a surface of the substrate 1, and the electrode stack 2 includes a first passivation layer 21, an electrode layer 22, and a second passivation layer 23.
For exemplary purposes, the resulting structure can be seen in FIG. 2; the electrode layer 22 may include a metal layer, which may include, but is not limited to, at least one of an aluminum layer, a copper layer, a silver layer, and a tungsten layer. The first protective layer 21 and the second protective layer 23 protect the electrode layer 22 from being oxidized to form oxide and generate voids.
S103: a plurality of spaced apart openings 20 are formed in the electrode stack 2 by an etching process.
Wherein, the etching process may include a dry etching process; the opening 20 exposes a portion of the upper surface of the substrate 1.
Illustratively, before forming the plurality of spaced openings 20 in the electrode stack 2 by using the etching process, the method further includes: forming a mask layer 3 on the surface of the electrode lamination layer 2 far away from the substrate 1, wherein the mask layer 3 is provided with a mask window 30, and the mask window 30 defines the shape and the position of the opening 20; forming a plurality of spaced apart openings 20 in the electrode stack 2 using an etching process includes: the electrode stack 2 is etched based on the mask window 30 to form a plurality of spaced apart openings 20 in the electrode stack 2, and the resulting structure can be seen in fig. 3. The mask layer 3 may include a photoresist layer or a titanium nitride layer; the photoresist layer may include a positive photoresist layer, and may also include a negative photoresist layer. Since mask window 30 has a precise shape and size, electrode stack 2 is etched based on mask window 30 to form a plurality of spaced apart openings 20 in electrode stack 2, and thus the resulting openings 20 also have a precise shape and size. After the opening 20 is formed, the mask layer 3 needs to be removed, and if the mask layer 3 is a photoresist layer, the photoresist layer can be removed by ashing, and then the residual polymer can be removed by wet method, so as to avoid the influence of the polymer remained in the opening 20 and on the surface of the electrode stack 2 on the conductivity of the electrode stack 2, reduce the influence on the inner wall of the opening 20, and reduce the generation of voids in the electrode layer 22.
S104: and forming an interlayer dielectric layer 4 in the opening 20 and on the surface of the electrode lamination 2 far away from the substrate 1 by adopting a high-density plasma deposition process, wherein the deposition etching ratio adopted in the high-density plasma deposition process is 3-3.5.
Referring to fig. 4, the structure obtained in step S104 can be seen, wherein, in the process of forming the interlayer dielectric layer 4 by using the high-density plasma deposition process, the temperature will continuously rise, and if the deposition time is longer, the stress of the semiconductor structure will increase, and the stress of the electrode layer 22 will correspondingly increase, resulting in more voids being formed, so that the deposition time can be reduced, the stress can be reduced, and the voids can be reduced by using a higher deposition-etching ratio in this embodiment.
Illustratively, the interlayer dielectric layer 4 may include an oxide layer, which may include, but is not limited to, at least one of a silicon oxide layer and a silicon oxycarbide layer; the deposition-to-etch ratio may be 3, 3.1, 3.2, 3.3, 3.4, or 3.5, or may be other suitable deposition-to-etch ratios, which is not limited in this embodiment.
The semiconductor structure obtained after steps S101-S104 can be referred to in fig. 4. Of course, in order to facilitate understanding of the present invention, fig. 4 shows an example of a semiconductor structure manufactured by the method for manufacturing a semiconductor structure according to the present invention, and other suitable examples of the semiconductor structure manufactured by the method for manufacturing a semiconductor structure according to the present invention are also possible, and the present invention is not limited thereto.
In the method for manufacturing the semiconductor structure in the above embodiment, the electrode stack 2 is formed on the surface of the substrate 1, the electrode stack 2 includes the first protective layer 21, the electrode layer 22 and the second protective layer 23 which are stacked, and the first protective layer 21 and the second protective layer 23 respectively protect the upper surface and the lower surface of the electrode layer 22, so as to prevent the electrode layer 22 from being damaged and generating voids; an interlayer dielectric layer 4 is formed in the opening 20 of the electrode layer 22 and on the surface of the electrode lamination layer 2 far away from the substrate 1 by adopting a high-density plasma deposition process, and in the process of forming the interlayer dielectric layer 4, if the time is too long, the stress of the semiconductor structure is increased, and the electrode layer 22 generates a cavity, so that the deposition etching ratio adopted in the high-density plasma deposition process is 3 to 3.5, the time for forming the interlayer dielectric layer 4 is reduced, the stress is reduced, the generation of the cavity of the electrode layer 22 is reduced, and the testing yield of the MBIST product is improved.
In one embodiment, still referring to fig. 2, forming the electrode stack 2 on the surface of the substrate 1 may include the following steps: forming a first protection layer 21 on the surface of the substrate 1; forming an electrode layer 22 on the surface of the first passivation layer 21 away from the substrate 1; forming a second passivation layer 23 on the surface of the electrode layer 22 away from the first passivation layer 21; the first passivation layer 21, the electrode layer 22 and the second passivation layer 23 are formed in the same vacuum environment.
In the above embodiment, the first passivation layer 21, the electrode layer 22 and the second passivation layer 23 are formed in the same vacuum environment to prevent the electrode layer 22 from being oxidized or corroded by contaminants in the air to generate voids during the replacement process.
In one embodiment, the materials of the first protective layer 21, the electrode layer 22 and the second protective layer 23 may include metals.
In one embodiment, referring to fig. 5, the first protection layer 21 may include a first conductive layer 211 and a first electrode dielectric layer 212; forming the first protection layer 21 on the surface of the substrate 1 may include the following steps: forming a first conductive layer 211 on the surface of the substrate 1; a first electrode dielectric layer 212 is formed on the surface of the first conductive layer 211 away from the substrate 1. The second passivation layer 23 may include a second conductive layer 231 and a second electrode dielectric layer 232; forming the second passivation layer 23 on the surface of the electrode layer 22 away from the first passivation layer 21 may include the following steps: forming a second conductive layer 231 on the surface of the electrode layer 22 away from the first electrode dielectric layer 212; a second electrode dielectric layer 232 is formed on the surface of the second conductive layer 231 away from the electrode layer 22.
In one embodiment, the first conductive layer 211 may be a titanium layer; the first electrode dielectric layer 212 may be a titanium nitride layer; the second conductive layer 231 may be a titanium layer; the second electrode dielectric layer 232 may be a titanium nitride layer.
In one embodiment, during the process of forming the plurality of spaced openings 20 in the electrode stack 2 by using the etching process, the temperature used in the etching process may be 58 ℃ to 70 ℃.
In the conventional process of etching the electrode stack 2 to form the opening 20, the temperature is generally lower than 40 ℃, so that the etching residual polymer is left in the structure, the conductivity of the electrode layer 22 is reduced, and the electrode layer 22 can generate a cavity; in the process of forming a plurality of openings 20 arranged at intervals in the electrode lamination layer 2 by adopting an etching process, the temperature adopted by the etching process can be 58-70 ℃, so that the polymer remained in the etching process is easier to volatilize, the polymer residue is reduced, the polymer is prevented from remaining in the openings 20 and on the surface of the electrode lamination layer 2 to influence the conductivity of the electrode lamination layer 2, the influence on the inner wall of the openings 20 can be reduced, and the generation of cavities of the electrode layer 22 is reduced.
Illustratively, the electrostatic chuck for bearing the semiconductor structure can be heated through the machine end, so that the temperature of the electrostatic chuck is increased, and the etching residual polymer is not easy to change into a solid state after the temperature is increased, so that the residual polymer is easy to be pumped out of the cavity when being pumped out by the machine end in a gaseous state.
In one embodiment, before forming the interlayer dielectric layer 4 in the opening 20 and on the surface of the electrode stack 2 away from the substrate 1 by using the high density plasma deposition process, the method further includes: and forming a silicon-rich oxide layer 5 in the opening 20 and on the surface of the electrode stack 2 away from the substrate 1. An interlevel dielectric layer 4 is also located on the upper surface of the silicon rich oxide layer 5 and the resulting structure can be seen in fig. 6.
In the above embodiment, before the interlayer dielectric layer 4 is obtained by the high-density plasma deposition process, the silicon-rich oxide layer 5 is deposited, the silicon-rich oxide layer 5 fills a part of the opening 20, and the interlayer dielectric layer 4 is deposited in the remaining space of the opening 20 to fill the opening 20, so that compared with a method in which the interlayer dielectric layer 4 is formed by the high-density plasma deposition process to fill the opening 20, the deposition time of the high-density plasma deposition process can be reduced, the electrode layer 22 can be prevented from generating large stress, and the generation of voids in the electrode layer 22 can be reduced. Wherein, the Silicon content in the Silicon Rich Oxide (SRO) is higher than that in the interlayer dielectric layer 4.
In one embodiment, the method for fabricating a semiconductor structure may further include the steps of: carrying out chemical mechanical polishing on the surface of the interlayer dielectric layer 4 away from the electrode lamination layer 2, wherein the obtained structure is shown in fig. 7; a plurality of through holes 40 are formed in the interlayer dielectric layer 4 at intervals, and the resulting structure is shown in fig. 8.
The through hole 40 further penetrates through the silicon-rich oxide layer 5 located on the surface of the electrode stack 2 away from the substrate 1, a part of the electrode stack 2 is exposed by the through hole 40, an interconnection conductive layer may be filled in the through hole 40, and a conductive structure is formed above the interconnection conductive layer, and the conductive structure is electrically connected with the electrode stack 2 through the interconnection conductive layer.
It should be understood that, although the steps in the flowcharts of the embodiments are shown in sequence as indicated by the arrows, the steps are not necessarily performed in sequence as indicated by the arrows. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise. Moreover, at least a portion of the steps in the flowcharts of the embodiments may include multiple steps or multiple stages, which are not necessarily performed at the same time, but may be performed at different times, and the order of performing the steps or stages is not necessarily sequential, but may be performed alternately or alternately with other steps or at least a portion of the steps or stages in other steps.
The present application further provides a semiconductor structure prepared by the method according to any of the above embodiments, as shown in fig. 4, the semiconductor structure may include: the device comprises a substrate 1, an electrode lamination layer 2 and an interlayer dielectric layer 4; the electrode stack 2 is positioned on the surface of the substrate 1, and the electrode stack 2 comprises a first protective layer 21, an electrode layer 22 and a second protective layer 23 which are arranged in a stacked manner; wherein, the electrode lamination 2 has a plurality of openings 20 arranged at intervals; the interlevel dielectric layer 4 is located within the opening 20 and the surface of the electrode stack 2 remote from the substrate 1.
Illustratively, the material of the substrate 1 may be any suitable material, for example, at least one of the following materials may be mentioned: silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbon (SiC), silicon germanium carbon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), gallium nitride (GaN), or other III/V compound semiconductors, and may be a multilayer structure formed of these semiconductors, or may be Silicon On Insulator (SOI), silicon on insulator (SSOI), silicon on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI), and germanium on insulator (GeOI), or may be Double-Side Polished silicon Wafers (DSP), and the like, and the present embodiment is not limited thereto.
The electrode layer 22 may include a metal layer, which may include, but is not limited to, at least one of an aluminum layer, a copper layer, a silver layer, and a tungsten layer. The first protective layer 21 and the second protective layer 23 protect the electrode layer 22 from being oxidized to form oxide and generate voids. The interlayer dielectric layer 4 may include an oxide layer, which may include, but is not limited to, at least one of a silicon oxide layer and a silicon oxycarbide layer.
The semiconductor structure in the above embodiment includes an electrode stack 2, where the electrode stack 2 includes a first protective layer 21, an electrode layer 22, and a second protective layer 23, and the first protective layer 21 and the second protective layer 23 respectively protect upper and lower surfaces of the electrode layer 22, so as to prevent the electrode layer 22 from being damaged to generate a cavity; the semiconductor structure is prepared by the preparation method of the semiconductor structure, the interlayer dielectric layer 4 is formed in the opening 20 of the electrode layer 22 and on the surface of the electrode lamination layer 2 far away from the substrate 1 by adopting a high-density plasma deposition process, and in the process of forming the interlayer dielectric layer 4, if the time is too long, the stress of the semiconductor structure is increased, and the electrode layer 22 generates a hole, so that the deposition etching ratio adopted in the high-density plasma deposition process is 3 to 3.5, the time for forming the interlayer dielectric layer 4 is reduced, the stress is reduced, the generation of the hole of the electrode layer 22 is reduced, and the testing yield of MBIST products is improved.
In one embodiment, the first protective layer 21 is located on the surface of the substrate 1; the electrode layer 22 is positioned on the surface of the first protective layer 21 away from the substrate 1; the second protective layer 23 is located on the surface of the electrode layer 22 away from the first protective layer 21.
In the above embodiment, the first protection layer 21 and the first protection layer 21 perform isolation protection on the electrode layer 22 to prevent the electrode layer 22 from being oxidized or corroded and damaged by contaminants in the air to generate voids.
In one embodiment, as shown in fig. 6, the first protection layer 21 may include a first conductive layer 211 and a first electrode dielectric layer 212; the first conductive layer 211 is located on the surface of the substrate 1; the first electrode dielectric layer 212 is located on the surface of the first conductive layer 211 away from the substrate 1. The second passivation layer 23 may include a second conductive layer 231 and a second electrode dielectric layer 232; the second conductive layer 231 is located on the surface of the electrode layer 22 away from the first electrode medium layer 212; the second electrode medium layer 232 is located on the surface of the second conductive layer 231 away from the electrode layer 22.
Exemplarily, the first conductive layer 211 may be a titanium layer; the first electrode dielectric layer 212 may be a titanium nitride layer; the second conductive layer 231 may be a titanium layer; the second electrode dielectric layer 232 may be a titanium nitride layer.
In one embodiment, still referring to fig. 6, the semiconductor structure further comprises a silicon-rich oxide layer 5; a silicon-rich oxide layer 5 is located within the opening 20 and on a surface of the electrode stack 2 facing away from the substrate 1, the silicon-rich oxide layer 5 filling a portion of the opening 20; the interlayer dielectric layer 4 is located on the upper surface of the silicon-rich oxide layer 5 and fills the remaining space of the opening 20. Wherein, the Silicon content in the Silicon-Rich Oxide (SRO) layer is higher than the Silicon content in the interlayer dielectric layer 4.
In one embodiment, as shown in fig. 8, the interlayer dielectric layer 4 has a plurality of spaced through holes 40. The through hole 40 further penetrates through the silicon-rich oxide layer 5 located on the surface, away from the substrate 1, of the electrode stack 2, a portion of the electrode stack 2 is exposed by the through hole 40, an interconnection conductive layer may be filled in the through hole 40, and a conductive structure is formed above the interconnection conductive layer, and the conductive structure is electrically connected with the electrode stack 2 through the interconnection conductive layer.
The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features of the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the claims. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (10)
1. A method for fabricating a semiconductor structure, comprising:
providing a substrate;
forming an electrode lamination on the surface of the substrate, wherein the electrode lamination comprises a first protective layer, an electrode layer and a second protective layer which are arranged in a lamination mode;
forming a plurality of openings which are arranged at intervals in the electrode lamination by adopting an etching process;
and forming an interlayer dielectric layer in the opening and on the surface of the electrode lamination layer far away from the substrate by adopting a high-density plasma deposition process, wherein the deposition etching ratio adopted in the high-density plasma deposition process is 3-3.5.
2. The method of claim 1, wherein forming an electrode stack on the surface of the substrate comprises:
forming the first protective layer on the surface of the substrate;
forming the electrode layer on the surface of the first protective layer far away from the substrate;
forming the second protective layer on the surface of the electrode layer far away from the first protective layer; the first protective layer, the electrode layer and the second protective layer are formed in the same vacuum environment.
3. The method according to claim 2, wherein the materials of the first protective layer, the electrode layer and the second protective layer comprise metals.
4. The method of claim 2, wherein the first protective layer comprises a first conductive layer and a first electrode dielectric layer; the second protective layer comprises a second conductive layer and a second electrode dielectric layer; forming the first protective layer on the surface of the substrate, including:
forming the first conductive layer on the surface of the substrate;
forming the first electrode dielectric layer on the surface of the first conductive layer, which is far away from the substrate;
forming the second protection layer on the surface of the electrode layer far away from the first protection layer, including:
forming the second conducting layer on the surface of the electrode layer far away from the first electrode medium layer;
and forming the second electrode dielectric layer on the surface of the second conducting layer far away from the electrode layer.
5. The method according to claim 4, wherein the first conductive layer is a titanium layer; the first electrode dielectric layer is a titanium nitride layer; the second conducting layer is a titanium layer; the second electrode dielectric layer is a titanium nitride layer.
6. The method according to claim 1, wherein the etching process is performed at a temperature of 58 ℃ to 70 ℃ during the step of forming the plurality of openings in the electrode stack at intervals.
7. The method of manufacturing according to claim 1, further comprising:
carrying out chemical mechanical polishing on the surface of the interlayer dielectric layer away from the electrode lamination;
and forming a plurality of through holes which are arranged at intervals in the interlayer dielectric layer.
8. A semiconductor structure produced by the method for producing a semiconductor structure according to any one of claims 1 to 7, the semiconductor structure comprising:
a substrate;
the electrode lamination is positioned on the surface of the substrate and comprises a first protective layer, an electrode layer and a second protective layer which are arranged in a lamination mode; wherein the electrode lamination is internally provided with a plurality of openings which are arranged at intervals;
and the interlayer dielectric layer is positioned in the opening and on the surface of the electrode lamination layer far away from the substrate.
9. The semiconductor structure of claim 8, wherein the first protective layer is on a surface of the substrate; the electrode layer is positioned on the surface of the first protective layer far away from the substrate; the second protective layer is located on the surface, far away from the first protective layer, of the electrode layer.
10. The semiconductor structure of claim 9, wherein the first protective layer comprises:
the first conducting layer is positioned on the surface of the substrate;
the first electrode dielectric layer is positioned on the surface of the first conducting layer, which is far away from the substrate;
the second protective layer includes:
the second conducting layer is positioned on the surface of the electrode layer, which is far away from the first electrode medium layer;
and the second electrode dielectric layer is positioned on the surface of the second conducting layer, which is far away from the electrode layer.
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