CN108389851B - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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CN108389851B
CN108389851B CN201710152679.XA CN201710152679A CN108389851B CN 108389851 B CN108389851 B CN 108389851B CN 201710152679 A CN201710152679 A CN 201710152679A CN 108389851 B CN108389851 B CN 108389851B
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semiconductor die
chip select
terminal
electrically connected
terminals
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CN108389851A (zh
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林柏均
朱金龙
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Nanya Technology Corp
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Nanya Technology Corp
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Abstract

本申请公开一种半导体装置及其制造方法，其中半导体装置包含一第一半导体晶粒以及以一水平偏移方式堆迭至该第一半导体晶粒上的一第二半导体晶粒。该第一半导体晶粒包含一第一芯片选择终端以及电性连接至该第一芯片选择终端的一第一下终端。该第二半导体晶粒包含一第二芯片选择终端及一第二下终端，该第二芯片选择终端经由该第二下终端而电性连接至该第一半导体晶粒的一第一上终端。电性连接至该第二芯片选择终端的该第一上终端与电性连接至该第一芯片选择终端的该第一下终端电性隔离。

Description

半导体装置及其制造方法
技术领域
本公开涉及一种半导体装置及其制造方法，特别关于一种具有多个水平偏移的半导体晶粒的半导体装置及其制造方法。
背景技术
芯片堆迭技术使得两个芯片可配置得更彼此靠近，因而使得该两芯片之间的数据传输更快速且消耗较低功率。存储器芯片可堆迭在一起，以得到具有大储存容量的存储器模块。除了堆迭两个相同芯片之外，亦可堆迭两个不同功能的芯片，以产生提供多重功能的组合。
在存储器芯片堆迭中，各个存储器芯片具有芯片选择(chip selection，CS)终端，其是用以使能该存储器芯片。例如，DRAM芯片可具有列位址选通(row address strobe，RAS)、栏位址选通(column address strobe(CAS)或是芯片选择接脚(chip selectionpin，CSP)作为芯片选择终端。当信号施加于存储器芯片堆迭中的芯片的芯片选择终端时，可存取该芯片，而无法存取该堆迭中的其他芯片。
在现有技术中，施加于存储器芯片堆迭的芯片选择终端的信号会经由线路(wire)传送。此线路的形成需要额外制程，当生产越来越精密的产品时，这会增加信号迹线瑕疵的风险。再者，长线路因占据较大空间而造成信号延迟，并且形成较大的芯片封装尺寸。
上文的“现有技术”说明仅是提供背景技术，并未承认上文的“现有技术”说明公开本公开的标的，不构成本公开的现有技术，且上文的“现有技术”的任何说明均不应作为本公开的任一部分。
发明内容
本公开的实施例提供一种半导体装置，包括一第一半导体晶粒；以一水平偏移方式附接至该第一半导体晶粒上的一第二半导体晶粒；其中该第一半导体晶粒包括一第一芯片选择终端以及电性连接至该第一芯片选择终端的一第一下终端；其中该第二半导体晶粒包括一第二芯片选择终端及一第二下终端，该第二芯片选择终端经由该第二下终端而电性连接至该第一半导体晶粒的一第一上终端，以及电性连接至该第二芯片选择终端的该第一上终端与电性连接至该第一芯片选择终端的该第一下终端电性隔离。
在本公开的一些实施例中，该第一半导体晶粒包括多个第一上终端、多个第一下终端、以及电性连接所述第一上终端与所述第一下终端的多个第一连接插塞；以及第二半导体晶粒包括多个第二上终端、多个第二下终端、以及电性连接所述第二上终端与所述第二下终端的多个第二连接插塞。
在本公开的一些实施例中，该第一半导体晶粒包括一第一芯片选择插塞，电性连接该第一芯片选择终端与所述第一下终端之一。
在本公开的一些实施例中，该第一芯片选择插塞未对准且未电性连接至该第二半导体晶粒的所述第二连接插塞的任何一个。
在本公开的一些实施例中，该第二半导体晶粒包括一第二芯片选择插塞，电性连接该第二芯片选择终端与所述第二下终端之一。
在本公开的一些实施例中，该第二芯片选择插塞对准且电性连接至该第一半导体晶粒的所述第一连接插塞之一。
在本公开的一些实施例中，该第一半导体晶粒包括一基板，该第一芯片选择终端位于该基板上方，以及该第一芯片选择插塞穿过该基板以接触所述第一下终端之一。
在本公开的一些实施例中，该第一半导体晶粒包括一基板与一电路部分，该第一芯片选择插塞穿过该基板，以及该第一连接插塞穿过该基板与该电路部分。
在本公开的一些实施例中，该第一半导体晶粒包括一基板，该第一芯片选择终端位于该基板下方，以及该第一芯片选择插塞接触所述第一下终端之一而未延伸至该基板中。
在本公开的一些实施例中，该第一半导体晶粒包括一基板与一电路部分，该第一芯片选择插塞未延伸至该基板中，以及该第一连接插塞穿过该基板与该电路部分。
在本公开的一些实施例中，该第一连接插塞对准且电性连接至该第一连接插塞正上方的该第二连接插塞。
在本公开的一些实施例中，所述第二下终端至少其中的一未电性连接至所述第一上终端的任何一个。
在本公开的一些实施例中，所述第一上终端的数目不同于所述第一下终端的数目。
在本公开的一些实施例中，所述第一上终端的数目比所述第一下终端的数目少至少一个。
在本公开的一些实施例中，该第一半导体晶粒与该第二半导体晶粒具有相同宽度，并且该第二半导体晶粒的一侧未对准该第一半导体晶粒的一侧。
在一些实施例中，该半导体装置另包括一物件，并且该第一半导体晶粒附接至该物件。
在本公开的一些实施例中，该物件包括多个接点，以及该第一芯片选择终端与该第二芯片选择终端电性连接至该物件的不同接点。
本公开的一些实施例提供一种半导体装置的制造方法，包括：制备具有一第一芯片选择终端的一第一半导体晶粒，其中该第一半导体晶粒包括一第一下终端电性连接至该第一芯片选择终端；制备具有一第二芯片选择终端的一第二半导体晶粒，其中该第二半导体晶粒包括一第二下终端电性连接至该第二芯片选择终端；以及以一水平偏移方式将该第二半导体晶粒附接至该第一半导体晶粒；其中该第二下终端电性连接至该第一半导体晶粒的一第一上终端，以及电性连接至该第二芯片选择终端的该第一上终端与电性连接至该第一芯片选择终端的该第一下终端电性隔离。
在本公开的一些实施例中，该方法另包括以多个接点附接该第一半导体晶粒至一物件，其中该第一芯片选择终端与该第二芯片选择终端电性连接至该物件的不同接点。
本公开涉及一种具有多个水平偏移的半导体晶粒的半导体装置及其制造方法。该多个水平偏移的半导体晶粒的所述芯片选择终端彼此电性隔离；因此，电子信号可被选择性传送至所述半导体晶粒之一，而该半导体装置中其他的半导体晶粒则无法存取。
上文已相当广泛地概述本公开的技术特征及优点，俾使下文的本公开详细描述得以获得优选了解。构成本公开的权利要求标的的其它技术特征及优点将描述于下文。本公开所属技术领域中的技术人员应了解，可相当容易地利用下文公开的概念与特定实施例可作为修改或设计其它结构或制程而实现与本公开相同的目的。本公开所属技术领域中的技术人员亦应了解，这类等效建构无法脱离随附的权利要求所界定的本公开的构思和范围。
附图说明
参阅详细说明与权利要求结合考量附图时，可得以更全面了解本申请案的公开内容，附图中相同的附图标记指代相同的元件。
图1为剖面示意图，例示本公开实施例的半导体装置。
图2为剖面拆解示意图，例示图1的半导体装置。
图3为剖面示意图，例示本公开实施例的半导体装置。
图4为剖面拆解示意图，例示图3的半导体装置。
图5为流程图，例示本公开实施例的半导体装置的制造方法。
图6至图13为示意图，例示本公开实施例通过图5的方法制造半导体装置的制程。
图14至图21为示意图，例示本公开实施例通过图5的方法制造半导体装置的制程。
附图标记说明：
100A 半导体装置
100B 半导体装置
110A 第一半导体晶粒
110A' 第一半导体晶粒
110B 第二半导体晶粒
110B' 第二半导体晶粒
110C 第三半导体晶粒
110C' 第三半导体晶粒
110D 第四半导体晶粒
110D' 第四半导体晶粒
111A 上表面
113A 下表面
115A 右侧
115B 右侧
127A 金属凸块
127B 金属凸块
200 物件
210A 接点
210B 接点
210C 接点
210D 接点
220A 焊球
220B 焊球
220C 焊球
220D 焊球
1101A 基板
1101A' 基板
1102A 底部
1103A 电路部分
1103A' 电路部分
1105A 上终端
1105B 上终端
1107A 下终端
1107B 下终端
1109A 第一芯片选择终端
1109A' 第一芯片选择终端
1109B 第二芯片选择终端
1109B' 第二芯片选择终端
1111A 第一芯片选择插塞
1111A' 第一芯片选择插塞
1111B 第二芯片选择插塞
1111B' 第二芯片选择插塞
1113A 连接插塞
1113B 连接插塞
具体实施方式
本公开的以下说明伴随并入且组成说明书之一部分的附图，说明本公开的实施例，然而本公开并不受限于该实施例。此外，以下的实施例可适当整合以下实施例以完成另一实施例。
“一实施例”、“实施例”、“例示实施例”、“其他实施例”、“另一实施例”等是指本公开所描述的实施例可包含特定特征、结构或是特性，然而并非每一实施例必须包含该特定特征、结构或是特性。再者，重复使用“在实施例中”一语并非必须指相同实施例，然而可为相同实施例。
本公开涉及一种具有多个水平偏移的半导体晶粒的半导体装置及其制造方法。为了使得本公开可被完全理解，以下说明提供详细的步骤与结构。显然，本公开的实施不会限制该技艺中的技术人士已知的特定细节。此外，已知的结构与步骤不再详述，以免不必要地限制本公开。本公开的优选实施例详述如下。然而，除了详细对其进行说明外，本公开亦可广泛实施于其他实施例中。本公开的范围不限于详细说明的内容，而是由权利要求定义。
图1为剖面示意图，例示本公开实施例的半导体装置100A。图2为剖面拆解示意图，例示图1的半导体装置100A。在一些实施例中，半导体装置100A包括物件200、附接至物件200的第一半导体晶粒110A、附接至第一半导体晶粒110A的第二半导体晶粒110B、附接至第二半导体晶粒110B的第三半导体晶粒110C、以及附接至第三半导体晶粒110C的第四半导体晶粒110D。
在一些实施例中，第二半导体晶粒110B以水平偏移方式堆迭至第一半导体晶粒110A上。在一些实施例中，第二半导体晶粒110B横向延伸跨过第一半导体晶粒110A的右侧115A。在一些实施例中，第一半导体晶粒110A与第二半导体晶粒110B具有相同宽度，并且第二半导体晶粒110B的右侧115B未对准第一半导体晶粒110A的右侧115A。在一些实施例中，第二半导体晶粒110B与第一半导体晶粒110A的右侧115A下方之空间可用以配置一装置，该装置可电性连接至物件200或电性连接至所述半导体晶粒。
在一些实施例中，第一半导体晶粒110A包括基板1101A、位于基板1101A上的电路部分1103A、位于第一半导体晶粒110A之上表面111A上的多个上终端1105A、位于第一半导体晶粒110A之下表面113A上的多个下终端1107A、位于电路部分1103A中的第一芯片选择终端1109A、以及电性连接第一芯片选择终端1109A与所述下终端1107A其中之一的第一芯片选择插塞(plug)1111A。在一些实施例中，第一半导体晶粒110A另包括多个连接插塞1113A，电性连接所述上终端1105A与所述下终端1107A。
在一些实施例中，基板1101A可为硅基板、绝缘体上覆半导体(semiconductor-on-insulator，SOI)基板、或是包括半导体材料的任何架构；并且电路部分1103A包括介电材料以及由例如Ti、Al、Ni、镍钒(NiV)、Cu或Cu合金制成的传导元件。在一些实施例中，第一半导体晶粒110A包含集成电路(IC)或半导体组件，例如晶体管、电容器、电阻器、二极管、光二极管、熔丝、或类似物，经配置以进行一或多种功能，其中在本公开中，为清楚说明，未示出的该IC与半导体组件。
在一些实施例中，所述半导体晶粒为与晶圆分离的集成电路晶粒。在一些实施例中，半导体晶粒为存储器芯片，例如DRAM芯片或快闪存储器芯片。已知存储器芯片包括用于寻址存储器胞元的位址输入终端、用于输入数据至存储器胞元且自存储器胞元输出数据的数据输入/输出终端、以及电源终端。
在一些实施例中，第二半导体晶粒110B、第三半导体晶粒110C与第四半导体晶粒110D可具有与第一半导体晶粒110A实质相同的架构。换言之，第二半导体晶粒110B包括多个上终端1105B、多个下终端1107B、电性连接所述上终端1105B与所述下终端1107B的多个连接插塞1113B、第二芯片选择终端1109B、以及电性连接第二芯片选择终端1109B与所述下终端1107B其中之一的第二芯片选择插塞1111B。
在一些实施例中，第一半导体晶粒110A(下方的半导体晶粒)的一些连接插塞1113A(最右边的两个插塞)对准且电性连接至第二半导体晶粒110B(上方的半导体晶粒)的一些对应的连接插塞1113B(中间两个插塞)。在一些实施例中，第二半导体晶粒110B(上方的半导体晶粒)的第二芯片选择插塞1111B对准且电性连接至第一半导体晶粒110A(下方的半导体晶粒)的一个连接插塞1113A(最左边的插塞)。
在一些实施例中，第一半导体晶粒110A的第一芯片选择终端1109A与第二半导体晶粒110B的第二芯片选择终端1109B经配置以电性连接逻辑电路中的MOS晶体管之栅极终端，该逻辑电路例如DRAM芯片的周边电路，并且MOS晶体管经配置以控制是否允许命令指令自其源极终端传播至漏极终端。
在一些实施例中，第一半导体晶粒110A之上终端1105A的数目可不同于第一半导体晶粒110A之下终端1107A的数目。在一些实施例中，所述上终端1105A的数目比所述下终端1107A的数目少至少一个终端。在一些实施例中，第二半导体晶粒110B的所述下终端1107B之一(最右边那个)未电性连接至第一半导体晶粒110A的所述上终端1105A。
在一些实施例中，物件200为封装电路基板或硅/玻璃中介物(interposer)，具有多个接点210A、210B、210C与210D。此外，该封装电路基板或硅/玻璃中介物亦具有多个焊球或凸块(例如，铜柱凸块)220A、220B、220C与220D分别附接至该多个接点210A、210B、210C与210D。在一些实施例中，第一半导体晶粒110A的该多个下终端1107A经由多个金属凸块127而分别附接至封装电路基板200的该多个接点210A、210B、210C与210D。
在一些实施例中，第一半导体晶粒110A的第一芯片选择终端1109A经由第一芯片选择插塞1111A、所述下终端1107A之一、以及第一半导体晶粒110A与物件200之间的所述金属凸块127A之一而电性连接至物件200的接点210A。在一些实施例中，第二半导体晶粒110B的第二芯片选择终端1109B经由第二芯片选择插塞1111B、第二半导体晶粒110B的所述下终端1107B之一、以及第二半导体晶粒110B与第一半导体晶粒110A之间的所述金属凸块127B之一而电性连接至第一半导体晶粒110A的所述上终端1105A之一。
此外，第一半导体晶粒110A的最左上终端1105A，其是电性连接至第二半导体晶粒110B的第二芯片选择终端1109B，另经由所述插塞1113A之一、第一半导体晶粒110A的所述下终端1107A之一以及所述金属凸块127A之一而电性连接至物件200的接点210B。在一些实施例中，第一半导体晶粒110A的所述上终端1105A(以及对应的下终端1107A)，其是电性连接至第二半导体晶粒110B的第二芯片选择终端1109B，未电性连接至下终端1107A，该下终端1107A是电性连接至第一半导体晶粒110A的第一芯片选择终端1109A。因此，第二芯片选择终端1109B与第一芯片选择终端1109A电性隔离。
在一些实施例中，经由焊球220B、接点210B、第一半导体晶粒110A的连接插塞1113A以及第二半导体晶粒110B的芯片选择插塞1111B，电子信号经选择性传送至第二半导体晶粒110B的第二芯片选择终端1109B；因此，第二半导体晶粒110B经选择用于操作并且可被存取，同时无法存取其他非经选择的半导体晶粒。同样地，可经由焊球220A通过选择性传送电子信号而选择第一半导体晶粒110A用于操作且存取第一半导体晶粒110A，可经由焊球220C通过选择性传送电子信号而选择第三半导体晶粒110C用于操作且存取第三半导体晶粒110C，以及可经由焊球220D通过选择性传送电子信号而选择第四半导体晶粒110D用于操作且存取第四半导体晶粒110D。
图3为剖面示意图，例示本公开实施例的半导体装置100B。图4为剖面拆解示意图，例示图3的半导体装置。在一些实施例中，半导体装置100B包括物件200、附接至物件200的第一半导体晶粒110A'、附接至第一半导体晶粒110'的第二半导体晶粒110B'、附接至第二半导体晶粒110B'的第三半导体晶粒110C'、以及附接至第三半导体晶粒110C'的第四半导体晶粒110D'。在图1中，所述半导体晶粒以面朝上方式(face-up manner)堆迭至物件200上，而图3中的半导体晶粒是以面朝下方式(face-down manner)堆迭至物件200上。
在图1与图2的面朝上堆迭中，具有第一芯片选择终端1109A的电路部分1103A为半导体晶粒的上部，基板1101A为半导体晶粒的下部，并且该下部面对物件200；其中第一芯片选择插塞1111A穿过基板1101A以接触对应的下终端1107A。在图3与图4所示的面朝下堆迭中，具有第一芯片选择终端1109A'的电路部分1103A'为半导体晶粒的下部，基板1101A'为半导体晶粒的上部，并且该下部面对物件200；其中第一芯片选择插塞1111A'接触对应的下终端1107A而未延伸至基板1101A'中。
图5为流程图，例示本公开实施例之半导体装置的制造方法。在一些实施例中，可通过图5的方法300形成半导体装置。方法300包含一些操作，并且描述与说明不被视为操作顺序的限制。方法300包含一些步骤(301、303与305)。
图6至图13为示意图，例示本公开实施例通过图5之方法制造半导体装置的制程。在步骤301中，提供具有第一芯片选择终端1109A的第一半导体晶粒110A，如图6至10所示。
在图6中，第一芯片选择插塞1111A与多个连接插塞1113A形成于基板1101A中。在一些实施例中，第一芯片选择插塞1111A与连接插塞1113A的形成包含进行微影蚀刻制程以于基板1101A中形成多个孔洞，而后用导体填充所述孔洞。在一些实施例中，使用钨(W)作为该导体，但亦可使用其他传导材料。
在图7中，进行微影蚀刻制程，以于第一芯片选择插塞1111A上形成第一芯片选择终端1109A。此外，通过制造制程，增加所述连接插塞1113A的高度。
在图8中，进行微影蚀刻制程以于基板1101A上形成电路部分1103A，并且于所述连接插塞1113A上形成多个第一上终端1105A，其中第一芯片选择终端1109A嵌置于电路部分1103A中。
在图9中，自基板1101A的底侧进行研磨制程，以移除底部1102A，因而暴露第一芯片选择插塞1111A与所述连接插塞1113A的底端。
在图10中，在下表面113A上形成多个下终端1107A，其中所述下终端1107A之一电性连接至第一芯片选择插塞1111A。而后，在所述下终端1107a上形成一些金属凸块127A，因而完成第一半导体晶粒110A。
在图11中，第一半导体晶粒110A以多个接点210A、210B、210C与210D附接至物件200，其中第一芯片选择终端1109A经由第一芯片选择插塞1111A、所述下终端1101A之一、以及所述金属凸块127之一而电性连接至接点210A。
在步骤302中，如图12所示，提供具有第二芯片选择终端1109B的第二半导体晶粒110B，其中第二半导体晶粒110B包括第二下终端1107B经由第二芯片选择插塞1111B电性连接至第二芯片选择终端1109B。在一些实施例中，第二半导体晶粒110B的制造可与图6至10所示的第一半导体晶粒110A的制造相同。
在步骤303中，第二半导体晶粒110B以水平偏移方式堆迭至第一半导体晶粒110A上。第一半导体晶粒110A的上终端1105A(与对应的下终端1107A)，其电性连接至第二半导体晶粒110B的第二芯片选择终端1109B，是未电性连接至下终端1107A，该下终端电性连接至第一半导体晶粒110A的第一芯片选择终端1109A；因此，第二芯片选择终端1109B与第一芯片选择终端1109A电性隔离。换言之，第一芯片选择终端1109A与第二芯片选择终端1109B电性连接至第一半导体晶粒110A之不同下终端1107A与物件200之不同接点。
此外，参阅图13，以水平交错方式(horizontally staggered manner)，第三半导体晶粒110C经制造且附接至第二半导体晶粒110B，第四半导体晶粒110经制造且附接至第三半导体晶粒110C，以及更多半导体晶粒可经制造且附接至第四半导体晶粒110D。
图14至21为示意图，例示本公开实施例通过图5之方法制造半导体装置的制程。在步骤301中，提供具有第一芯片选择终端1109A'的第一半导体晶粒，如图14至18所示。
在图14中，在芯片1101中，形成多个连接插塞1113A。在一些实施例中，所述连接插塞1113A的形成包含进行微影蚀刻制程，以于基板1101A中形成多个孔洞，而后用导体填充所述孔洞。在一些实施例中，使用钨(W)作为导体，但亦可使用其他传导材料。
在图15中，进行沉积、微影与蚀刻制程，以形成第一芯片选择终端1109A'于基板1101A'上。此外，通过制造制程，增加所述连接插塞1113A的高度。
在图16中，进行沉积、微影与蚀刻制程，以形成具有第一芯片选择插塞1111A'的电路部分1103A'于基板1101A'上，而后形成多个下终端1107A于下表面113A上，其中所述下终端1107A之一电性连接至第一芯片选择插塞1111A'。而后，形成多个金属凸块127A于所述下终端1107A上。
在图17中，自基板1101A'的底侧进行研磨制程，以移除底部1102A，因而暴露连接插塞1113A'的底端。
在图18中，在所述连接插塞1113A上形成多个上终端1105A，以完成第一半导体晶粒110A'。
在图19中，第一半导体晶粒110A'被上下颠倒且以多个接点210A、210B、210C与210D附接至物件200，其中第一芯片选择终端1109A'经由第一芯片选择终端1111A'、所述下终端1107A之一与所述金属凸块127之一而电性连接至接点210A。
在步骤302中，如图20所示，提供具有第二芯片选择终端1109B'的第二半导体晶粒110B'，其中第二半导体晶粒110B'包括第二下终端1107B经由第二芯片选择插塞1111B'电性连接至第二基片选择终端1109B'。在一些实施例中，第二半导体晶粒110B'的制造可与图14至19所示的第一半导体晶粒110A'的制造相同。
在步骤303中，第二半导体晶粒110B'以水平偏移方式堆迭至第一半导体晶粒110A'上。第一半导体晶粒110A'的上终端1105A(与对应的下终端1107A)，其是电性连接至第二半导体晶粒110B'的第二芯片选择终端1109B'，未电性连接至下终端1107A，该下终端电性连接至第一半导体晶粒110A'的第一芯片选择终端1109A'；因此，第二芯片选择终端1109B'与第一芯片选择终端1109A'电性隔离。换言之，第一芯片选择终端1109A'与第二芯片选择终端1109B'电性连接至第一半导体晶粒110A'的不同下终端1107A与物件200的不同接点。
此外，参阅图21，以水平偏移方式，第三半导体晶粒110C'经制造且附接至第二半导体晶粒110B'，第四半导体晶粒110'经制造且附接至第三半导体晶粒110C'，以及更多的半导体晶粒可经制造且附接至第四半导体晶粒110D'。
本公开涉及一种具有多个水平偏移的半导体晶粒之半导体装置及其制造方法。该多个水平偏移的半导体晶粒之芯片选择终端彼此电性隔离；因此，电子信号可被选择性传送至所述半导体晶粒之一，而该半导体装置中其他的半导体晶粒则无法存取。
本公开的一实施例提供一种半导体装置，包括一第一半导体晶粒；以一水平偏移方式附接至该第一半导体晶粒上的一第二半导体晶粒；其中该第一半导体晶粒包括一第一芯片选择终端以及电性连接至该第一芯片选择终端的一第一下终端；其中该第二半导体晶粒包括一第二芯片选择终端及一第二下终端，该第二芯片选择终端经由该第二下终端而电性连接至该第一半导体晶粒的一第一上终端，以及电性连接至该第二芯片选择终端的该第一上终端与电性连接至该第一芯片选择终端的该第一下终端电性隔离。
本公开的另一实施例提供一种半导体装置的制造方法，包括：制备具有一第一芯片选择终端的一第一半导体晶粒，其中该第一半导体晶粒包括一第一下终端电性连接至该第一芯片选择终端；制备具有一第二芯片选择终端的一第二半导体晶粒，其中该第二半导体晶粒包括一第二下终端电性连接至该第二芯片选择终端；以及以一水平偏移方式将该第二半导体晶粒附接至该第一半导体晶粒；其中该第二下终端电性连接至该第一半导体晶粒的一第一上终端，以及电性连接至该第二芯片选择终端的该第一上终端与电性连接至该第一芯片选择终端的该第一下终端电性隔离。
虽然已详述本公开及其优点，然而应理解可进行各种变化、取代与替代而不脱离权利要求所定义的本公开的构思与范围。例如，可用不同的方法实施上述的许多制程，并且以其他制程或其组合替代上述的许多制程。
再者，本申请的范围并不受限于说明书中所述的制程、机械、制造、物质组成物、手段、方法与步骤的特定实施例。本领域的技术人士可自本公开的公开内容理解可根据本公开而使用与本文所述的对应实施例具有相同功能或是达到实质相同结果之现存或是未来发展的制程、机械、制造、物质组成物、手段、方法、或步骤。据此，这些制程、机械、制造、物质组成物、手段、方法、或步骤是包含于本申请的权利要求的范围内。

Claims (15)

1.一种半导体装置，包括：
一第一半导体晶粒，包括一基板与一电路部分；
一第二半导体晶粒，以一水平偏移方式附接至该第一半导体晶粒上；
其中该第一半导体晶粒包括一第一芯片选择终端、多个第一上终端、多个第一下终端、一第一芯片选择插塞及多个第一连接插塞，该第一芯片选择终端嵌置于电路部分中，该第一芯片选择插塞穿过该基板以接触该第一芯片选择终端与所述第一下终端之一，所述第一连接插塞穿过该基板与该电路部分以接触所述第一上终端与其他所述第一下终端；
其中该第二半导体晶粒包括一第二芯片选择终端及多个第二下终端，该第二芯片选择终端经由所述第二下终端之一而电性连接至该第一半导体晶粒的所述第一上终端之一，电性连接至该第二芯片选择终端的该第一半导体晶粒的该第一上终端与电性连接至该第一芯片选择终端的该第一下终端电性隔离。
2.如权利要求1所述的半导体装置，其中：
该第二半导体晶粒包括多个第二上终端、以及电性连接该第二上终端与其他所述第二下终端的多个第二连接插塞。
3.如权利要求2所述的半导体装置，其中该第一芯片选择插塞未对准且未电性连接至该第二半导体晶粒的所述第二连接插塞之一。
4.如权利要求2所述的半导体装置，其中该第二半导体晶粒包括一第二芯片选择插塞，电性连接该第二芯片选择终端与所述第二下终端之一。
5.如权利要求4所述的半导体装置，其中该第二芯片选择插塞对准且电性连接至该第一半导体晶粒的所述第一连接插塞之一。
6.如权利要求2所述的半导体装置，其中该第一连接插塞对准且电性连接至该第一连接插塞正上方的所述第二连接插塞之一。
7.如权利要求2所述的半导体装置，其中所述第二下终端的至少其中之一未电性连接至所述第一上终端。
8.如权利要求2所述的半导体装置，其中所述第一上终端的数目不同于所述第一下终端的数目。
9.如权利要求2所述的半导体装置，其中所述第一上终端的数目比该第一下终端的数目少至少一个终端。
10.如权利要求1所述的半导体装置，其中该第一半导体晶粒与该第二半导体晶粒具有相同宽度，并且该第二半导体晶粒的一侧未对准该第一半导体晶粒的一侧。
11.如权利要求1所述的半导体装置，其中该第二半导体晶粒横向延伸跨过该第一半导体晶粒的一侧。
12.如权利要求1所述的半导体装置，另包括一物件，其中该第一半导体晶粒附接至该物件。
13.如权利要求12所述的半导体装置，其中该物件包括多个接点，以及该第一芯片选择终端与该第二芯片选择终端电性连接至该物件的不同接点。
14.一种半导体装置的制造方法，包括：
提供一第一半导体晶粒，包括如下步骤：形成穿过一基板的一第一芯片选择插塞与多个连接插塞；于该第一芯片选择插塞上形成第一芯片选择终端；于该基板上形成一电路部分，并且于所述连接插塞上形成多个第一上终端，其中第一芯片选择终端嵌置于电路部分中；以及于该第一芯片选择插塞与所述连接插塞下形成多个第一下终端；
提供具有一第二芯片选择终端的一第二半导体晶粒，其中该第二半导体晶粒包括一第二下终端电性连接至该第二芯片选择终端；以及
以一水平偏移方式将该第二半导体晶粒附接至该第一半导体晶粒；
其中该第二下终端电性连接至该第一半导体晶粒的所述第一上终端之一，以及电性连接至该第二芯片选择终端的该第一上终端与电性连接至该第一芯片选择终端的该第一下终端电性隔离。
15.如权利要求14所述的制造方法，另包括：以多个接点将该第一半导体晶粒附接至一物件，其中该第一芯片选择终端与该第二芯片选择终端电性连接至该物件的不同接点。
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