CN108363825A - A kind of encapsulation bonding line design method of impedance matching, electronic equipment and storage medium - Google Patents
A kind of encapsulation bonding line design method of impedance matching, electronic equipment and storage medium Download PDFInfo
- Publication number
- CN108363825A CN108363825A CN201711251091.6A CN201711251091A CN108363825A CN 108363825 A CN108363825 A CN 108363825A CN 201711251091 A CN201711251091 A CN 201711251091A CN 108363825 A CN108363825 A CN 108363825A
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- impedance
- matching
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- bonding line
- curve
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/36—Circuit design at the analogue level
- G06F30/367—Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
Abstract
The invention discloses a kind of encapsulation bonding line design method of impedance matching, including：Establish simulation model；Extract the scattering parameter of simulation model；The parameter of matching impedance is calculated according to scattering parameter；Matching impedance is completed in simulation model according to the parameter of matching impedance.The invention also discloses a kind of electronic equipment and storage mediums, encapsulation bonding line design method of impedance matching, electronic equipment and storage medium provided by the invention, by establishing chip, bonding line and the simulation model of substrate, extract the scattering parameter of simulation model, the parameter of matching impedance is calculated according to scattering parameter, matching impedance is completed in simulation model, so as to which the impedance matching of bonding line is rapidly completed, to meet the requirement of high-frequency high-speed signal transmission.
Description
Technical field
The present invention relates to encapsulation optimum design method more particularly to a kind of encapsulation bonding line design method of impedance matching, electricity
Sub- equipment and storage medium.
Background technology
Currently, for chip package, common signal interconnection mode is bonding line from chip to substrate, this interconnection process at
It is ripe reliable, go so far as today with integrated circuit.But as chip develops to high-speed high frequency, especially light recent years
The progress of the communication technology, signal transmission rate tens Gbps or even Gbps up to a hundred easily, this carrys out the interconnection belt of chip and substrate
Great challenge.The inductance characteristic of bonding line so that high-impedance behavior is presented in high frequency, hinders effective biography of high-frequency signal
It is defeated, become the bottleneck of signal transmission.Solving transmission bottleneck in this, there are two types of methods：One is to give up bonding line interconnection, uses other
Interconnection structure, but the rising of processing cost can be caused in this way；Second is that using the method for impedance matching, existing impedance matching side
Method needs to design equivalent circuit to carry out matching impedance, and calculating is cumbersome.
Invention content
For overcome the deficiencies in the prior art, one of the objects of the present invention is to provide a kind of encapsulation bonding line impedance matchings
Design method, to solve the problems, such as that it is cumbersome that existing impedance matching methods calculate.
The second object of the present invention of the present invention is to provide a kind of electronic equipment, to solve in terms of existing impedance matching methods
Cumbersome problem.
An object of the present invention adopts the following technical scheme that realization：
A kind of encapsulation bonding line design method of impedance matching, including：
Establish simulation model, wherein the simulation model includes chip, bonding line and substrate, and the chip passes through described
Bonding line and the substrate connection；
Extract the scattering parameter of the simulation model；
The parameter of matching impedance is calculated according to the scattering parameter；
According to the parameter of the matching impedance matching impedance is completed in the simulation model.
Further, the parameter that matching impedance is calculated according to the scattering parameter includes：
The scattering parameter is imported into Smith chart；
The parameter of the matching impedance is found out in the Smith chart.
Further, the parameter that the matching impedance is found out in the Smith chart includes：
The impedance point of bonding line is oriented in the Smith chart according to the scattering parameter；
It obtains and presets impedance value, rail is drawn on the Smith chart according to the default impedance value and the impedance point
Trace curve is overlapped until the terminal of the geometric locus with the center of circle of the Smith chart, and the parameter of the geometric locus is
The parameter of the matching impedance.
Further, described obtain presets impedance value, close in the history according to the default impedance value and the impedance point
On this circle diagram track drafting curve until the geometric locus overlap with the center of circle of the Smith chart including：
The first impedance value is obtained, the first curve is drawn by endpoint of the impedance point according to first impedance value；
The second impedance value is obtained, the second song is drawn by endpoint of the terminal of first curve according to second impedance value
Line, wherein the terminal of second curve is the center of circle of the Smith chart.
Further, described obtain presets impedance value, close in the history according to the default impedance value and the impedance point
Track drafting curve further includes until the geometric locus is overlapped with the center of circle of the Smith chart on this circle diagram：
The width that the first matching microstrip line is calculated according to first impedance value, second is calculated according to second impedance value
Match the width of microstrip line.
Further, first length of a curve is the described first length for matching microstrip line, second curve
Length is the described second length for matching microstrip line.
Further, the parameter according to the matching impedance completes matching impedance in the simulation model and includes：
It is micro- according to the width of the first matching microstrip line, the length of the first matching microstrip line, second matching
The length of width with line and the second matching microstrip line draws out first matching on the substrate of the simulation model
Microstrip line and the second matching microstrip line.
The second object of the present invention adopts the following technical scheme that realization：
A kind of electronic equipment, including：Processor；
Memory；And program, wherein described program is stored in the memory, and is configured to by processor
It executes, described program includes for executing above-mentioned method.
The invention further relates to a kind of computer readable storage mediums, are stored thereon with computer program, the computer journey
Sequence is executed by processor above-mentioned method.
Compared with prior art, the beneficial effects of the present invention are：The simulation model for establishing chip, bonding line and substrate, carries
The scattering parameter for taking simulation model calculates the parameter of matching impedance according to scattering parameter, and matching resistance is completed in simulation model
It is anti-, so as to which the impedance matching of bonding line is rapidly completed, to meet the requirement of high-frequency high-speed signal transmission.
Description of the drawings
Fig. 1 is the flow chart of encapsulation bonding line design method of impedance matching provided in an embodiment of the present invention；
Fig. 2 is the emulation mould before the matching impedance of encapsulation bonding line design method of impedance matching provided in an embodiment of the present invention
The schematic diagram of type；
Fig. 3 is the signal of the Smith chart of encapsulation bonding line design method of impedance matching provided in an embodiment of the present invention
Figure；
Fig. 4 is the emulation mould after the matching impedance of encapsulation bonding line design method of impedance matching provided in an embodiment of the present invention
The schematic diagram of type；
Fig. 5 is electronic equipment schematic diagram provided in an embodiment of the present invention.
Specific implementation mode
In the following, in conjunction with attached drawing and specific implementation mode, the present invention is described further, it should be noted that not
Under the premise of conflicting, new implementation can be formed between various embodiments described below or between each technical characteristic in any combination
Example.
As shown in Figure 1, encapsulation bonding line design method of impedance matching provided in an embodiment of the present invention, including：
Step S101：Establish simulation model.
Wherein, as shown in Fig. 2, simulation model includes chip 1, substrate 2 and bonding line 3, chip 1 passes through bonding line 3 and base
Plate 2 connects.Simulation model is drawn out according to the size of chip 1, substrate 2 and bonding line 3.
Step S102：Extract the scattering parameter of the simulation model.
Specifically, extracting scattering parameter according to the simulation model drawn out, wherein scattering parameter is to be used for assessment signal
The parameter of signal transmission characteristics in transmission process includes the amplitude and phase information of signal, is extracted by electromagnetic simulation software imitative
The scattering parameter of true mode is the prior art, and details are not described herein.
Step S103：The parameter of matching impedance is calculated according to the scattering parameter.
Specifically, the step includes：
Step S1031：The scattering parameter is imported into Smith chart.
Step S1032：The parameter of the matching impedance is found out in Smith's original circle diagram.
Specifically, as shown in figure 3, Smith chart is the polar diagram of reflectance factor, Smith chart subscript, which is painted with, returns
One changes input impedance equivalence family of circles.Scattering parameter is imported into Smith chart, you can bonding line is oriented in Smith chart
Impedance point a；It obtains and presets impedance value, track drafting curve is straight on Smith chart according to default impedance value and impedance point a
The center of circle of terminal and Smith chart to geometric locus overlaps, the parameter of geometric locus is the parameter of matching impedance, and use is micro-
Band line indicates that terminated line, default impedance are associated with the width of microstrip line, and the width of microstrip line can be obtained according to default impedance value
Degree, the corresponding length of geometric locus is the length of microstrip line.
As preferred embodiment, after orienting impedance point a according to scattering parameter, the first impedance value is obtained, is equivalent to
The serial or parallel connection resistance in simulation model, resistance value are the microstrip line of counterpart impedance.According to the first impedance value with impedance point a
The first curve ab is drawn for endpoint；First impedance value is associated with the width of the first matching microstrip line, first in Smith chart
Impedance value corresponds to the width of the first matching microstrip line, and the length of the first curve ab corresponds to the length of the first matching microstrip line.It obtains
The second impedance value is taken, continuation serial or parallel connection microstrip line in simulation model is equivalent to, according to the second impedance value with the first curve
Terminal b be endpoint draw the second curve bc, be moving curve in Smith chart, until terminal c and the history of the second curve are close
The center of circle of this circle diagram overlaps, i.e., the terminal of the second curve bc is the center of circle of Smith chart, and the second impedance value matches micro- with second
Width association with line, in Smith chart, the second impedance value corresponds to the width of the second matching microstrip line, the second curve bc
Length correspond to second matching microstrip line length.For example, the width of the first microstrip line of design is 0.55 millimeter, the matched
One length of a curve is 0.52 millimeter, i.e., the length of the first microstrip line is 0.52 millimeter；The width for designing the second microstrip line is
0.08 millimeter, the second length of a curve matched is 1.23 millimeters, i.e., the length of the second microstrip line is 1.23 millimeters.
Step S104：According to the parameter of the matching impedance matching impedance is completed in the simulation model.
Specifically, as shown in figure 4, according to first matching microstrip line width, first matching microstrip line length, second
The length of width and the second matching microstrip line with microstrip line draws out 4 He of the first matching microstrip line on the substrate of simulation model
Second matching microstrip line 5, the first matching microstrip line 4 and second match microstrip line 5 and are connect with the transmission line on substrate.By upper
State method, you can the impedance matching of chip package bonding line is rapidly completed, the matching impedance of simulation model is applied to actual
In chip package, the requirement of high-frequency high-speed signal transmission can be met.
As shown in figure 5, electronic equipment provided in an embodiment of the present invention, including：Processor 11, memory 12 and program,
Its Program is stored in memory 12, and is configured to be executed by processor 11, and program includes above-mentioned for executing
Method.
The method in electronic equipment and previous embodiment in the present embodiment is based on two sides under same inventive concept
Face is in front described in detail method implementation process, so those skilled in the art can be clear according to foregoing description
The implementation process for understanding to Chu the electronic equipment in the present embodiment, in order to illustrate the succinct of book, details are not described herein again.
As seen through the above description of the embodiments, those skilled in the art can be understood that the present invention can
It is realized by the mode of software plus required general hardware platform.Based on this understanding, technical scheme of the present invention essence
On in other words the part that contributes to existing technology can be expressed in the form of software products.The invention further relates to one kind
Computer readable storage medium, such as ROM/RAM, magnetic disc, CD, are stored thereon with computer program, and computer program is located
Reason device executes above-mentioned method.
Encapsulation bonding line design method of impedance matching, electronic equipment and storage medium provided by the invention, by establishing core
The simulation model of piece, bonding line and substrate, extracts the scattering parameter of simulation model, and matching impedance is calculated according to scattering parameter
Parameter, addition matching microstrip line, completes matching impedance, so as to which the impedance of bonding line is rapidly completed in simulation model
Match, to meet the requirement of high-frequency high-speed signal transmission.
The above embodiment is only the preferred embodiment of the present invention, and the scope of protection of the present invention is not limited thereto,
The variation and replacement for any unsubstantiality that those skilled in the art is done on the basis of the present invention belong to institute of the present invention
Claimed range.
Claims (9)
1. a kind of encapsulation bonding line design method of impedance matching, which is characterized in that including：
Establish simulation model, wherein the simulation model includes chip, bonding line and substrate, and the chip passes through the bonding
Line and the substrate connection；
Extract the scattering parameter of the simulation model；
The parameter of matching impedance is calculated according to the scattering parameter；
According to the parameter of the matching impedance matching impedance is completed in the simulation model.
2. encapsulation bonding line design method of impedance matching according to claim 1, which is characterized in that described to be dissipated according to described
It penetrates parameter and calculates the parameter of matching impedance and include：
The scattering parameter is imported into Smith chart；
The parameter of the matching impedance is found out in the Smith chart.
3. encapsulation bonding line design method of impedance matching according to claim 2, which is characterized in that described close in the history
The parameter that the matching impedance is found out in this circle diagram includes：
The impedance point of bonding line is oriented in the Smith chart according to the scattering parameter；
It obtains and presets impedance value, track drafting is bent on the Smith chart according to the default impedance value and the impedance point
Line is overlapped until the terminal of the geometric locus with the center of circle of the Smith chart, and the parameter of the geometric locus is described
The parameter of matching impedance.
4. encapsulation bonding line design method of impedance matching according to claim 3, which is characterized in that described to obtain pre- handicapping
Anti- value, according to the default impedance value and the impedance point on the Smith chart track drafting curve until the track
Curve overlapped with the center of circle of the Smith chart including：
The first impedance value is obtained, the first curve is drawn by endpoint of the impedance point according to first impedance value；
The second impedance value is obtained, the second curve is drawn by endpoint of the terminal of first curve according to second impedance value,
Wherein, the terminal of second curve is the center of circle of the Smith chart.
5. encapsulation bonding line design method of impedance matching according to claim 4, which is characterized in that described to obtain pre- handicapping
Anti- value, according to the default impedance value and the impedance point on the Smith chart track drafting curve until the track
Curve is overlapped with the center of circle of the Smith chart：
The width that the first matching microstrip line is calculated according to first impedance value calculates the second matching according to second impedance value
The width of microstrip line.
6. encapsulation bonding line design method of impedance matching according to claim 5, which is characterized in that first curve
Length is the described first length for matching microstrip line, and second length of a curve is the described second length for matching microstrip line.
7. encapsulation bonding line design method of impedance matching according to claim 6, which is characterized in that described in the basis
Parameter with impedance completes matching impedance in the simulation model：
The width of microstrip line, the length of the first matching microstrip line, the second matching microstrip line are matched according to described first
Width and it is described second matching microstrip line length drawn out on the substrate of the simulation model it is described first matching micro-strip
Line and the second matching microstrip line.
8. a kind of electronic equipment, which is characterized in that including：Processor；
Memory；And program, wherein described program is stored in the memory, and is configured to be held by processor
Row, described program include the method required for perform claim described in 1-7 any one.
9. a kind of computer readable storage medium, is stored thereon with computer program, it is characterised in that：The computer program quilt
Processor executes the method as described in claim 1-7 any one.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201711251091.6A CN108363825A (en) | 2017-12-01 | 2017-12-01 | A kind of encapsulation bonding line design method of impedance matching, electronic equipment and storage medium |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201711251091.6A CN108363825A (en) | 2017-12-01 | 2017-12-01 | A kind of encapsulation bonding line design method of impedance matching, electronic equipment and storage medium |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113609813A (en) * | 2021-10-09 | 2021-11-05 | 深圳飞骧科技股份有限公司 | Microstrip line modeling method, microstrip line modeling device and related equipment |
| CN114299223A (en) * | 2021-11-18 | 2022-04-08 | 芯瑞微(上海)电子科技有限公司 | Three-dimensional model identification and construction method for multilayer routing package |
| CN114826173A (en) * | 2022-06-30 | 2022-07-29 | 深圳市时代速信科技有限公司 | Radio frequency power device and electronic equipment |
| CN115065337A (en) * | 2022-06-14 | 2022-09-16 | 中国电子科技集团公司第二十六研究所 | Assembling method and assembling structure of micro-acoustic film filter |
| WO2023098122A1 (en) * | 2021-11-30 | 2023-06-08 | 上海望友信息科技有限公司 | Method for generating parameterized bonding data on basis of bonding wire model, and medium and device |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1523774A (en) * | 2003-02-17 | 2004-08-25 | 明基电通股份有限公司 | A design method for antenna impedance matching circuit |
| US20070268088A1 (en) * | 2006-05-18 | 2007-11-22 | Lsi Logic Corporation | Stub-tuned wirebond package |
| CN102034797A (en) * | 2009-09-10 | 2011-04-27 | Nxp股份有限公司 | Impedance optimized chip system |
| CN102075158A (en) * | 2010-12-29 | 2011-05-25 | 重庆邮电大学 | Method for designing ultra wideband impedance matching network |
| CN102393863A (en) * | 2011-06-15 | 2012-03-28 | 西安电子科技大学 | Impedance matching method for gold bonding wire |
| WO2012063128A2 (en) * | 2010-11-11 | 2012-05-18 | King Abdullah University Of Science And Technology | Fractional order element based impedance matching |
| CN103825571A (en) * | 2014-03-05 | 2014-05-28 | 锐迪科创微电子（北京）有限公司 | Radio frequency (RF) antenna switch circuit capable of realizing impedance matching |
| CN107068658A (en) * | 2017-03-21 | 2017-08-18 | 中国电子科技集团公司第三十八研究所 | The capacitance compensation and its design method of gold wire bonding in a kind of three-dimension packaging circuit |
-
2017
- 2017-12-01 CN CN201711251091.6A patent/CN108363825A/en active Pending
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1523774A (en) * | 2003-02-17 | 2004-08-25 | 明基电通股份有限公司 | A design method for antenna impedance matching circuit |
| US20070268088A1 (en) * | 2006-05-18 | 2007-11-22 | Lsi Logic Corporation | Stub-tuned wirebond package |
| CN102034797A (en) * | 2009-09-10 | 2011-04-27 | Nxp股份有限公司 | Impedance optimized chip system |
| US20130268909A1 (en) * | 2009-09-10 | 2013-10-10 | Nxp B.V. | Impedance optimized chip system |
| WO2012063128A2 (en) * | 2010-11-11 | 2012-05-18 | King Abdullah University Of Science And Technology | Fractional order element based impedance matching |
| CN102075158A (en) * | 2010-12-29 | 2011-05-25 | 重庆邮电大学 | Method for designing ultra wideband impedance matching network |
| CN102393863A (en) * | 2011-06-15 | 2012-03-28 | 西安电子科技大学 | Impedance matching method for gold bonding wire |
| CN103825571A (en) * | 2014-03-05 | 2014-05-28 | 锐迪科创微电子（北京）有限公司 | Radio frequency (RF) antenna switch circuit capable of realizing impedance matching |
| CN107068658A (en) * | 2017-03-21 | 2017-08-18 | 中国电子科技集团公司第三十八研究所 | The capacitance compensation and its design method of gold wire bonding in a kind of three-dimension packaging circuit |
Non-Patent Citations (2)
| Title |
|---|
| WEI HAN ETAL.: "Investigation of the packaging-induced RF attenuations and resonances in a broadband optoelectronic modulator module", 《JOURNAL OF LIGHTWAVE TECHNOLOGY》 * |
| 邓庆文 等: "Ka波段微带滤波器的仿真与测试 ", 《现代电子技术》 * |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113609813A (en) * | 2021-10-09 | 2021-11-05 | 深圳飞骧科技股份有限公司 | Microstrip line modeling method, microstrip line modeling device and related equipment |
| CN114299223A (en) * | 2021-11-18 | 2022-04-08 | 芯瑞微(上海)电子科技有限公司 | Three-dimensional model identification and construction method for multilayer routing package |
| CN114299223B (en) * | 2021-11-18 | 2024-01-23 | 芯瑞微(上海)电子科技有限公司 | Three-dimensional model identification and construction method for multilayer wire bonding package |
| WO2023098122A1 (en) * | 2021-11-30 | 2023-06-08 | 上海望友信息科技有限公司 | Method for generating parameterized bonding data on basis of bonding wire model, and medium and device |
| CN115065337A (en) * | 2022-06-14 | 2022-09-16 | 中国电子科技集团公司第二十六研究所 | Assembling method and assembling structure of micro-acoustic film filter |
| CN115065337B (en) * | 2022-06-14 | 2023-09-05 | 中国电子科技集团公司第二十六研究所 | Method and structure for assembling micro-acoustic thin film filter |
| CN114826173A (en) * | 2022-06-30 | 2022-07-29 | 深圳市时代速信科技有限公司 | Radio frequency power device and electronic equipment |
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