CN104244610A - Design method for reducing CONNECTOR via influences - Google Patents
Design method for reducing CONNECTOR via influences Download PDFInfo
- Publication number
- CN104244610A CN104244610A CN201410438863.7A CN201410438863A CN104244610A CN 104244610 A CN104244610 A CN 104244610A CN 201410438863 A CN201410438863 A CN 201410438863A CN 104244610 A CN104244610 A CN 104244610A
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- Prior art keywords
- connector
- via hole
- reducing
- influences
- impact
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- 238000000034 method Methods 0.000 title claims abstract description 17
- 238000013461 design Methods 0.000 title abstract description 8
- 238000003780 insertion Methods 0.000 claims description 4
- 230000037431 insertion Effects 0.000 claims description 4
- 238000012857 repacking Methods 0.000 claims description 3
- 238000012360 testing method Methods 0.000 claims description 3
- 238000004080 punching Methods 0.000 abstract 2
- 230000005540 biological transmission Effects 0.000 abstract 1
- 238000004088 simulation Methods 0.000 abstract 1
- 238000010200 validation analysis Methods 0.000 abstract 1
- 238000012545 processing Methods 0.000 description 2
- 230000007423 decrease Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
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- Coupling Device And Connection With Printed Circuit (AREA)
Abstract
The invention provides a design method for reducing CONNECTOR via influences. The design method for reducing the CONNECTOR via influences comprises the steps of additionally punching a via in the position close to a connector, enabling high-speed signals to carry out wire arrangement on a PCB layer with a small sub in the via as much as possible and enabling a wire to be connected to a jack on the connector. One via is additionally arranged, influences of a branch of a VIA stub are effectively reduced, and signal quality of the connector is obviously improved through simulation and actual board punching validation. Compared with the prior art, the design method for reducing the CONNECTOR via influences can effectively reduce transmission losses of high-frequency signals on a link and improve signal quality. In addition, the product produced through the design method for reducing the CONNECTOR via influences has the advantages of being reasonable in design, simple in structure, easy to machine, convenient to use and the like, thereby having excellent use value.
Description
Technical field
The present invention is a kind of method for designing reducing the impact of CONNECTOR via hole specifically.
Background technology
When circuit principle design, high-speed line generally can be connected in series AC electric capacity, causes line short phenomenon, namely play the effect that stopping direct current leads to interchange to prevent from sending and accepting device because reference potential is unequal.Therefore, for reducing the quantity of high-speed line through VIA via hole, generally can put PCB aspect at electric capacity and carrying out cabling.
Found by emulation connector place VIA via hole insertion loss loss, TX Signal transmissions decay on Top layer is obviously large than the RX signal attenuation on Bottom layer cabling, meanwhile, TX link exists due to larger VIA STUB, its loss waveform has large resonance point occur.And it is less to survey TX receiving terminal signal eye diagram, and signal rising has larger being separated with trailing edge, and namely signal jitter shakes comparatively large, has had influence on the quality of signal.
summary of the invention
The object of the invention is to overcome the deficiencies in the prior art, a kind of method for designing reducing the impact of CONNECTOR via hole is provided.
Technical scheme of the present invention realizes in the following manner, adds and makes a call to a via hole, make high speed signal carry out cabling in the PCB aspect that VIA via hole sub is less as far as possible, and be connected on connector jack in its structure at close connector place; Increase a via hole, but effectively reduce the impact of VIA stub branch, by emulating and the actual checking that re-packs, its signal quality improves significantly.
After above-mentioned improvement, connector place VIA via hole insertion loss waveform does not occur that large resonance point and actual re-packing improve significantly at TX receiving terminal signal testing eye pattern.
Above-mentioned Connector connector place adds again makes a call to a VIA via hole, is connected by high speed signal through internal layer with connector jack.
Advantage of the present invention is:
Of the present invention a kind of reduce CONNECTOR via hole impact method for designing compared to the prior art, this mode can effectively reduce the loss of high-frequency signal on link, promotion signal quality, and the present invention also have reasonable in design, structure simple, be easy to processing, the feature such as easy to use, thus, there is good use value.
Accompanying drawing explanation
Fig. 1 is a kind of structural representation reducing the method for designing of CONNECTOR via hole impact.
Embodiment
Be described in detail below below in conjunction with the method for designing of accompanying drawing on a kind of CONNECTOR of reduction via hole impact of the present invention.
As shown in Figure 1, a kind of method for designing reducing the impact of CONNECTOR via hole of the present invention, in adding make a call to a via hole near connector place, make high speed signal carry out cabling in the PCB aspect that VIA via hole sub is less as far as possible, and be connected on connector jack; Increase a via hole, but effectively reduce the impact of VIA stub branch, by emulating and the actual checking that re-packs, its signal quality improves significantly.
For the progressive loss of signal reduced on TX link, connector connector vicinity is carried out by the wiring of Top layer at TX signal, we will strengthen a VIA via hole again, and by internal layer, short VIA STUB will be in connector jack and be connected, and its cabling as shown in Figure 1.
Though this mode on TX link more increase a VIA via hole, but it decreases the impact of connector place via hole VIA Stub largely, its improve after connector place VIA via hole insertion loss waveform do not occur that large resonance point and actual re-packing improve significantly at TX receiving terminal signal testing eye pattern.
From to the emulation before and after the correcting of TX link and measured waveform, add again at Connector connector place and make a call to a VIA via hole, through internal layer, high speed signal is connected with connector jack, effectively can improve the quality of signal.
Of the present invention a kind of reduce CONNECTOR via hole impact its processing and fabricating of method for designing very simple and convenient, can process shown in accompanying drawing to specifications.
Except the technical characteristic described in specification, be the known technology of those skilled in the art.
Claims (3)
1. reduce a method for designing for CONNECTOR via hole impact, it is characterized in that adding at close connector place making a call to a via hole, make high speed signal carry out cabling in the PCB aspect that VIA via hole sub is less as far as possible, and be connected on connector jack; Increase a via hole, but effectively reduce the impact of VIA stub branch, by emulating and the actual checking that re-packs, its signal quality improves significantly.
2. a kind of method for designing reducing the impact of CONNECTOR via hole according to claim 1, is characterized in that improving rear connector place VIA via hole insertion loss waveform and does not occur that large resonance point and actual re-packing improve significantly at TX receiving terminal signal testing eye pattern.
3. a kind of method for designing reducing the impact of CONNECTOR via hole according to claim 1 and 2, is characterized in that adding at Connector connector place making a call to a VIA via hole again, is connected by high speed signal through internal layer with connector jack.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410438863.7A CN104244610A (en) | 2014-09-01 | 2014-09-01 | Design method for reducing CONNECTOR via influences |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410438863.7A CN104244610A (en) | 2014-09-01 | 2014-09-01 | Design method for reducing CONNECTOR via influences |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN104244610A true CN104244610A (en) | 2014-12-24 |
Family
ID=52231689
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410438863.7A Pending CN104244610A (en) | 2014-09-01 | 2014-09-01 | Design method for reducing CONNECTOR via influences |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104244610A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106872791A (en) * | 2017-03-04 | 2017-06-20 | 郑州云海信息技术有限公司 | A kind of method and system of the FOOTPRINT losses for detecting connector |
| CN108829937A (en) * | 2018-05-24 | 2018-11-16 | 郑州云海信息技术有限公司 | A method of optimization PCB high speed signal via hole |
-
2014
- 2014-09-01 CN CN201410438863.7A patent/CN104244610A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106872791A (en) * | 2017-03-04 | 2017-06-20 | 郑州云海信息技术有限公司 | A kind of method and system of the FOOTPRINT losses for detecting connector |
| CN108829937A (en) * | 2018-05-24 | 2018-11-16 | 郑州云海信息技术有限公司 | A method of optimization PCB high speed signal via hole |
| CN108829937B (en) * | 2018-05-24 | 2022-02-18 | 郑州云海信息技术有限公司 | Method for optimizing PCB high-speed signal via hole |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| WD01 | Invention patent application deemed withdrawn after publication | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20141224 |