CN203705485U

CN203705485U - LVDS device testing adapter

Info

Publication number: CN203705485U
Application number: CN201420008927.5U
Authority: CN
Inventors: 石雪梅
Original assignee: CASIC Defense Technology Research and Test Center
Current assignee: CASIC Defense Technology Research and Test Center
Priority date: 2014-01-07
Filing date: 2014-01-07
Publication date: 2014-07-09
Anticipated expiration: 2024-01-07

Abstract

The utility model discloses an LVDS device testing adapter which comprises a PCB, a socket and two GIS connectors, wherein the LVDS device is plugged into the socket, and the two GIS connectors are connected with the LVDS device via wiring of the PCB. The PCB comprises an independent LVDS signal layer used for wiring of LVDS signal lines; the two GIS connectors are respectively connected with an input interface and an output capture interface of a testing system; and jacks, which correspond the difference output ends of the LVDS device, of the socket are correspondingly connected with jacks, which correspond differential-pair channels in the output capture interface of the testing system, of the GIS connectors via the LVDS signal lines. The LVDS device testing adapter provided by the utility model can effectively help test of the LVDS device.

Description

LVDS device detection adapter

Technical field

The utility model relates to electron device testing technical field, refers to especially a kind of LVDS device detection adapter.

Background technology

Due to the restriction of integrated circuit automatic testing system and test adapter technology, import Low Voltage Differential Signal LVDS(Low Voltage Differential Signal) test rate of device is lower, can only reach 70MHZ, can not test by the speed 400Mbps of device handbook regulation; Though reduction of speed test also can be tested most of DC parameter of device, but key parameter---power consumption that can not test component, because this parameter is to be operated in the exact value that just can record under certain 200MHZ frequency at device, and key parameter rise time and the fall time of reflection interface device performance also will record under the speed of 400Mbps, if these parameters can not accurately be tested, the quality of real performance that just can not detection means.

Utility model content

In view of this, the purpose of this utility model is to propose a kind of LVDS device detection adapter, effectively subtest LVDS device.

A kind of LVDS device detection adapter providing based on above-mentioned purpose the utility model, comprises pcb board, for the socket of the LVDS device of pegging graft and by connected two the GIS connectors of PCB layout; Described pcb board comprises independently LVDS signals layer, for the wiring of LVDS signal wire; Described two GIS connectors are caught interface with the input interface of test macro and output respectively and are connected; On described socket corresponding to the jack of the difference output end of LVDS device, by the corresponding jack of catching the differential pair passage in interface on described GIS connector corresponding to test macro output that connects of described LVDS signal wire.

In some embodiments, every described LVDS signal wire cabling is isometric, and equidistant between adjacent described LVDS signal wire.

In some embodiments, the wiring of described LVDS signal wire adopts circular arc coiling or serpentine.

In some embodiments, the single-ended signal line impedence of described LVDS signal wire is 50 Ω, and differential signal line impedence is 100 Ω.

As can be seen from above, the LVDS device detection adapter that the utility model provides, can meet the test rate of LVDS device, and the highest test rate can reach 400Mbps, has solved the problem that LVDS device can not be tested at full speed.

Accompanying drawing explanation

Wherein a kind of schematic diagram of LVDS device that the LVDS device detection adapter embodiment that Fig. 1 provides for the utility model tests;

The structural representation of the LVDS device detection adapter embodiment that Fig. 2 provides for the utility model.

Embodiment

For making the purpose of this utility model, technical scheme and advantage clearer, below in conjunction with specific embodiment, and with reference to accompanying drawing, the utility model is further described.

Several principal elements such as test macro, test adapter, tested LVDS device in the environment of LVDS device detection, are comprised.In whole test process, test macro is sent test vector, is added to the input end of tested LVDS device by test adapter, and the result that then receives LVDS device output end judges the correctness of test.This process is under high velocity environment, and the interface of test macro and test adapter, test adapter and measured device is due to the degree of agreement of contact point, or electrical specification difference each other can cause the problem of impedance matching, can directly affect the high speed test of device.Because the characteristic of test macro and measured device is fixed, in order to improve test rate, solve by the test adapter of design specialized.

With reference to accompanying drawing 1, wherein a kind of schematic diagram of LVDS device that the LVDS device detection adapter embodiment providing for the utility model tests.

As shown in Figure 1, described LVDS device comprises 4 groups of signal input output ends (first input end 1A, the first difference output plus terminal 1Y, the first difference output negative terminal 1Z, the second input end 2A, the second difference output plus terminal 2Y, the second difference output negative terminal 2Z, the 3rd input end 3A, the 3rd difference output plus terminal 3Y, the 3rd difference output negative terminal 3Z, four-input terminal 4A, the 4th difference output plus terminal 4Y, the 4th difference output negative terminal 4Z).

With reference to accompanying drawing 2, the structural representation of the LVDS device detection adapter embodiment providing for the utility model.

An embodiment of the present utility model, based on SOC test macro V93000, has designed SN65LVDS31 high speed test adapter.Described LVDS device detection adapter, comprises pcb board, for the socket of the LVDS device of pegging graft and by connected two the GIS connectors of PCB layout; Described pcb board adopts 4 laminate designs, and lamination order is: LVDS signals layer, stratum, bus plane, other signals layer; Independently described LVDS signals layer, for the wiring of LVDS signal wire; Described two GIS connectors are caught interface with the input interface of test macro and output respectively and are connected.

V93000 test macro provides effective 50 Ω terminal impedance matching ways to suppress the reflection of transmission line, and digital channel has single-ended comparison and two kinds of modes of differential comparison; Therefore, on described socket corresponding to the difference output end of LVDS device (the first difference output plus terminal 1Y, the first difference output negative terminal 1Z, the second difference output plus terminal 2Y, the second difference output negative terminal 2Z, the 3rd difference output plus terminal 3Y, the 3rd difference output negative terminal 3Z, the 4th difference output plus terminal 4Y, the 4th difference output negative terminal 4Z) jack, be connected respectively the jack of catching the differential pair passage in interface on described GIS connector corresponding to test macro output by described LVDS signal wire; The input end (first input end 1A, the second input end 2A, the 3rd input end 3A, the 3rd difference output plus terminal 3Y, four-input terminal 4A) of LVDS device is connected with Any Digit passage.

Every described LVDS signal wire cabling is isometric, and equidistant between adjacent described LVDS signal wire.The wiring of described LVDS signal wire adopts circular arc coiling or serpentine.The single-ended signal line impedence of described LVDS signal wire is 50 Ω, and differential signal line impedence is 100 Ω.

Adjust through the repeatedly live width to signal wire and distance between centers of tracks, the resistance value after practical wiring, by calculating as shown in table 1 " calculated value " hurdle, meets designing requirement substantially.

Table 1 impedance computation details table

Type	Desired value (ohm)	Live width/spacing (mil)	Calculated value (ohm)
				Single-ended	50	6.6	52.11
Difference	100	5/6.8	99.58

Can find out from above-described embodiment, the utility model is based on SOC test macro V93000, and the SN65LVDS31 high speed test adapter of design, can make the highest test rate of SN65LVDS31 reach 400Mbps; Solve import Low Voltage Differential Signal LVDS(Low Voltage Differential Signal) problem that can not test at full speed of device SN65LVDS31, can test by the speed 400Mbps of device handbook regulation, can reflect truly electrical quantity, time parameter performance quality during tested.Described LVDS device detection adapter has been broken through the problem that SN65LVDS31 can not test at full speed on test macro V93000, can on test macro, realize test at full speed, and accurately test out the numerical value of every electrical quantity, time parameter, reflect more realistically the quality of measured device.

Those of ordinary skill in the field are to be understood that: the foregoing is only specific embodiment of the utility model; be not limited to the utility model; all within spirit of the present utility model and principle; any modification of making, be equal to replacement, improvement etc., within all should being included in protection domain of the present utility model.

Claims

1. a LVDS device detection adapter, is characterized in that, comprises pcb board, for the socket of the LVDS device of pegging graft and by connected two the GIS connectors of PCB layout; Described pcb board comprises independently LVDS signals layer, for the wiring of LVDS signal wire; Described two GIS connectors are caught interface with the input interface of test macro and output respectively and are connected; On described socket corresponding to the jack of the difference output end of LVDS device, by the corresponding jack of catching the differential pair passage in interface on described GIS connector corresponding to test macro output that connects of described LVDS signal wire.

2. test adapter according to claim 1, is characterized in that, every described LVDS signal wire cabling is isometric, and equidistant between adjacent described LVDS signal wire.

3. test adapter according to claim 2, is characterized in that, the wiring of described LVDS signal wire adopts circular arc coiling or serpentine.

4. according to the test adapter described in claim 1-3 any one, it is characterized in that, the single-ended signal line impedence of described LVDS signal wire is 50 Ω, and differential signal line impedence is 100 Ω.