CN209218453U - A kind of test board of ATE - Google Patents
A kind of test board of ATE Download PDFInfo
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- CN209218453U CN209218453U CN201821476359.6U CN201821476359U CN209218453U CN 209218453 U CN209218453 U CN 209218453U CN 201821476359 U CN201821476359 U CN 201821476359U CN 209218453 U CN209218453 U CN 209218453U
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Abstract
The utility model discloses the test boards of ATE a kind of, comprising: a kind of test board of ATE, comprising: the top layer set gradually from top to bottom, middle layer and bottom；Further include recess portion, is extended from the top layer to the middle layer；Flexible circuit board, the flexible circuit board setting is within the recess；It include multilayer signal layer in the middle layer；Different signals layers is electrically connected by the flexible circuit board.Therefore, the bottom in test board with the application opens up a recess portion, and flexible circuit board is placed in recess portion, realize electrical connection, the improvement of this circuit structure shortens via length, realizes the high-precision control of signal link impedance, Insertion Loss return loss is optimized, guarantees the integrality of test macro high speed signal.
Description
Technical field
The utility model relates to chip testing field, in particular to a kind of test board of ATE.
Background technique
During chip production, need to guarantee that the various functions of chip meet design requirement by means of testing.And core
Built-in testing can be divided into two class testings again, and the first kind is the test before die package, and the second class is the test behind die package.This its
In, the first class testing needs to be tested using probe card (probe card), and the second class is needed using support plate
(loadboard) it is tested.
Fig. 1 is the Vertrical probe clasp test structure of current comparative maturity, if Fig. 2 is the structure of mature support plate；Chip testing
In, two ways would generally be used for high speed signal test, the first is chip internal loopback, and second is signal and board
Interconnection.For the first test mode, since most of high speed signals are AC couplings, needed during signal loopback by
Capacitor.Simultaneously as chip side forbids putting device, therefore the coupled capacitor is to be placed in tester side.Due to surveying
The requirement of commissioning stage, for the plate thickness of PCB generally in 150mil or more, the plate thickness of some designs even can achieve 300mil or more.
Shown in fig. 3, TX/RX is differential signal: signal issues (TX) from chip (DUT), first passes around on PCB
A pair of of via hole switches to internal layer, then switches to Bot layers (tester side) by via hole after one section of cabling；Then it passes through
It crosses capacitor and reaches RX signal wire part, switch to internal layer using via hole, then switch to DUT through via hole by one section of cabling
side.Since via hole is very long, the impedance of via hole is difficult to control here, when signal rate is up to 30Gbps or more, via hole pair
Signal via influences very big.
Based on the technical problem present on, this application provides the technical solutions for solving the above technical problem.
Summary of the invention
The purpose of this utility model is the test board of ATE a kind of, further logical by increasing the setting of flexible circuit board
Setting groove is crossed, the connection that arbitrary signal can be achieved in groove is arranged in flexible circuit board, and it is hardened to substantially increase such test
The test bandwidth of structure, while also reliable pillar is provided for the higher rate measurement of Future Development.
The technical scheme that the utility model is provided is as follows:
A kind of test board of ATE, comprising: the top layer set gradually from top to bottom, middle layer and bottom；
Further include recess portion, is extended from the top layer to the middle layer；Flexible circuit board, the flexible circuit board
Setting is within the recess；It include multilayer signal layer in the middle layer；Different signals layers passes through the flexible circuit board electricity
Gas connection.
Specifically, carrying out grooving processing in PCB test board, the signal interconnection between random layer is realized by flexible board；
Flexible circuit board may be implemented directly to carry out two signal port TX and RX interconnections on same circuit board, save signal in this way
Track lengths；The control of impedance is realized, the further rate for improving signal, in addition flexible circuit board is arranged in groove
The connection that arbitrary signal can be achieved can be born hundreds of when pressing to test board with free bend, winding, folding
Ten thousand dynamic bendings not will receive the influence of the structure of shape without damaging conducting wire.
It is further preferred that including: that multiple electronic components are arranged on the flexible circuit board.
It is further preferred that include: be arranged on the flexible circuit board it is multiple corresponding with the pin of electronic component
Connector；Multiple connectors form connectivity port, and are arranged on the flexible circuit board.
It is further preferred that the middle layer includes that the first signal setting layer and second signal set layer；In the first signal
Set the first cabling port of the corresponding setting of layer；The second cabling port of the corresponding setting of layer is set in second signal；First cabling
Port neutralizes in the second cabling port and multiple connectors corresponding with signal is respectively set.
It is further preferred that the connector of the first cabling port is by the connectivity port that is arranged on flexible circuit board, with the
The connector of two cabling ports is electrically connected.
It is further preferred that include: top layer, middle layer, the flexible circuit board in bottom, and the setting recess portion is to press
The mode of conjunction forms the test board of the ATE.
Specifically, in this application, moving towards different according to signal, relevant signal will be generated；In the survey of existing ATE
After slotting on test plate (panel), according to the design that calculating optimizes, in the different layers being arranged due to the cabling of signal, one
The transmitting terminal of component from the cabling of receiving end be it is different, therefore, while not changing routing layer, in the fluting of respective layer
Out, outconnector is established between signal and is communicated for being connected with flexible circuit board.
The test board of ATE provided by the utility model a kind of, has the beneficial effect that:
The utility model is improved for circuit structure herein, shortens via length, realizes signal link impedance
High-precision control optimizes Insertion Loss return loss, guarantees the integrality of test macro high speed signal, substantially increases the survey of such structure
Test strip is wide.Also reliable pillar is provided for the higher rate measurement of Future Development.
The via hole amount of the number of vias of the application compared with the existing technology is reduced, and influence of the via hole for loss also can be obvious
It reduces, signal quality improves obviously, has very important significance for the test of two-forty signal.Signal quality can be significantly
It is promoted, can achieve 20% or more.
The application carries out grooving processing in PCB test board, realizes the signal interconnection between random layer by flexible board；It is soft
Property circuit board may be implemented directly to carry out two signal port TX and RX interconnections on same circuit board, saved signal in this way
Track lengths；The control of impedance is realized, the further rate for improving signal, in addition flexible circuit board setting can in groove
Realize that the connection of arbitrary signal can be born millions of when pressing to test board with free bend, winding, folding
Secondary dynamic bending not will receive the influence of the structure of shape without damaging conducting wire.
Detailed description of the invention
Below by clearly understandable mode, preferred embodiment is described with reference to the drawings, to a kind of the upper of the test board of ATE
Characteristic, technical characteristic, advantage and its implementation is stated to be further described.
Fig. 1 is the structural schematic diagram for the probe card that the prior art is used to test wafer；
Fig. 2 is the structural schematic diagram for the support plate that the prior art is used to test wafer；
Fig. 3 is the via structure schematic diagram that the prior art goes differential signal on test board；
Fig. 4 is the structural schematic diagram of the test board of the utility model ATE；
Fig. 5 is the utility model source impedance curve graph.
Drawing reference numeral explanation:
1. printed circuit board, 2. substrates, 3. connectors, 4. probes, 5. wafers, 6. sockets, 7. chips, 8. recess portions, 9. survey
Commissioning stage side, 10. determinand sides, 11. prior art source impedance curves, the source impedance curve of 12. the application, 13.
Connector, 14. flexible circuit boards, 15. capacitors, 100. top layers, 200. middle layers, 300. bottoms.
Specific embodiment
In order to illustrate the embodiment of the utility model or the technical proposal in the existing technology more clearly, attached drawing will be compareed below
Illustrate specific embodiment of the present utility model.It should be evident that the accompanying drawings in the following description is only the one of the utility model
A little embodiments for those of ordinary skill in the art without creative efforts, can also be according to these
Attached drawing obtains other attached drawings, and obtains other embodiments.
To make simplified form, part relevant to the utility model is only schematically shown in each figure, they are simultaneously
Its practical structures as product is not represented.
This application provides the test boards of ATE a kind of, as shown in Figure 4；It include: the top layer 100 set gradually from top to bottom,
Middle layer 200 and bottom 300；Further include recess portion 8, is extended from top layer 100 to middle layer 200；Flexible circuit board
14, flexible circuit board 14 is arranged in recess portion 8；It include multilayer signal layer in middle layer 200；Different signals layers pass through flexible electrical
Road plate 14 is electrically connected.
Specifically, in this application due to as shown in Figure 3 in the prior art；ATE(Automatic Test Equipment
Automatic test equipment)；Signal issues (TX) from chip (DUT), and a pair of of via hole is first passed around on PCB and switches to internal layer, then
Bot layers (tester side) are switched to by via hole after one section of cabling；Then RX signal wire part is reached by capacitor,
Internal layer is switched to using via hole, then switches to DUT side through via hole by one section of cabling.Since via hole is very long, mistake here
The impedance in hole is difficult to control, and when signal rate is up to 30Gbps or more, via hole influences signal via very big.With reference to figure
Shown in 4, the application carries out grooving processing in existing pcb board, realizes the signal interconnection between random layer by flexible board；It is soft
Property circuit board 14 may be implemented directly to carry out two signal port TX and RX interconnections on same circuit board, saved signal in this way
Track lengths；The control of impedance is realized, the further rate for improving signal, in addition flexible circuit board 14 is arranged in groove
The connection of interior achievable arbitrary signal can bear number when pressing to test board with free bend, winding, folding
Million dynamic bendings not will receive the influence of the structure of shape without damaging conducting wire.
Preferably, comprising: multiple electronic components are set on flexible circuit board 14.
It is provided with different electronic components on flexible circuit board 14, is configured according to test board demand.
Preferably, comprising: multiple connectors 13 corresponding with the pin of electronic component are set on flexible circuit board 14；
Multiple connectors 13 form connectivity port, and are arranged on flexible circuit board 14.
Preferably, middle layer 200 includes that the first signal setting layer and second signal set layer；It is right in the first signal setting layer
The first cabling of the setting port answered；The second cabling port of the corresponding setting of layer is set in second signal；First cabling port neutralizes
Multiple connectors 13 corresponding with signal are respectively set in second cabling port.
Preferably, the connector 13 of the first cabling port passes through the connectivity port being arranged on flexible circuit board 14, with second
The connector 13 of cabling port is electrically connected.
Preferably, comprising: top layer 100, middle layer 200, bottom 300, and the flexible circuit board being arranged in the recess portion 8
14 form the test board of the ATE in a manner of pressing.
Specifically, in this application, moving towards different according to signal, relevant signal will be generated；In the survey of existing ATE
After slotting on test plate (panel), according to the design that calculating optimizes, in the different layers being arranged due to the cabling of signal, one
The transmitting terminal of component from the cabling of receiving end be it is different, therefore, while not changing routing layer, in the fluting of respective layer
Out, outconnector is established between signal and is communicated for being connected with flexible circuit board 14.It is carried out by taking capacitor as an example in the application
Explanation；Join shown in Fig. 4；Specific implementation is will to be located at the devices such as bot layers of capacitor to design on flexible board, is carried out to PCB
Grooving presses PCB after then corresponding to signal combination on flexible board, so that signal completes interconnection.After DUT chip issues signal,
It needs after AC capacitive coupling, returns to DUT chip, i.e. DUT chip internal loopback proofing chip high speed performance.But Normal practice
In, capacitor needs to be placed in bot layers, therefore can have 4 pairs of via holes in a bars.Structure shown in the following figure, on a pair of of signal only
There are 2 pairs of via holes, and two pairs of via holes at capacitor both ends are removed by using the design method.
According to the application to setting is improved in a kind of structure of the test board of ATE in the prior art, referring to Fig. 5 institute
Show, the loss comparison diagram of the new design method of the application, curve 12 is the damage curve of new design method in Fig. 5, and curve 11 is
The damage curve of the prior art, it can be seen that new design method loss improves about 0.5db, and loss improves about 10%.For difference
Project, improvement has difference, and the length of this and via hole has very direct relationship.
The via hole amount of the number of vias of the application compared with the existing technology is reduced, and influence of the via hole for loss also can be obvious
It reduces, signal quality improves obviously, has very important significance for the test of two-forty signal.Signal quality can be significantly
It is promoted, can achieve 20% or more.
It should be noted that above-described embodiment can be freely combined as needed.The above is only the utility model
Preferred embodiment, it is noted that for those skilled in the art, do not departing from the utility model principle
Under the premise of, several improvements and modifications can also be made, these improvements and modifications also should be regarded as the protection scope of the utility model.
Claims (6)
1. a kind of test board of ATE characterized by comprising
The top layer set gradually from top to bottom, middle layer and bottom；
Further include recess portion, is extended from the top layer to the middle layer；
Flexible circuit board, the flexible circuit board setting is within the recess；
It include multilayer signal layer in the middle layer；
Different signals layers is electrically connected by the flexible circuit board.
2. a kind of test board of ATE as described in claim 1 characterized by comprising
Multiple electronic components are set on the flexible circuit board.
3. a kind of test board of ATE as claimed in claim 2 characterized by comprising
Multiple connectors corresponding with the pin of electronic component are set on the flexible circuit board；Multiple connector compositions connect
Port is connect, and is arranged on the flexible circuit board.
4. a kind of test board of ATE as claimed in claim 3, which is characterized in that
The middle layer includes that the first signal setting layer and second signal set layer；
The first cabling port of the corresponding setting of layer is set in the first signal；
The second cabling port of the corresponding setting of layer is set in second signal；
First cabling port neutralizes in the second cabling port and multiple connectors corresponding with signal is respectively set.
5. a kind of test board of ATE as claimed in claim 4, which is characterized in that
The connector of first cabling port passes through the connectivity port being arranged on flexible circuit board, the connector with the second cabling port
It is electrically connected.
6. the test board of ATE as described in any one of claim 1-5 a kind of characterized by comprising
Top layer, middle layer, bottom, and the flexible circuit board being arranged in the recess portion form the ATE's in a manner of pressing
Test board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821476359.6U CN209218453U (en) | 2018-09-10 | 2018-09-10 | A kind of test board of ATE |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821476359.6U CN209218453U (en) | 2018-09-10 | 2018-09-10 | A kind of test board of ATE |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN209218453U true CN209218453U (en) | 2019-08-06 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201821476359.6U Active CN209218453U (en) | 2018-09-10 | 2018-09-10 | A kind of test board of ATE |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110568340A (en) * | 2019-08-22 | 2019-12-13 | 苏州浪潮智能科技有限公司 | Impedance test structure, device and method |
| CN113267659A (en) * | 2021-05-18 | 2021-08-17 | 上海泽丰半导体科技有限公司 | ATE test board and manufacturing method thereof |
| CN114264996A (en) * | 2021-11-30 | 2022-04-01 | 上海御渡半导体科技有限公司 | Method for detecting DC calibration effectiveness of ATE equipment |
| CN115128418A (en) * | 2022-06-17 | 2022-09-30 | 上海泽丰半导体科技有限公司 | Wafer-level high-speed signal testing device |
| CN115128389A (en) * | 2022-08-31 | 2022-09-30 | 皇虎测试科技(深圳)有限公司 | ATE test interface device and equipment |
-
2018
- 2018-09-10 CN CN201821476359.6U patent/CN209218453U/en active Active
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110568340A (en) * | 2019-08-22 | 2019-12-13 | 苏州浪潮智能科技有限公司 | Impedance test structure, device and method |
| CN113267659A (en) * | 2021-05-18 | 2021-08-17 | 上海泽丰半导体科技有限公司 | ATE test board and manufacturing method thereof |
| CN114264996A (en) * | 2021-11-30 | 2022-04-01 | 上海御渡半导体科技有限公司 | Method for detecting DC calibration effectiveness of ATE equipment |
| CN115128418A (en) * | 2022-06-17 | 2022-09-30 | 上海泽丰半导体科技有限公司 | Wafer-level high-speed signal testing device |
| CN115128418B (en) * | 2022-06-17 | 2023-10-24 | 上海泽丰半导体科技有限公司 | Wafer level high-speed signal testing device |
| CN115128389A (en) * | 2022-08-31 | 2022-09-30 | 皇虎测试科技(深圳)有限公司 | ATE test interface device and equipment |
| CN115128389B (en) * | 2022-08-31 | 2022-12-02 | 皇虎测试科技(深圳)有限公司 | ATE test interface device and equipment |
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