CN108346574B - 制作具有钴硅化物层的半导体元件的方法 - Google Patents

制作具有钴硅化物层的半导体元件的方法 Download PDF

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CN108346574B
CN108346574B CN201710060808.2A CN201710060808A CN108346574B CN 108346574 B CN108346574 B CN 108346574B CN 201710060808 A CN201710060808 A CN 201710060808A CN 108346574 B CN108346574 B CN 108346574B
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layer
cobalt
silicon structure
cobalt silicide
silicide
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CN108346574A (zh
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张凯钧
郑存闵
蔡志杰
李瑞珉
陈意维
张家隆
刘玮鑫
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Fujian Jinhua Integrated Circuit Co Ltd
United Microelectronics Corp
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United Microelectronics Corp
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Abstract

本发明公开一种制作具有钴硅化物层的半导体元件的方法，其步骤包含提供一硅结构，其上形成有层间介电层、在该层间介电层中形成接触孔以裸露出硅结构、在300℃～400℃的温度环境中在裸露的硅结构上沉积一钴层，其中该钴层的表面同时形成一钴保护层、进行一快速升温处理，将该硅结构上的钴层转化成钴硅化物层、以及移除未转化的钴层。

Description

制作具有钴硅化物层的半导体元件的方法
技术领域
本发明大体上涉及一种半导体元件的制作方法，特别是涉及一种制作具有钴硅化物层的半导体元件的方法。
背景技术
随着半导体元件的集成度越来越高，电路尺寸逐渐变小，布局中提供给连接个别元件用的接触结构的接触区域也变得越来越小，特别是在高密度的存储单元中，如动态随机处理存储元件(DRAM)，其接触结构所需到达的深度增加，所流通的电流也变小。在此情况下，接触电阻这项参数在元件的电性上变得更为重要。
为了加速元件的运作速度，同时考虑到布线微细化以及热阻等因素，现今业界一般会在金属线与源/漏极与栅极的连接处进行硅化制作工艺来形成硅化钴(cobaltsilicide)等金属硅化物来降低减少接触电阻。例如在DRAM结构中，含有金属成分的位线会经由多晶硅接触插塞来与存取晶体管的源/漏极连接，此时硅化钴会作为两者间的界面来达到良好的欧姆接触。
现有的做法中会使用氮化钛盖层形成在尚未反应的钴层上来防止钴氧化，然而该氮化钛盖层在高温的硅化反应后会变得不易移除，容易形成雪花状残留物的缺陷。为此，目前业界仍需改进现有的硅化制作工艺来克服该问题。
发明内容
为了解决上述现有问题，本发明提出了一种新颖的钴硅化物层形成方法，其在形成未反应的钴层的同时(in-situ)就同时在表面形成一钴保护层，如此后续就不需要再额外形成氮化钛盖层来避免钴氧化。
本发明的其中一目的在于提供一种新颖的钴硅化物层形成方法，其步骤包含提供一硅结构，其上形成有层间介电层、在该层间介电层中形成接触孔以裸露出硅结构、在300℃～400℃的温度环境中在裸露的硅结构上沉积一钴层，其中该钴层的表面同时形成一钴保护层、进行一快速升温处理以将该硅结构上的钴层转化成钴硅化物层、以及移除未转化的钴层。
本发明的这类目的与其他目的在阅者读过下文以多种附图与绘图来描述的较佳实施例细节说明后将变得更为显见。
附图说明
本说明书含有附图并于文中构成了本说明书的一部分，以使阅者对本发明实施例有进一步的了解。该些附图描绘了本发明一些实施例并连同本文描述一起说明了其原理。在该些附图中：
图1至图3为本发明制作具有钴硅化物层的半导体元件的各个步骤流程的截面示意图。
主要元件符号说明
10 基底
12 元件隔离层
14 沟槽
16 栅绝缘层
18 阻障层
20 金属层
22 盖层
24 层间介电层
26 接触开口
27 外延层
28 钴层
30 钴硅化物
32 钴硅化物层
具体实施方式
在下文的细节描述中，元件符号会标示在随附的附图中成为其中的一部分，并且以可实行该实施例的特例描述方式来表示。这类实施例会说明足够的细节以使该领域的一般技术人士得以具以实施。为了图例清楚之故，附图中可能有部分元件的厚度会加以夸大。阅者须了解到本发明中也可利用其他的实施例或是在不悖离所述实施例的前提下作出结构性、逻辑性、及电性上的改变。因此，下文的细节描述将不欲被视为是一种限定，反之，其中所包含的实施例将由随附的权利要求来加以界定。
图1至图3为根据本发明实施例制作具有钴硅化物层的半导体元件的各个步骤流程的截面示意图。下文中将参照该些附图来说明根据本发明实施例的钴硅化物层的形成方法。
请参照图1，其将通过一埋入式字符线晶体管结构来说明本发明形成钴硅化物层的方法。首先提供一基底10，如一硅基底。基底10上预先形成有多个沟槽14，以供后续埋入式字符线的设置，其中可设置有元件隔离层12，如浅沟槽隔离结构(shallow trenchisolation,STI)，来分隔界定出个别的元件或其区域。接着，在沟槽14的底面和侧面形成一栅绝缘层16。栅绝缘层16可经由对硅基底10进行热氧化的方式形成，形成在基底10表面的栅绝缘层16后续可以现有的蚀刻制作工艺去除。一阻障层18形成在栅绝缘层16的表面，其可通过化学气相沉积法(CVD)或是原子层沉积法(ALD)来形成。在本实施例中，阻障层18可使用下列材料来形成，包含氮化钛(TiN)、Ti/TiN、氮化钨(WN)、W/WN、氮化钽(Ta/TaN)、TaN、TaSiN、WSiN、或是上述材料的组合。
复参照图1，接着在沟槽14中形成一金属层20，其制作方式可包含在基底上形成一金属层并埋入沟槽14中，之后进行一化学机械研磨将超出沟槽14外的金属层部位移除来形成。在本实施例中，金属层20可使用下列材料来形成，包含钨(W)、铝(Al)、铜(Cu)、钼(Mo)、钛(Ti)、钽(Ta)、钌(Ru)、或是上述材料的组合。在本实施例中，阻障层18与金属层20共同构成一埋入式字符线，该埋入式字符线会延伸穿过基底的主动区域与元件隔离层。之后，可选择在栅电极层18和金属层20上形成一盖层22来保护埋入式字符线结构，其顶面与周围齐平而不突出基底面。盖层22可用绝缘材料形成，如氧化硅或是氮化硅。
在形成盖层22后，之后在整个基底10上形成一层间介电层24，如一氧化层，并在其中形成接触开口26。接触开口26设置在两字符线结构之间，其贯穿层间介电层24而裸露出下方硅基底10，其可能已预先形成有源/漏极区域。复参照图1，在裸露出硅基底10后，接着进行一外延制作工艺在裸露出的硅基底10上生长一外延层27，如一多晶硅层或一非晶硅层。接着，在外延层27上形成一共形的钴层28，其会覆盖住接触开口26的侧壁以及开口中裸露的硅基底10主动区域12。
须注意在本发明中，钴层28使用高温的物理气相沉积(PVD)制作工艺来形成，例如在制作工艺温度介于300℃～400℃的温度环境下使用溅镀制作工艺来形成，其有别于一般现有技术中是在常温环境下溅镀形成钴层。在此步骤中，使用高温制作工艺来形成钴层的好处在于，由于高温的缘故，在形成钴层28的时候会有部分的钴层28被同时(in-situ)与下层的硅反应而直接转化成钴硅化物(cobalt silicide,CoSi2)30，特别是钴层28的表面位置，其他部位则含有未转化的钴以及未完全转化的CoSi相硅化物。此时已经转化的钴硅化物30可作为一钴保护层来避免所形成的钴氧化，如此在本发明制作工艺中就不须像现有技术一般还需要在钴层表面上额外形成一层氮化钛层来避免钴层氧化。此步骤的好处在于形成钴层28的时候同时形成钴保护层，不需要转换制作工艺腔体，不需要再额外的氮化钛层形成步骤，为其进步性所在。
请参照图2，在形成钴层28后，接着在惰性气体的环境下进行一快速热处理(rapidthermal process,RTP)，例如在制作工艺温度介于700℃～850℃的温度环境。如此，开口中尚未反应的钴以及未完全反应的CoSi相硅化物会完全反应形成一完整的钴硅化物层32，进一步降低其阻值。未与硅接触、位于开口侧壁部位的钴层则不会产生反应。在一般现有步骤中，钴层会经过两道快速热处理步骤(RTP1,RTP2)才能完全反应为钴硅化物。相较之下，本发明由于一开始就使用高温来形成钴层并同时使部分钴层转化为钴硅化物，除了可提供防止氧化的效果外，其之后也仅需要一道快速热处理步骤即可将剩余未反应的钴层转化为钴硅化物，不须如现有技术般还要再多进行一次快速热处理步骤，是其优点所在。
请参照图3，在快速热处理形成钴硅化物后，接着进行一清洗步骤将未反应的钴层去除，如位于开口侧壁上的钴层。由于不需要像现有技术般形成额外的氮化钛保护层，此清洗步骤可包含使用未混有任何氧化剂(如过氧化氢)的浓硫酸溶液(浓度介于94％-98％之间)来将未反应的钴层去除，仅留下开口中硅基底表面上的钴硅化物层32，作为接触插塞与硅基底之间提供良好欧姆接触的中介结构。再者，由于本发明仅使用一道快速热处理步骤，故也仅需要进行一次的清洗步骤即可获得所欲的钴硅化物层，其有别于现有技术使用两道快速热处理步骤之后可能还需要进行个别的多道清洗步骤的繁复做法。
之后的制作工艺可如现有步骤般地在开口中形成接触插塞结构，如存储节点接触插塞，以及其上的电路线。因简明之故以及避免模糊了本发明的焦点，其附图与细节在文中将不再多与赘述。
总结而论，本发明方法由于采用同时形成钴硅化物保护层的高温制作工艺之故，其不需如现有技术般额外形成氮化钛保护层，进而避免了后续清洗制作工艺不易完全移除氮化钛保护层造成雪花状残留的缺点，同时也省去了多道制作工艺步骤，是为一兼具新颖性与创造性的方法。
以上所述仅为本发明的较佳实施例，凡依本发明权利要求所做的均等变化与修饰，皆应属本发明的涵盖范围。

Claims (9)

1.一种制作具有钴硅化物层的半导体元件的方法，其步骤包含：
提供一硅结构，该硅结构上形成有层间介电层；
在该层间介电层中形成接触孔以裸露出该硅结构；
在300℃～400℃的温度环境中在裸露的该硅结构上沉积一钴层，其中该钴层的表面同时形成一钴保护层；该钴层介于该钴保护层与该硅结构之间；
对进行一快速升温处理，将该硅结构上的该钴层转化成钴硅化物层；以及
移除未转化的该钴层，且在移除未转化的该钴层后不再进行额外的快速升温处理。
2.如权利要求1所述的制作具有钴硅化物层的半导体元件的方法，其中该钴保护层为钴硅化物。
3.如权利要求1所述的制作具有钴硅化物层的半导体元件的方法，其中该钴层共形地沉积在该接触孔以及裸露的该硅结构上。
4.如权利要求1所述的制作具有钴硅化物层的半导体元件的方法，其中移除未转化的该钴层的步骤包含以浓硫酸进行一清洗步骤将未转化的该钴层移除。
5.如权利要求4所述的制作具有钴硅化物层的半导体元件的方法，其中该浓硫酸的浓度介于94％-98％之间。
6.如权利要求1所述的制作具有钴硅化物层的半导体元件的方法，其中该快速升温处理的温度介于700℃～850℃之间。
7.如权利要求1所述的制作具有钴硅化物层的半导体元件的方法，还包含在沉积该钴层前进行一外延制作工艺在裸露出该硅结构上形成一外延层。
8.如权利要求1所述的制作具有钴硅化物层的半导体元件的方法，其中该钴层上不会额外形成氮化钛保护层。
9.如权利要求1所述的制作具有钴硅化物层的半导体元件的方法，还包含在该钴硅化物层上形成接触插塞。
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