CN108334148B - Improved voltage comparator - Google Patents
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- CN108334148B CN108334148B CN201711414689.2A CN201711414689A CN108334148B CN 108334148 B CN108334148 B CN 108334148B CN 201711414689 A CN201711414689 A CN 201711414689A CN 108334148 B CN108334148 B CN 108334148B
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- 230000003111 delayed effect Effects 0.000 claims description 5
- 238000010586 diagram Methods 0.000 description 10
- 230000000694 effects Effects 0.000 description 5
- 238000004806 packaging method and process Methods 0.000 description 3
- 238000012935 Averaging Methods 0.000 description 2
- 230000000630 rising effect Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 1
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/575—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices characterised by the feedback circuit
Abstract
The present invention provides a voltage comparator, comprising: a bandgap reference voltage power supply circuit that provides a bandgap reference voltage; and the first input end of the comparison unit receives the band-gap reference voltage, the second input end of the comparison unit is connected with the target voltage, and the output end of the comparison unit outputs a comparison result. The band-gap reference voltage source circuit comprises an operational amplifier, a third resistor, a first intermediate node, a second intermediate node, a sampling switch, a first capacitor, a filter, a reference voltage output end, a switch combination circuit, N bipolar transistors and a control circuit. In different time periods, the switch combination circuit enables the N bipolar transistors to be connected to the second middle node one by one in turn, other bipolar transistors are connected to the first middle node in parallel, mismatch among the bipolar transistors can be averagely eliminated through the alternation, and therefore higher output voltage precision can be achieved, and the voltage comparator can output more accurate comparison results.
Description
[ technical field ] A method for producing a semiconductor device
The invention relates to the technical field of electronic circuits, in particular to an improved voltage comparator.
[ background of the invention ]
Bandgap reference voltage sources are widely used in various analog circuits. In practical applications, a high-precision bandgap reference voltage source is favored. Fig. 1 is a circuit diagram of a bandgap reference voltage source in the prior art, which includes resistors R1, R2, R3, bipolar transistors PNP transistors Q1, Q2, and an operational amplifier OP. The emitter area of Q1 is generally designed to be larger than that of Q2, for example, the ratio is K:1, and in order to achieve a relatively good matching effect in practical design, Q1 is generally designed to have K PNP transistors in parallel with Q2, and in one example, K is 4. In general, the resistances of the resistors R1 and R2 are designed to be the same, and are M times the resistance of R3, VBG is Vbe + m.vt.lnk, where Vbe is the emitter-base voltage of Q2, M is the ratio of the resistance of R1 to the resistance of R3, VT is the thermal voltage, which is a positive temperature coefficient, and K is the ratio of the emitter areas of Q1 and Q2. Vbe is a negative temperature coefficient, and good temperature compensation can be realized by designing a proper M value, so that a VBG voltage value with an approximate zero temperature coefficient is realized.
Although Q1 is designed with K transistors in parallel with Q2, there is a mismatch between each transistor in Q1 and Q2, i.e., when produced in large quantities, there are differences between the chips that result in inaccurate VBG and that can vary due to package stress effects. Even if the VBG is accurately adjusted by the trimming technique at the wafer or chip stage, there is a deviation between chips due to the influence of package stress after packaging.
Therefore, the output result of the voltage comparator using such a bandgap reference voltage source is also inaccurate due to the deviation of the generated bandgap reference voltage VGB.
[ summary of the invention ]
The invention aims to provide a voltage comparator, which adopts an improved band-gap reference voltage source voltage, wherein the band-gap reference voltage source voltage can further improve the precision of the output reference voltage and reduce the influences of mismatch and packaging stress of a bipolar transistor, so that the voltage comparator can output a more accurate comparison result.
In order to solve the above problem, the present invention provides a voltage comparator including: a bandgap reference voltage power supply circuit that provides a bandgap reference voltage; and the first input end of the comparison unit receives the band-gap reference voltage, the second input end of the comparison unit is connected with the target voltage, and the output end of the comparison unit outputs a comparison result. Wherein the band-gap reference voltage source circuit comprises an operational amplifier, a third resistor, a first intermediate node, a second intermediate node, a sampling switch, a first capacitor, a filter, a reference voltage output end, a switch combination circuit, N bipolar transistors and a control circuit, wherein the first input end of the operational amplifier is connected with the second intermediate node, the second input end of the operational amplifier is connected with the first intermediate node through the third resistor, the output end of the operational amplifier is sequentially grounded through the sampling switch and the first capacitor, the control end of the sampling switch is connected with the control circuit, the input end of the filter is connected with a connection node between the sampling switch and the first capacitor, the output end of the filter is connected with the reference voltage output end, wherein the first connection end of each bipolar transistor in the N bipolar transistors is connected with the switch combination circuit, the second connection ends of the bipolar transistors are connected with the control end of the bipolar transistor and are grounded, the control circuit controls the switch combination circuit, so that the first connection end of each bipolar transistor can be selectively connected with the first intermediate node or the second intermediate node, and N is larger than or equal to 2.
Compared with the prior art, the band-gap reference voltage source circuit comprises a switch combination circuit, wherein N bipolar transistors are connected to a second middle node B one by one in turn by the switch combination circuit in different time periods, the rest (N-1) bipolar transistors are connected to a first middle node A in parallel, and mismatch among the bipolar transistors can be averagely eliminated through the rotation, so that higher output voltage precision can be realized, and the influence of the mismatch and packaging stress of the bipolar transistors is smaller. Therefore, the voltage comparator adopting the band-gap reference voltage source circuit can output more accurate comparison results.
[ description of the drawings ]
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise. Wherein:
FIG. 1 is a circuit diagram of a bandgap reference voltage source in the prior art;
FIG. 2 is a circuit schematic of a bandgap reference voltage source circuit in one embodiment of the present invention;
FIG. 3 is a waveform diagram of the clock signals of FIG. 2 in one embodiment;
FIG. 4 is a circuit schematic of a bandgap reference voltage source circuit in another embodiment of the present invention;
FIG. 5 is a waveform diagram of the clock signal of FIG. 4 in one embodiment;
fig. 6 is a circuit diagram of an improved voltage comparator in accordance with the present invention in one embodiment.
[ detailed description ] embodiments
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.
Reference herein to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic may be included in at least one implementation of the invention. The appearances of the phrase "in one embodiment" in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Unless otherwise specified, the terms connected, and connected as used herein mean electrically connected, directly or indirectly.
Fig. 2 is a circuit diagram of a bandgap reference voltage source circuit according to an embodiment of the invention. The bandgap reference voltage source circuit shown in fig. 2 includes a third resistor R3, an operational amplifier OP, a first intermediate node a, a second intermediate node B, a sampling switch S6, a first capacitor C1, a filter 210, a reference voltage output terminal VBG, a switch combination circuit 220, N bipolar transistors, and a control circuit 230.
Wherein the first input terminal of the operational amplifier OP is connected to the second intermediate node B, the second input terminal of the operational amplifier OP is connected to the first intermediate node a through the third resistor R3, the output terminal of the operational amplifier OP is sequentially connected to the ground through the sampling switch S6 and the first capacitor C1, and the control terminal of the sampling switch S6 is connected to the control circuit 230; the input terminal of the filter 210 is connected to the connection node between the sampling switch S6 and the first capacitor C1, the output terminal of the filter 210 is connected to a reference voltage output terminal VBG, and the filter 210 is configured to filter the voltage fluctuation on the first capacitor C1 to form an average voltage, and output the average voltage to the reference voltage output terminal VBG.
In the N bipolar transistors, a first connection end of each bipolar transistor is connected to the switch combination circuit 220, and a second connection end of each bipolar transistor is connected to its own control end and to ground; the control circuit 230 controls the switch combination circuit 220 such that the first connection terminal of each bipolar transistor is selectively connected to either the first intermediate node a or the second intermediate node B, where N is greater than or equal to 2. The control circuit 230 controls the switch combination circuit 220 such that N bipolar transistors are alternately connected to the second intermediate node B one by one and the remaining (N-1) bipolar transistors are connected in parallel to the first intermediate node a during different time periods. In each time period, after the first connection terminal of one bipolar transistor is connected to the second intermediate node B and the first connection terminals of the remaining (N-1) bipolar transistors are connected in parallel to the first intermediate node a, the control circuit 230 controls the sampling switch S6 to be turned on to sample the voltage at the output terminal of the operational amplifier OP onto the first capacitor C1, and after the sampling is finished, the control circuit 230 controls the sampling switch S6 to be turned off.
In the specific embodiment shown in fig. 2, the bandgap reference voltage source circuit further comprises a first resistor R1 and a second resistor R2. One end of the first resistor R1 is connected to the output end of the operational amplifier OP, and the other end thereof is connected to a connection node between the second input end of the operational amplifier OP and the third resistor R3; one end of the second resistor R2 is connected to the output end of the operational amplifier OP, and the other end thereof is connected to the first input end of the operational amplifier OP.
In the embodiment shown in fig. 2, N is equal to 5, fig. 2 altogether uses 5 identically designed bipolar transistors Q1-Q5, of which 4 constitute Q1 in the equivalent fig. 1 and the remaining 1 constitute Q2 in the equivalent fig. 1, i.e. the ratio of the emitter areas of the bipolar transistors connected to the first intermediate node a to the bipolar transistors connected to the second intermediate node B is 4: 1. However, by having one bipolar transistor of fig. 2 connected to the second intermediate node B and the other four bipolar transistors connected to the first intermediate node a at different time periods, respectively, the schematic of the equivalent operating circuit is similar to that of fig. 1, except that the bipolar transistors Q1-Q5 are replaced one by one with successive cycles to the second intermediate node B.
In the embodiment shown in fig. 2, the switch combination circuit 220 includes 5 switch groups (221-225), each switch group corresponds to one bipolar transistor, and the control circuit 230 controls each switch group so that the first connection terminal of the bipolar transistor corresponding to the switch group can be selectively connected to the first intermediate node a or the second intermediate node B. For example, the switch group 221 corresponds to the bipolar transistor Q1, and the first connection terminal of the bipolar transistor Q1 can be selectively connected to the first intermediate node a or the second intermediate node B by controlling the switch group 221; the switch group 222 corresponds to the bipolar transistor Q2, and the first connection terminal of the bipolar transistor Q2 can be selectively connected to the first intermediate node a or the second intermediate node B by controlling the switch group 222; the switch group 223 corresponds to the bipolar transistor Q3, and the first connection end of the bipolar transistor Q3 can be selectively connected with the first intermediate node a or the second intermediate node B by controlling the switch group 223; the switch group 224 corresponds to the bipolar transistor Q4, and the first connection terminal of the bipolar transistor Q4 can be selectively connected to the first intermediate node a or the second intermediate node B by controlling the switch group 224; the switch set 225 corresponds to the bipolar transistor Q5, and the first connection terminal of the bipolar transistor Q5 can be selectively connected to the first intermediate node a or the second intermediate node B by controlling the switch set 225.
In the specific embodiment shown in fig. 2, each switch group comprises a first switch and a second switch, wherein one end of the first switch is connected to the first connection terminal of the corresponding bipolar transistor, and the other end of the first switch is connected to the first intermediate node a; one end of the second switch is connected with the first connection end of the corresponding bipolar transistor, and the other end of the second switch is connected with the second intermediate node B. For example, the switch group 221 includes a first switch S1a and a second switch S1B, wherein one end of the first switch S1a is connected to the first connection terminal of the corresponding bipolar transistor Q1, and the other end thereof is connected to the first intermediate node a, and one end of the second switch S1B is connected to the first connection terminal of the corresponding bipolar transistor Q1, and the other end thereof is connected to the second intermediate node B; the switch group 222 includes a first switch S2a and a second switch S2B, wherein one end of the first switch S2a is connected to the first connection end of the corresponding bipolar transistor Q2, the other end thereof is connected to the first intermediate node a, one end of the second switch S2B is connected to the first connection end of the corresponding bipolar transistor Q2, and the other end thereof is connected to the second intermediate node B; the switch group 223 includes a first switch S3a and a second switch S3B, wherein one end of the first switch S3a is connected to the first connection end of the corresponding bipolar transistor Q3, and the other end thereof is connected to the first intermediate node a, and one end of the second switch S3B is connected to the first connection end of the corresponding bipolar transistor Q3, and the other end thereof is connected to the second intermediate node B; the switch set 224 includes a first switch S4a and a second switch S4B, wherein one end of the first switch S4a is connected to the first connection terminal of the corresponding bipolar transistor Q4, and the other end thereof is connected to the first intermediate node a, and one end of the second switch S4B is connected to the first connection terminal of the corresponding bipolar transistor Q4, and the other end thereof is connected to the second intermediate node B; the switch set 225 includes a first switch S5a and a second switch S5B, wherein the first switch S5a has one end connected to the first connection terminal of the corresponding bipolar transistor Q5 and the other end connected to the first intermediate node a, and the second switch S5B has one end connected to the first connection terminal of the corresponding bipolar transistor Q5 and the other end connected to the second intermediate node B.
In the specific embodiment shown in fig. 2, the control circuit 230 is an oscillator, the oscillator 230 generates clock signals CK1, CK1B, CK2, CK2B, CK3, CK3B, CK4, CK4 4, CK5 4, and CK4, the clock signals CK1 4 and CK4 are respectively connected to the control terminals of the first switch S1 4 and the second switch S1 4 in the switch group 221, the clock signals CK 24 and CK4 are respectively connected to the control terminals of the first switch S2 4 and the second switch S2 4 in the switch group 222, the clock signals CK3 4 and CK4 are respectively connected to the control terminals of the first switch S3 4 and the second switch S3 4 in the switch group CK 223, the clock signals CK4 4 and CK4 are respectively connected to the control terminals of the first switch S4 4 and the second switch S4S 72 in the switch group 224, and the clock signals CK5 are respectively connected to the control terminals of the first switch S3S 4 and the second switch S5 in the switch group.
In fig. 2, the clock signals CK1B and CK1 are inverted signals, that is, CK1B is at a low level when CK1 is at a high level, and CK1B is at a high level when CK1 is at a low level; CK2B and CK2 are mutually inverse signals, that is, CK2B is at low level when CK2 is at high level, and CK2B is at high level when CK2 is at low level; CK3B and CK3 are mutually inverse signals, that is, CK3B is at low level when CK3 is at high level, and CK3B is at high level when CK3 is at low level; CK4B and CK4 are mutually inverse signals, that is, CK4B is at low level when CK4 is at high level, and CK4B is at high level when CK4 is at low level; CK5B and CK5 are inverted signals, that is, CK5B is at low level when CK5 is at high level, and CK5B is at high level when CK5 is at low level. When the clock signals are all high level (or called as a first logic level), the connected switches are controlled to be conducted; when these clocks are low (or referred to as a second logic level), the associated switches are controlled to be off (non-conductive). The control circuit 230 outputs the clock signals CK1-CK5 to the switch sets 221-.
Referring to fig. 3, which is a waveform diagram of the clock signals in fig. 2 in one embodiment, it can be seen from fig. 3 that the high levels (or referred to as first logic levels) of the clock signals CK1-CK5 do not overlap and jump to high levels (or referred to as first logic levels) in sequence. In the embodiment shown in FIG. 3, the clock signals CK1-CK5 have the same high time (or referred to as the first logic level) and are sequentially phase-delayed by a predetermined time equal to the same high time as the clock signals CK1-CK 5.
This is achieved by the waveforms of fig. 3, one of the bipolar transistors Q1-Q5 being in turn connected to the second intermediate node B, while the other four bipolar transistors are connected in parallel to the first intermediate node a. In addition, the sampling clock signal CK6 appears high level (first logic level) in any high level (or first logic level) period of CK1-CK5, but its rising edge is delayed by Td time (as shown in fig. 3), i.e., the time when the sampling clock signal CK6 jumps from low level to high level (i.e., the start time of high level) is delayed by a predetermined time Td from the time when the sampling clock signal CK6 jumps from low level to high level (i.e., the start time of high level) in the high level period of CK1-CK5 where the sampling clock signal CK6 jumps from low level to high level. The delay time Td is to ensure that enough time is left for the circuit to stabilize the output Voltage (VS) of the operational amplifier OP when the bipolar transistors are rotated. After the VS voltage is stabilized, the voltage sampled to the capacitor C1 is sampled by the sampling switch S6, and due to the mismatch, the voltage sampled to the capacitor C1 fluctuates at different clock phases, and the fluctuations can be filtered out by the filter 210 composed of the fourth resistor R4 and the second capacitor C2, so as to form an average voltage. Through the effect of the rotation and the averaging, the mismatching between the bipolar transistors can be averaged, so that higher output voltage precision can be realized, and the influence of the mismatching of the bipolar transistors is reduced.
It should be noted that, in the embodiment shown in fig. 2, the first input terminal and the second input terminal of the operational amplifier OP are respectively a forward input terminal and an inverted output terminal of the operational amplifier OP; the N bipolar transistors are PNP type transistors, and the first connecting end, the second connecting end and the control end of each bipolar transistor are respectively an emitter, a collector and a base of the PNP type transistor.
The invention can be applied not only to the bandgap reference source structure shown in fig. 2, but also to any other bandgap reference source structure. Fig. 4 is a circuit diagram of a bandgap reference voltage source circuit according to another embodiment of the present invention. The bandgap reference voltage source circuit shown in fig. 4 includes a third resistor R3, an operational amplifier OP, a first intermediate node a, a second intermediate node B, a sampling switch S6, a first capacitor C1, a filter 310, a reference voltage output terminal VBG, a switch combination circuit 320, N bipolar transistors, and a control circuit 330.
Wherein the first input terminal of the operational amplifier OP is connected to the second intermediate node B, the second input terminal of the operational amplifier OP is connected to the first intermediate node a through the third resistor R3, the output terminal of the operational amplifier OP is sequentially connected to the ground through the sampling switch S6 and the first capacitor C1, and the control terminal of the sampling switch S6 is connected to the control circuit 330; the input terminal of the filter 310 is connected to the connection node between the sampling switch S6 and the first capacitor C1, the output terminal of the filter 310 is connected to a reference voltage output terminal VBG, and the filter 310 is configured to filter the voltage fluctuation on the first capacitor C1 to form an average voltage, and output the average voltage to the reference voltage output terminal VBG.
In the N bipolar transistors, a first connection end of each bipolar transistor is connected to the switch combination circuit 320, and a second connection end of each bipolar transistor is connected to its own control end and to ground; the control circuit 330 controls the switch combination circuit 320 such that the first connection terminal of each bipolar transistor is selectively connected to the first intermediate node a or the second intermediate node B, where N is greater than or equal to 2. The control circuit 330 controls the switch combination circuit 320 such that N bipolar transistors are alternately connected to the second intermediate node B one by one and the remaining (N-1) bipolar transistors are connected in parallel to the first intermediate node a during different time periods. In each time period, after the first connection terminal of one bipolar transistor is connected to the point B and the first connection terminals of the remaining (N-1) bipolar transistors are connected to the point a in parallel, the control circuit 330 controls the sampling switch S6 to be turned on to sample the voltage at the output terminal of the operational amplifier OP onto the first capacitor C1, and after the sampling is finished, the control circuit 330 controls the sampling switch S6 to be turned off.
In the specific embodiment shown in fig. 4, the bandgap reference voltage source circuit further includes a second resistor R2, a first MOS transistor MP1 and a second MOS transistor MP2, the first connection terminals of the first MOS transistor MP1 and the second MOS transistor MP2 are both connected to the power supply terminal VIN, the control terminal of the first MOS transistor MP1 is connected to the control terminal of the second MOS transistor MP2, and the second connection terminal of the first MOS transistor MP1 is connected to the connection node between the second connection terminal of the operational amplifier OP and the third resistor R3; the control end of the second MOS transistor MP2 is connected to the output end of the operational amplifier OP, and the second connection end of the second MOS transistor MP2 is connected to the first input end of the operational amplifier OP via the second resistor R2.
In the embodiment shown in fig. 4, N is equal to 3, fig. 4 altogether uses 3 identically designed bipolar transistors Q1-Q3, of which 2 constitute Q1 in the equivalent fig. 1 and the remaining 1 constitute Q2 in the equivalent fig. 1, i.e. the emitter area ratio of the bipolar transistor connected to the first intermediate node a to the bipolar transistor connected to the second intermediate node B is 2: 1. However, by having one bipolar transistor of fig. 4 connected to the second intermediate node B and the other two bipolar transistors connected to the first intermediate node a at different time periods, respectively, the schematic of the equivalent operating circuit is similar to that of fig. 1, except that the bipolar transistors Q1-Q3 are replaced one by one with successive cycles to the second intermediate node B.
In the embodiment shown in fig. 4, the emitter area ratio of the bipolar transistor connected to the first intermediate node a to the bipolar transistor connected to the second intermediate node B is 2:1, but in practice any other value may be used, and a larger ratio may achieve better results, because the shift effect is better, and the difference between the base-emitter voltages of the two bipolar transistors is larger, which may reduce the influence of the input mismatch of the operational amplifier, and therefore the accuracy is better.
In the embodiment shown in fig. 4, the switch combination circuit 320 includes 3 switch groups (321-323), each switch group corresponds to one bipolar transistor, and the control circuit 330 controls each switch group to selectively connect the first connection terminal of the bipolar transistor corresponding to the switch group to the first intermediate node a or the second intermediate node B. For example, the switch group 321 corresponds to the bipolar transistor Q1, and the first connection terminal of the bipolar transistor Q1 can be selectively connected to the first intermediate node a or the second intermediate node B by controlling the switch group 321; the switch group 322 corresponds to the bipolar transistor Q2, and the first connection end of the bipolar transistor Q2 can be selectively connected to the first intermediate node a or the second intermediate node B by controlling the switch group 322; the switch block 323 corresponds to the bipolar transistor Q3, and the first connection terminal of the bipolar transistor Q3 is selectively connected to the first intermediate node a or the second intermediate node B by controlling the switch block 323.
In the specific embodiment shown in fig. 4, each switch group comprises a first switch and a second switch, wherein one end of the first switch is connected to the first connection terminal of the corresponding bipolar transistor, and the other end of the first switch is connected to the first intermediate node a; one end of the second switch is connected with the first connection end of the corresponding bipolar transistor, and the other end of the second switch is connected with the second intermediate node B. For example, the switch group 321 includes a first switch S1a and a second switch S1B, wherein one end of the first switch S1a is connected to the first connection terminal of the corresponding bipolar transistor Q1, and the other end thereof is connected to the first intermediate node a, and one end of the second switch S1B is connected to the first connection terminal of the corresponding bipolar transistor Q1, and the other end thereof is connected to the second intermediate node B; the switch group 322 includes a first switch S2a and a second switch S2B, wherein one end of the first switch S2a is connected to the first connection end of the corresponding bipolar transistor Q2, and the other end thereof is connected to the first intermediate node a, and one end of the second switch S2B is connected to the first connection end of the corresponding bipolar transistor Q2, and the other end thereof is connected to the second intermediate node B; the switch group 323 includes a first switch S3a and a second switch S3B, wherein one end of the first switch S3a is connected to the first connection terminal of the corresponding bipolar transistor Q3, and the other end thereof is connected to the first intermediate node a, and one end of the second switch S3B is connected to the first connection terminal of the corresponding bipolar transistor Q3, and the other end thereof is connected to the second intermediate node B.
In the specific embodiment shown in fig. 4, the control circuit 330 is an oscillator, the oscillator 330 generates clock signals CK1, CK1B, CK2, CK2B, CK3, CK3B and CK6, the clock signals CK1B and CK1 are respectively connected to control terminals of the first switch S1a and the second switch S1b in the switch group 321, the clock signals CK2B and CK2 are respectively connected to control terminals of the first switch S2a and the second switch S2b in the switch group 322, and the clock signals CK3B and CK3 are respectively connected to control terminals of the first switch S3a and the second switch S3b in the switch group 323.
In fig. 4, the clock signals CK1B and CK1 are inverted signals, that is, CK1B is at a low level when CK1 is at a high level, and CK1B is at a high level when CK1 is at a low level; CK2B and CK2 are mutually inverse signals, that is, CK2B is at low level when CK2 is at high level, and CK2B is at high level when CK2 is at low level; CK3B and CK3 are mutually inverse signals, that is, CK3B is at low level when CK3 is at high level, and CK3B is at high level when CK3 is at low level. When the clock signals are all high level (or called as a first logic level), the connected switches are controlled to be conducted; when these clocks are low (or referred to as a second logic level), the associated switches are controlled to be off (non-conductive). The control circuit 330 can also output the clock signals CK1-CK3 to the switch groups 321-323, respectively, when the clock signals CK1-CK3 are at the first logic level, the first switch and the second switch of the corresponding switch group 321-323 are turned off, and when the clock signals CK1-CK3 are at the second logic level, the first switch and the second switch of the corresponding switch group are turned on, respectively.
Referring to fig. 5, which is a waveform diagram of the clock signals in fig. 4 in one embodiment, it can be seen from fig. 5 that the high levels (or referred to as the first logic levels) of the clock signals CK1-CK3 do not overlap and jump to the high level (or referred to as the first logic level) in sequence. In the embodiment shown in FIG. 5, the clock signals CK1-CK3 have the same high time (or referred to as the first logic level) and are sequentially phase-delayed by a predetermined time equal to the same high time as the clock signals CK1-CK 3.
This is achieved by the waveforms of fig. 5, one of the bipolar transistors Q1-Q3 being connected in turn to the second intermediate node B, while the other two bipolar transistors are connected in parallel to the first intermediate node a. In addition, the sampling clock signal CK6 appears high level (first logic level) in any high level (or first logic level) period of CK1-CK3, but its rising edge is delayed by Td time (as shown in fig. 5), i.e., the time when the sampling clock signal CK6 jumps from low level to high level (i.e., the start time of high level) is delayed by a predetermined time Td from the time when the sampling clock signal CK6 jumps from low level to high level (i.e., the start time of high level) in the high level period of CK1-CK3 where the sampling clock signal CK6 jumps from low level to high level. The delay time Td is to ensure that enough time is left for the circuit to stabilize the output Voltage (VS) of the operational amplifier OP when the bipolar transistors are rotated. After the VS voltage is stabilized, the voltage sampled to the capacitor C1 is sampled by the sampling switch S6, and due to the mismatch, the voltage sampled to the capacitor C1 fluctuates at different clock phases, and the fluctuations can be filtered out by the filter 210 composed of the fourth resistor R4 and the second capacitor C2, so as to form an average voltage. Through the effect of the rotation and the averaging, the mismatching between the bipolar transistors can be averaged, so that higher output voltage precision can be realized, and the influence of the mismatching of the bipolar transistors is reduced.
It should be noted that, in the embodiment shown in fig. 4, the first input terminal and the second output terminal of the operational amplifier OP are the inverting input terminal and the forward output terminal of the operational amplifier OP, respectively; the N bipolar transistors are PNP type transistors, and the first connecting end, the second connecting end and the control end of each bipolar transistor are respectively an emitter, a collector and a base of the PNP type transistor; the first MOS transistor MP1 and the second MOS transistor MP2 are both PMOS transistors, and the first connection end, the second connection end, and the control end of the first MOS transistor MP1 and the second MOS transistor MP2 are respectively a source electrode, a drain electrode, and a gate electrode of the PMOS transistor.
FIG. 6 is a circuit diagram of a voltage comparator in one embodiment of the invention. As shown in fig. 6, the voltage comparator 600 includes: a bandgap reference voltage source circuit 610 and a comparing unit Comparator. The bandgap reference voltage source circuit 610 provides a bandgap reference voltage, which may be the improved bandgap reference voltage source circuit described above. A first input end of the comparison unit receives the bandgap reference voltage VR, a second input end of the comparison unit is connected with the target voltage VIN, and an output end of the comparison unit outputs a comparison result. Therefore, the voltage comparator adopting the band-gap reference voltage source circuit can output a more accurate comparison result.
In the present invention, the terms "connected", connected, "connecting," and "connecting" mean electrically connected, and if not specifically stated, directly or indirectly indicate electrically connected.
It should be noted that those skilled in the art can make modifications to the embodiments of the present invention without departing from the scope of the appended claims. Accordingly, the scope of the appended claims is not to be limited to the specific embodiments described above.
Claims (5)
1. A voltage comparator, comprising:
a bandgap reference voltage power supply circuit that provides a bandgap reference voltage;
a comparison unit, a first input end of which receives the band-gap reference voltage, a second input end of which is connected with a target voltage, and an output end of which outputs a comparison result;
wherein the band-gap reference voltage source circuit comprises an operational amplifier, a third resistor, a first intermediate node, a second intermediate node, a sampling switch, a first capacitor, a filter, a reference voltage output end, a switch combination circuit, N bipolar transistors and a control circuit, the first input end of the operational amplifier is connected with the second intermediate node, the second input end of the operational amplifier is connected with the first intermediate node through the third resistor, the output end of the operational amplifier is sequentially grounded through the sampling switch and the first capacitor, the control end of the sampling switch is connected with the control circuit, the input end of the filter is connected with the connection node between the sampling switch and the first capacitor, the output end of the filter is connected with the reference voltage output end,
wherein the first connection terminal of each bipolar transistor of the N bipolar transistors is connected with the switch combination circuit, the second connection terminal of each bipolar transistor is connected with the control terminal of each bipolar transistor and is grounded, the control circuit controls the switch combination circuit, so that the first connection terminal of each bipolar transistor can be selectively connected with the first intermediate node or the second intermediate node, N is more than or equal to 2,
the control circuit controls the switch combination circuit, in different time periods, N bipolar transistors are connected to a second intermediate node one by one in turn, first connecting ends of the other (N-1) bipolar transistors are connected to a first intermediate node in parallel, in each time period, if the first connecting end of one bipolar transistor is connected to the second intermediate node, the first connecting ends of the other (N-1) bipolar transistors are connected to the first intermediate node in parallel, the control circuit controls the sampling switch to be switched on so as to sample the voltage of the output end of the operational amplifier onto the first capacitor, and after the sampling is finished, the control circuit controls the sampling switch to be switched off,
the switch combination circuit comprises N switch groups, each switch group corresponds to one bipolar transistor, the control circuit controls each switch group to enable the first connection end of the bipolar transistor corresponding to the switch group to be selectively connected with the first intermediate node or the second intermediate node,
each switch group comprises a first switch and a second switch, wherein one end of each first switch is connected with the first connecting end of the corresponding bipolar transistor, and the other end of each first switch is connected with the first intermediate node; one end of the second switch is connected with the first connecting end of the corresponding bipolar transistor, the other end of the second switch is connected with the second intermediate node,
the control circuit is an oscillator, the oscillator outputs a first clock signal to an Nth clock signal to the N switch groups respectively, when the clock signal is at a first logic level, the first switch in the corresponding switch group is turned off, the second switch in the corresponding switch group is turned on, when the clock signal is at a second logic level, the first switch in the corresponding switch group is turned on, the second switch in the corresponding switch group is turned off,
the oscillator outputs a sampling clock signal to a control terminal of the sampling switch, the sampling switch is turned on when the sampling clock signal is at a first logic level, and the sampling switch is turned off when the sampling clock signal is at a second logic level,
the first logic levels of the first to Nth clock signals are not overlapped and jump to the first logic level in turn,
the first logic level of the sampling clock signal appears in each first logic level time period of the first to the Nth clock signals, and the starting time of the first logic level of the sampling clock signal is delayed by a first preset time than the starting time of the first logic level time period of the first to the Nth clock signals,
the filter circuit comprises a second capacitor and a fourth resistor, one end of the fourth resistor is connected with a connection node between the first capacitor and the sampling switch, and the other end of the fourth resistor is connected with the reference voltage output end; the second capacitor is connected between the reference voltage output terminal and a ground terminal,
the N bipolar transistors are the same, the first clock signal to the Nth clock signal have the same first logic level time, the phases of the first clock signal to the Nth clock signal sequentially lag behind second preset time, and the second preset time is equal to the first logic level time of the first clock signal to the Nth clock signal.
2. The voltage comparator as claimed in claim 1, wherein the bandgap reference voltage source circuit further comprises a second resistor, a first MOS transistor and a second MOS transistor,
the first connection ends of the first MOS transistor and the second MOS transistor are connected with a power supply end, the control end of the first MOS transistor is connected with the control end of the second MOS transistor, and the second connection end of the first MOS transistor is connected with a connection node between the second input end of the operational amplifier and the third resistor; and the control end of the second MOS transistor is connected with the output end of the operational amplifier, and the second connecting end of the second MOS transistor is connected with the first input end of the operational amplifier through the second resistor.
3. The voltage comparator as claimed in claim 2,
the first input end and the second input end of the operational amplifier are respectively an inverting input end and a forward output end of the operational amplifier,
the N bipolar transistors are PNP type transistors, and the first connecting end, the second connecting end and the control end of each bipolar transistor are respectively an emitter, a collector and a base of the PNP type transistor;
the first MOS transistor, the second MOS transistor and the power transistor are all PMOS transistors, and the first connecting end, the second connecting end and the control end of the first MOS transistor, the second MOS transistor and the power transistor are respectively a source electrode, a drain electrode and a grid electrode of the PMOS transistor.
4. The voltage comparator as claimed in claim 1, further comprising a first resistor and a second resistor,
one end of the first resistor is connected with the output end of the operational amplifier, and the other end of the first resistor is connected with a connecting node between the second output end of the operational amplifier and the third resistor;
one end of the second resistor is connected with the output end of the operational amplifier, and the other end of the second resistor is connected with the first output end of the operational amplifier.
5. The voltage comparator as claimed in claim 4,
the first input end and the second output end of the operational amplifier are respectively a positive input end and a negative output end of the operational amplifier,
the N bipolar transistors are PNP type transistors, and the first connecting end, the second connecting end and the control end of each bipolar transistor are respectively an emitter, a collector and a base of the PNP type transistor.
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| CN111064453B (en) * | 2019-12-13 | 2023-07-04 | 南京中感微电子有限公司 | Voltage comparator |
| CN113376423B (en) * | 2021-04-25 | 2023-08-08 | 合肥中感微电子有限公司 | Voltage detection circuit |
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| CN104503532A (en) * | 2014-12-13 | 2015-04-08 | 无锡来燕微电子有限公司 | Reference voltage production circuit of charge pump |
| CN104901359A (en) * | 2015-05-13 | 2015-09-09 | 无锡中星微电子有限公司 | Charging and discharging control device with battery current detection circuit |
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| EP0490432A1 (en) * | 1990-12-11 | 1992-06-17 | Koninklijke Philips Electronics N.V. | Power-supply arrangement |
| US6930539B2 (en) * | 2002-05-29 | 2005-08-16 | Infineon Technologies Ag | Reference voltage circuit and method of generating a reference voltage |
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