KR100426548B1 - Phase shift circuit and fm detecting circuit - Google Patents

Abstract

The present invention is for performing a stable delay time with a simple circuit, and turns on and off the transistors 12a and 12b with the input signals reversed to each other. The capacitors 16a and 16b are discharged by turning on the transistors 12a and 12b, and the capacitors 16a and 16b are charged with constant current from the constant current sources 18a and 18b by turning off the transistors 12a and 12b. Is done. As a result, a voltage gradually rising in the L period of the input signal is obtained at the positive input terminals of the comparators 14a and 14b. By comparing this with a constant voltage of the reference power supplies 20a and 20b, a signal whose rise timing is shifted from the 90 ° input signal at the output of the comparators 14a and 14b is obtained. The outputs of the comparators 14a and 14b are shifted by 180 ° from each other, and by resetting the RS flip-flop 22 at their rise, a signal having a 90 ° phase delayed with respect to the input signal is obtained at the output.

Description

Fault circuit and FM detection circuit {PHASE SHIFT CIRCUIT AND FM DETECTING CIRCUIT}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an abnormal circuit for shifting a phase of a spherical input signal by a predetermined time and outputting the same, and an FM detection circuit using such an abnormal circuit.

Conventionally, quadrature detection circuits have been used as FM detection circuits. In this quadrature detection circuit, a delay signal is obtained by shifting the phase of an IF (intermediate frequency) signal for a predetermined time (almost 90 degrees relative to the center frequency), and FM detection is performed by multiplying the delay signal by the IF signal. Therefore, an abnormal circuit for creating a delay signal is required.

As the abnormal circuit, an abnormal circuit using a coil and a capacitor, a ceramic resonator, or the like is usually used.

However, in such a conventional abnormal circuit, a coil or a ceramic resonator becomes an external component, and there is a problem that integration is difficult and enlarged.

Moreover, although a delay line etc. can also be used, there existed a problem that a circuit became large and temperature dependence became high.

SUMMARY OF THE INVENTION An object of the present invention has been made in view of the above problems, and an object of the present invention is to provide an abnormal circuit capable of performing a stable delay time abnormality with a simple circuit and a detection circuit using the same.

According to an aspect of the present invention, there is provided an abnormal circuit for shifting a phase of a spherical input signal by a predetermined time and outputting the first input signal, the first switch being on and off by receiving a first input signal; A first capacitor charged by a constant current from a constant current source and discharged by a first switch; A first comparator comparing the charging voltage of the first capacitor with a reference voltage to obtain an output whose shift timing is shifted with the first input signal for a predetermined time; A second switch configured to receive on and off a second input signal 180 ° out of phase with the first input signal; A second capacitor charged by the constant current from the constant current source and discharged by the second switch; A second comparator for comparing the charging voltage of the second capacitor with a reference voltage; And a signal processing circuit for obtaining a signal shifted in phase with respect to the first and second input signals by a predetermined time based on the outputs of the first and second comparators.

In this manner, by charging the capacitor with a current from a constant current source, a voltage rising by a predetermined gradient can be obtained, and by setting the desired time (predetermined time) to delay the time when the voltage exceeds the reference voltage. A signal whose rising phase is delayed by a predetermined time is obtained. Similarly, with respect to the inverted input signal, a signal in which the rising phase is delayed by a predetermined time can be obtained. Thus, a signal delayed by a predetermined time phase can be obtained from the input signal at the rise of these two signals.

In this manner, according to the present invention, a signal obtained by shifting a predetermined time phase with a simple circuit requiring no coil can be obtained. In addition, a resonator, a delay line, or the like is also unnecessary.

Further, the signal processing circuit is preferably a flip-flop set by one comparator output and reset by the other comparator output.

Further, the signal processing circuit preferably includes a logic circuit that takes an exclusive OR or OR of the outputs of both comparators, and a divider circuit that divides the output of the logic circuit.

Moreover, it is preferable to perform FM detection from the output from the abnormal circuit mentioned above and an input signal.

In addition, the present invention is characterized in that it comprises an ideal phase consisting of a delay unit for delaying the input signal only a predetermined time, and a multiplier for multiplying the input signal and the output of the abnormal phase.

1 is a block diagram showing a configuration of an embodiment.

2 shows waveforms of respective parts of the same embodiment.

3 illustrates another embodiment.

4 is a diagram illustrating a configuration of a detection circuit.

5A is a diagram showing a relationship between an input frequency of a S curve characteristic and a phase difference.

5B is a diagram illustrating a relationship between an input frequency and a phase difference.

6 is a block diagram showing a configuration of another embodiment of the present invention.

7 shows means for obtaining a constant current source and a voltage source from the same current source.

<Explanation of symbols for the main parts of the drawings>

10: amplifier

12a, 12b: transistor,

14a, 14b: comparators

16a, 16b: condenser

18a, 18b: constant current source

20a, 20b: reference power

22: RS flip flop

24: buffer

26: exclusive OR

28: dividing circuit

EMBODIMENT OF THE INVENTION Hereinafter, the Example (henceforth Example) of this invention is described based on drawing.

1 is a block diagram showing a configuration of an abnormal circuit according to an embodiment. The first and second input signals, which are mutually out of phase (180 ° out of phase), are input to the amplifier 10. Such first and second input signals are, for example, IF (intermediate frequency) signals of a desired station of the FM radio, and are shaped as square waves. The amplifier 10 performs predetermined amplification on these two signals, and supplies them to the two transistors 12a and 12b, respectively. The signals supplied to the transistors 12a and 12b are also mutually inverted signals, which are square waves.

The transistor 12a receives a first input signal at the base, the emitter is connected to ground, and the collector is connected to the plus input terminal of the comparator 14a. The positive input terminal of the comparator 14a is connected to a capacitor 16a having the other end connected to ground and a current source 18a having the other end connected to the power supply.

The negative power supply terminal of the comparator 14a is connected to a reference power supply 20a having the other end connected to ground. The output of this comparator 14a is input to the reset terminal R of the RS flip-flop 22.

On the other hand, transistor 12b receives the second input signal at the base, the emitter is connected to ground, and the collector is connected to the positive input terminal of comparator 14b. The positive input terminal of the comparator 14b is connected to a capacitor 16b having the other end connected to ground and a current source 18b having the other end connected to the power supply. The negative power supply terminal of the comparator 14b is connected to a reference power supply 20b having the other end connected to ground.

The output of this comparator 14b is also input to the set terminal S of the RS flip-flop 22. The Q output terminal and the QB output terminal which is the inverted output of the RS flip-flop 22 are output through the buffer circuit 24, respectively.

The operation of such a circuit will be described with reference to the waveform diagrams of the respective parts in FIG. The first and second input signals are square waves of approximately constant frequency IF, as indicated by a in the figure. The input signal is a signal that is FM-modulated, and the frequency change is FM demodulated at a later stage.

In FIG. 1, as an example, the case where the reference voltage (threshold voltage) of the constant current source 18a, the capacitor 16a, and the reference power supply 20a is set so that the phase delay in the absence of the IF frequency shift becomes 90 ° is considered. do. Also, the phase delay of 90 ° is for the center frequency of the FM modulated signal.

Since the circuit from the transistor 12a to the output of the comparator 14a and the circuit from the transistor 12b to the output of the comparator 14b are all the same and the input signal is reversed, the output of the comparator 14b is the comparator 14a. ) Will only reverse the output signal. Therefore, a and b which are subscripts are abbreviate | omitted and demonstrated next.

Since the input signal shown as A in FIG. 2 is connected to the base of the transistor 12, the upper side of the capacitor 16, i.e., the positive input terminal of the comparator 14, is connected to ground during the period where the input signal is H. On the other hand, since the capacitor 16 flows a predetermined amount of current predetermined by the constant current source 18 toward the capacitor 16 during the period in which the input signal is L, the capacitor 16 is charged according to this amount of current, and FIG. 2. At the point indicated by B, the voltage at the positive input terminal of the comparator 14 rises linearly with a predetermined gradient. On the other hand, when the transistor 12 is turned on, the charge of the capacitor 16 is discharged at a time. Therefore, as shown by B in FIG. 2, the positive input terminal of the comparator 14 rises with a constant slope in the period in which the input signal is L, and the signal always becomes L during the period in H.

The comparator 14 compares the voltage of the reference power supply 20 with the gradually rising voltage of the positive input terminal. The output is set to H when the voltage at the positive input terminal exceeds the voltage of the reference power supply 20.

Then, by appropriately setting the capacitance of the capacitor 16, the current amount of the constant current source 18 and the voltage of the reference power supply 20 in advance, as shown in the figure, the input signal is exactly 1/2 of the period of L. When the period elapses, the input voltage of the positive input terminal of the comparator 14 exceeds the voltage of the reference power supply 20 and its output becomes H. After that, when the input signal becomes H, the output of the comparator 14 becomes L. Therefore, the output of the comparator 14 rises in the step shifted by 90 ° after the input signal becomes L, so that the input signal becomes L period. The signal shown by C in the drawing descending at the end of is obtained. That is, the output signal of the comparator 14 rises in the phase of 90 degrees from the rising and falling of the input signal, as shown by C in the figure, and becomes a signal which becomes H for a period of 90 degrees.

The output signals from the comparators 14a and 14b are exactly reversed, and signals C and C 'having 180 ° out of phase with each other are obtained. In addition, the signals A, A ', B, and B' are also reversed.

The outputs C and C 'of these comparators 14a and 14b are input to the reset terminal R and the set terminal S of the RS flip-flop 22. Therefore, the signal set at the rise of C 'and reset at the rise of C is obtained at the Q output of the RS flip-flop 22, and the QB output is inverted thereof.

The signals E and E ', which are outputs of the flip-flop 22, are signals obtained by delaying the first input signal and the second input signal by 90 degrees.

As described above, according to the circuit of the present embodiment, an unusual signal of 90 ° can be obtained without using a coil or the like.

3, another embodiment is shown. This circuit has an exclusive OR circuit 26 and a divider circuit 28 instead of the flip-flop 22 described above. By this circuit, as shown in Fig. 2, the output of the exclusive OR circuit 26 is shifted by 90 ° from the input signal, and signals D and D 'which repeat H and L at 90 ° intervals are obtained. Lose. Therefore, by dividing this signal by the dividing circuit 28 in half, the same signals E and E 'as in the above-described embodiment can be obtained.

Here, since a signal of the same kind can be obtained for two input signals, a signal inverse to each other is obtained at the output.

In addition, although the exclusive OR circuit 26 was employ | adopted in this embodiment, since there is no period which both become H in the signal input to the exclusive OR circuit 26, OR circuit can also be employ | adopted.

4 shows a quadrature detection circuit using the above-described abnormal circuit. In this way, the IF signal is input to the abnormal circuit 30, and a signal having a phase shift of 90 ° from the input signal is obtained at the output, which is input to the multiplier 32. On the other hand, the multiplier 32 is supplied with the IF signal as it is. Multiplication of the input signal with the 90 ° phase ahead and the current input signal is performed. The output of this multiplier is then supplied to the low pass filter 34 and converted into a direct current signal. Thereby, the level which fluctuates with the frequency shift at the output of the low pass filter 34 is obtained, and FM detection is achieved.

1 to 4, an example in which a 90 ° phase is delayed with respect to the center frequency of the FM modulated signal is set, but the present invention is not limited thereto. That is, if it is set to output from the comparators 14a and 14b after the predetermined time elapses from the rise of the input signals A and A 'of FIG. 2, it is not necessary to set it to said 90 degrees. It is good to find and set the ideal abnormal amount suitably. In order to shift the abnormal amount in this manner, conventionally, a coil, a ceramic resonator, or a delay line is used. However, according to the present invention, the constant current source 18a, the capacitor 16a, the voltage of the reference power supply 20a, and the like can be accurately and simply. You can set the delay time.

In the abnormal circuits of FIGS. 1 and 4, it is assumed that a constant delay time is obtained, but this will be described as follows. If the delay time is T0, the delay time T0 is charged with the capacitors 16a and 16b so that the terminal voltage of the capacitors 16a and 16b reaches the reference voltage Vref of the reference power supplies 20a and 20b, and the capacitors 14a and 14b. It is the time until the output signal of () is reversed. In the capacitors 16a and 16b in the abnormal circuit, Q is Q = I.T = C.V when the charge accumulated in the capacitors 16a and 16b is Q. Where I is the current flowing per unit time, T is the time, C is the capacitance, and V is the terminal voltage of the capacitor.

Applying this relationship to capacitors 16a and 16b, Q = IT0 = CVref

Becomes Where I is the constant current of the constant current sources 18a and 18b, and C is the capacitance of the capacitors 16a and 16b. Since the constant current I, the capacitor C, and the reference voltage Vref are fixed values, the delay time T0 can be set to a fixed time, and the delay time can be arbitrarily changed by arbitrarily changing the settings of the constant current I, the capacitor C, and the reference voltage Vref. have.

On the other hand, if the difference between the phase of the original signal of the input signal and the phase of the output signal abnormally output by the abnormal circuit of Fig. 1 or 3 is zero (0),

It becomes Where T is the period of the input signal. The ratio of the delay time to the period of the input signal indicates the phase difference. For example, if the delay time is 1/4 of the period of the input signal, the phase difference becomes π / 2.

Substituting Equation 1 as a delay time into Equation 2 representing such a phase difference,

If the frequency of the input signal is ｆ, from ｆ = 1 / T

Since the capacitance C, the reference voltage Vref, and the constant current I are fixed values, θｆ,, and the frequency and phase difference θ of the input signal are in proportional relationship.

In the quadrature FM detection circuit, although there is a relationship between an input frequency and a phase difference called a so-called S curve characteristic as in Fig. 5A, the linearity of the frequency and phase difference as in Fig. 5B is improved by using such an abnormal circuit. The distortion rate of the FM demodulated signal is improved.

6 shows another embodiment of the present invention. Instead of the reference voltage sources 20a and 20b, the output signal of the D / A conversion circuit 40 is connected. The D / A conversion circuit 40 is connected to a control circuit 42, such as a microcomputer or a PLL controller, for example through FIG. 6 via an external pin in the case of a board or IC. Therefore, the output level of the D / A conversion circuit can be controlled by the external control circuit 42, and the reference levels of the comparators 14a and 14b are variable, so that the delay time can be easily changed. Thereby, it can adjust externally so that the phase difference with respect to the center frequency of an FM demodulation circuit may become an appropriate value.

In particular, the FM demodulation characteristic can be adjusted after completion of the radio receiver set. Specifically, automatic adjustment of the FM demodulation circuit in the production line of the radio receiver set can also be supported. In other words, by connecting the adjusting device 44 to the radio receiver and causing the radio receiver to receive an input signal for the center frequency of the FM signal, the FM signal of the center frequency is input to the FM demodulation circuit, and the adjusting circuit 44 is connected to the adjusting device 44. The demodulation level is compared with a reference value, an adjustment signal is calculated so that the comparison result is zero, and the adjustment signal is transferred to the D / A conversion circuit 40 via the control circuit 42 and the board or external pins. To enter. The voltage corresponding to the adjustment signal is generated from the D / A conversion circuit 40 to become the reference values of the comparators 14a and 14b. As a result, the delay time is adjusted to improve the FM demodulation characteristic to an appropriate value. When the adjustment is finished, the adjustment device 44 is disconnected from the FM receiver set.

In addition, the temperature compensation can be easily realized by using the D / A conversion circuit 40. By storing and executing a temperature compensation program in a control circuit 42 such as a microcomputer or a PLL controller, the FM demodulation circuit can be improved in temperature compensation. In short, when the demodulation circuit is IC, the temperature of the IC changes due to the temperature outside the IC (ambient environment) or the heat generation inside the IC, and the characteristics of the FM demodulation circuit change. By setting a table in which the relationship between the IC temperature and the correction value is stored in the control circuit, the correction value is calculated according to the temperature change, and the digital data to which the correction value is added is applied to the D / A conversion circuit 40. In addition, the delay time of the abnormal circuit can be temperature compensated and the characteristics of the FM demodulation circuit can be compensated.

In addition, as a means for temperature compensation, means for obtaining the constant current sources 18a and 18b and the voltage sources 20a and 20b from the same current source can also be realized as shown in FIG. By setting a value so as to cancel the temperature characteristic of the output current of the current source and the resistance, the delay time can be made constant regardless of the temperature change.

That is, the constant current flowing through the constant current sources 50a and 50b flows to the current mirror input side transistors 52a and 52b of the PNP type in which the collector-base is short-circuited. The bases of the PNP transistors 54a and 56a are connected to the base of the transistor 52a, and the transistors 54a and 56a flow the same current as the transistor 52a. In addition, the bases of the PNP transistors 54b and 56b are connected to the base of the transistor 52b, and the transistors 54b and 56b carry the same current as the transistor 52b. Transistors 52a and 52b provide current to the upper and positive inputs of capacitors 16a and 16b of comparators 14a and 14b, respectively. On the other hand, the transistors 56a and 56b flow current to ground via the resistors 58a and 58b. Thus, a constant voltage is obtained at the upper ends of these resistors 58a and 58b. And this is connected to the negative input terminal of the comparators 14a and 14b. As a result, the constant current sources 50a and 50b operate as constant current sources of the capacitors 16a and 16b, and operate as low voltage sources to the negative input terminals of the comparators 14a and 14b.

When the circuit according to the present invention is ICized, the resistors 58a and 58b are formed as diffusion resistors, and the temperature conditions are set to appropriate values, whereby the comparators 14a and the temperature characteristics of the constant current sources 50a and 50b are formed. The voltage change of the positive input terminal of 14b) can be compensated for by the voltage change of the negative input terminal.

6 and 7 are based on FIG. 1, but needless to say, those applicable to FIG. 3.

As described above, according to the present invention, a voltage rising by a predetermined gradient can be obtained by charging a capacitor with a current from a constant current source, and the predetermined time is obtained by corresponding the desired delay time with the time when the voltage exceeds the reference voltage. Obtain a signal with a rising phase delay. On the other hand, with respect to the inverted input signal, a signal in which the predetermined time rise phase is delayed can be obtained. Thus, it is possible to obtain a signal whose rise of these two signals is delayed by a predetermined time from the input signal. According to the present invention, a signal obtained by shifting a phase for a predetermined time can be obtained by a simple circuit in which a coil is unnecessary. In addition, a resonator, a delay line, or the like is also unnecessary. According to the present invention, an accurate FM detection circuit can be implemented by obtaining an accurate delay time, and the S / N ratio and the distortion rate can be improved.

Claims (8)

An abnormal circuit for shifting a phase of an input signal by a predetermined time and outputting the same, A first delay circuit for delaying the input signal by a predetermined time; A second delay circuit for delaying the inverted signal of the input signal by a predetermined time; and A signal processing circuit for obtaining a signal shifted by a predetermined amount with respect to an input signal from the output signals of the first and second delay circuits; An ideal circuit comprising a. The method of claim 1, wherein the first delay circuit, A first switch that receives an input signal and is turned on or off, A first capacitor charged by a constant current from a constant current source and discharged by the first switch, and A first comparator comparing the charging voltage of the first capacitor with a reference voltage, and obtaining an output whose rising timing is shifted with the input signal by a predetermined time; Including, The second delay circuit, A second switch that receives an inverted signal of the input signal and is turned on or off; A second capacitor charged by a constant current from a constant current source and discharged by the second switch, and A second comparator comparing the charging voltage and the reference voltage of the second capacitor An ideal circuit comprising a. 3. The abnormal circuit according to claim 2, wherein the signal processing circuit is a flip-flop set by one comparator output and reset by the other comparator output. The signal processing circuit of claim 2, wherein the signal processing circuit includes: A logic circuit that takes an exclusive OR or OR of the outputs of both comparators, and Division circuit for dividing the output of the logic circuit An ideal circuit comprising a. The FM detection circuit performs FM detection from the output from the abnormal circuit as described in any one of Claims 2-4, and an input signal. delete The abnormal circuit according to any one of claims 2 to 4, wherein the reference voltage generates external data by digital / analog conversion. 6. The FM detection circuit according to claim 5, wherein the reference voltage generates external data by digital / analog conversion.