CN108227805A - A kind of band gap reference voltage source circuit - Google Patents
A kind of band gap reference voltage source circuit Download PDFInfo
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- CN108227805A CN108227805A CN201711418389.1A CN201711418389A CN108227805A CN 108227805 A CN108227805 A CN 108227805A CN 201711418389 A CN201711418389 A CN 201711418389A CN 108227805 A CN108227805 A CN 108227805A
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
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Abstract
The present invention provide a kind of band gap reference voltage source circuit it include operational amplifier, 3rd resistor, first node, second node, sampling switch, the first capacitance, wave filter, switch combination circuit, N number of bipolar transistor.The first input end of operational amplifier is connected with the second intermediate node, and the second input terminal is connected through 3rd resistor with first node, and output terminal is sampled successively to be switched and the first capacity earth；Connecting node between the input terminal of wave filter and sampling switch and the first capacitance is connected, and the output terminal of wave filter is connected with reference voltage output end.First connecting pin of each bipolar transistor in N number of bipolar transistor is connected with switch combination circuit, its second connection end is connected and is grounded with the control terminal of its own, and switch combination circuit causes the first connecting pin of each bipolar transistor is selectable to be connected with first node or second node.Compared with prior art, the present invention can further improve the precision of the reference voltage of output.
Description
【Technical field】
The present invention relates to electronic circuit technology field, more particularly to a kind of band gap reference voltage source circuit.
【Background technology】
Bandgap voltage reference is widely used in various analog circuits.In practical applications, high-precision band gap base
Reference voltage source is by pro-gaze.It is a kind of circuit diagram of bandgap voltage reference of the prior art shown in please referring to Fig.1,
It includes resistance R1, R2, R3, bipolar transistor PNP pipe Q1, Q2 and operational amplifier OP.It is typically designed the emitter of Q1
Area is bigger than the emitter area of Q2, such as its ratio be K:1, in order to realize relatively good matching effect in actual design,
General Q1 is designed as the K PNP pipe parallel connections as Q2, in one example K=4.The resistance value of general resistance R1 and R2 are set
The same, and being designed as R3 M times of resistance value is counted into, then VBG=Vbe+M.VT.lnK, wherein Vbe is emitter-base stage of Q2
Voltage, M are the ratio between the resistance value of R1 and the resistance value of R3, and VT is thermal voltage, are positive temperature coefficient, and K is the transmitting of Q1 and Q2
Pole area ratio.Vbe is negative temperature coefficient, can realize preferable temperature-compensating by designing suitable M values, realize approximation zero
The VBG voltage values of temperature coefficient.
Although Q1 is designed to coupled in parallel of the K as Q2, deposited between each transistor and Q2 in Q1
It in mismatch, i.e., when produced in large volumes, can be had differences between chip, these differences cause VBG inaccurate, and this species diversity
It can change due to encapsulation stress influences.Even if in wafer or wafer stage, by trimming technology VBG is adjusted very accurate, but
After encapsulation, due to the influence of encapsulation stress, lead between chip that there are deviations again.
Therefore, it is necessary to a kind of improved technical solution is provided to further improve the voltage accuracy of VBG.
【Invention content】
The purpose of the present invention is to provide a kind of band gap reference voltage source circuits, can further improve the benchmark of output
The precision of voltage reduces the mismatch of bipolar transistor and the influence of encapsulation stress.
To solve the above-mentioned problems, the present invention provide a kind of band gap reference voltage source circuit it include operational amplifier, the
Three resistance, the first intermediate node, the second intermediate node, sampling switch, the first capacitance, wave filter, reference voltage output end, switch
Combinational circuit, N number of bipolar transistor and control circuit.Wherein, the first input end of operational amplifier and the second intermediate node
Be connected, the second input terminal of operational amplifier is connected through 3rd resistor with the first intermediate node, the output terminal of operational amplifier according to
It is secondary through the sampling switch and the first capacity earth, the control terminal of the sampling switch is connected with control circuit, the wave filter
Input terminal be connected with the connecting node between the sampling switch and the first capacitance, the output terminal of the wave filter and the base
Quasi- voltage output end is connected.First connecting pin of each bipolar transistor in N number of bipolar transistor with the switch
Combinational circuit is connected, and second connection end is connected and is grounded with the control terminal of its own, is opened described in the control circuit control
Combinational circuit is closed, so that the first connecting pin of each bipolar transistor is selectable with the first intermediate node or the second middle node
Point is connected, and N is more than or equal to 2.
Further, the control circuit controls the switch combination circuit, in different time sections so that N number of bipolar
Transistor is connected to the second intermediate node in turn one by one, and first connecting pin of remaining (N-1) a bipolar transistor is in parallel
It is connected to the first intermediate node.In each period, if the first connecting pin of a bipolar transistor is connected in second
Intermediate node, first connecting pin of remaining (N-1) a bipolar transistor are parallel capacitances connected in parallel to the first intermediate node, the control electricity
Road controls sampling switch conducting, on the voltage of the output terminal of sampled operational amplifier to the first capacitance, after sampling,
The control circuit controls the sampling switch shutdown.
Further, the switch combination circuit includes N number of switching group, and each switching group corresponds to a bipolar transistor
Pipe, the control circuit is by controlling each switching group, so that the first connection of bipolar transistor corresponding with the switching group
It holds and selectable is connected with the first intermediate node or the second intermediate node.
Further, each switching group includes a first switch and a second switch, wherein, one end of first switch
It is connected with the first connecting pin of corresponding bipolar transistor, the other end is connected with the first intermediate node；The one of second switch
End is connected with the first connecting pin of corresponding bipolar transistor, and the other end is connected with the second intermediate node.The control electricity
Road is oscillator, and oscillator first clock signal of output to N clock signals gives N number of switching group respectively, at that time the clock
When signal is the first logic level so that clock signal is worked as in first switch cut-off, second switch conducting in corresponding switching group
During for the second logic level so that the first switch conducting in corresponding switching group, second switch cut-off.The oscillator output
Sampled clock signal gives the control terminal of the sampling switch, when the sampled clock signal is the first logic level so that institute
Sampling switch conducting is stated, when the sampled clock signal is the second logic level so that the sampling switch cut-off.
Further, the first logic level of the first clock signal to N clock signals does not overlap, and saltus step is the successively
One logic level can occur described within each first logic level period of the first clock signal to N clock signals
First logic level of sampled clock signal, and the initial time of the first logic level of the sampled clock signal is than where it
The first clock signal to N clock signals the first logic level period initial time postpone the first predetermined time.
Further, N number of bipolar transistor is identical, and the first clock signal to N clock signals has identical
First logic level time, and phase lagged for the second predetermined time successively, second predetermined time is equal to the first clock signal
To the first logic level time of N clock signals；The filter circuit includes the second capacitance and the 4th resistance, the 4th electricity
Connecting node between one end of resistance and the first capacitance and the sampling switch is connected, and the other end is exported with the reference voltage
End is connected；Second capacitance connection is between the reference voltage output end and ground terminal.
Further, the band gap voltage source circuit further includes first resistor and second resistance, and the one of the first resistor
End is connected with the output terminal of the operational amplifier, second output terminal and the third of the other end with the operational amplifier
Connecting node between resistance is connected；One end of the second resistance is connected with the output terminal of the operational amplifier, another
End is connected with the first output terminal of the operational amplifier.
Further, the first input end of the operational amplifier and second output terminal are respectively the forward direction of operational amplifier
Fan-in and inverse output terminal, N number of bipolar transistor be PNP transistor, the first of the bipolar transistor
Connecting pin, second connection end and control terminal are respectively the emitter-base bandgap grading, collector and base stage of PNP transistor.
Further, the band gap voltage source circuit further includes second resistance, the first metal-oxide-semiconductor and the second metal-oxide-semiconductor, and described
First connecting pin of one metal-oxide-semiconductor and the second metal-oxide-semiconductor is connected with power end, the control terminal of the first metal-oxide-semiconductor and the control of the second metal-oxide-semiconductor
End processed is connected, the connection section between the second connection end of the first metal-oxide-semiconductor and the second input terminal and 3rd resistor of operational amplifier
Point is connected；The control terminal of second metal-oxide-semiconductor is connected with the output terminal of the operational amplifier, the second connection end warp of the second metal-oxide-semiconductor
The second resistance is connected with the first input end of operational amplifier.
Further, the first input end of the operational amplifier and the second input terminal are respectively the reversed of operational amplifier
Input terminal and positive output terminal, N number of bipolar transistor are PNP transistor, and the first of the bipolar transistor connects
End, second connection end and control terminal are respectively the emitter-base bandgap grading, collector and base stage of PNP transistor；First metal-oxide-semiconductor and second
Metal-oxide-semiconductor is PMOS transistor, and the first connecting pin of the first metal-oxide-semiconductor and the second metal-oxide-semiconductor, second connection end and control terminal are distinguished
Source electrode, drain and gate for PMOS transistor.
Compared with prior art, the band gap reference voltage source circuit in the present invention includes switch combination circuit, when different
Between in section, the switch combination circuit causes N number of bipolar transistor to be connected to the second intermediate node B in turn one by one, makes remaining
(N-1) a bipolar transistor is parallel capacitances connected in parallel to the first intermediate node A, and bipolar transistor can be realized by this rotation
Between mismatch be averaged out, so as to realize higher output voltage precision, make its mismatch by bipolar transistor and
The influence smaller of encapsulation stress.
【Description of the drawings】
In order to illustrate the technical solution of the embodiments of the present invention more clearly, required use in being described below to embodiment
Attached drawing be briefly described, it should be apparent that, the accompanying drawings in the following description is only some embodiments of the present invention, for this
For the those of ordinary skill of field, without having to pay creative labor, it can also be obtained according to these attached drawings other
Attached drawing.Wherein：
Fig. 1 is a kind of circuit diagram of bandgap voltage reference of the prior art；
Fig. 2 is the circuit diagram of the band gap reference voltage source circuit of the present invention in one embodiment；
Fig. 3 is the oscillogram of clock signal in one embodiment in Fig. 2；
Fig. 4 is the circuit diagram of the band gap reference voltage source circuit of the present invention in another embodiment；
Fig. 5 is the oscillogram of clock signal in one embodiment in Fig. 4.
【Specific embodiment】
In order to make the foregoing objectives, features and advantages of the present invention clearer and more comprehensible, it is below in conjunction with the accompanying drawings and specific real
Applying mode, the present invention is described in further detail.
" one embodiment " or " embodiment " referred to herein refers to may be included at least one realization method of the present invention
A particular feature, structure, or characteristic." in one embodiment " that different places occur in the present specification not refers both to same
A embodiment, nor the individual or selective embodiment mutually exclusive with other embodiment.Unless stated otherwise, herein
In connect, be connected, connecting expression be electrically connected word represent directly or indirectly to be electrical connected.
Shown in please referring to Fig.2, the circuit signal for the band gap reference voltage source circuit of the present invention in one embodiment
Figure.Band gap reference voltage source circuit shown in Fig. 2 includes 3rd resistor R3, operational amplifier OP, the first intermediate node A, second
Intermediate node B, sampling switch S6, the first capacitance C1, wave filter 210, reference voltage output end VBG, switch combination circuit 220, N
A bipolar transistor and control circuit 230.
Wherein, the first input end of the operational amplifier OP is connected with the second intermediate node B, the operation amplifier
The second input terminal of device OP is connected through the 3rd resistor R3 with the first intermediate node A, and the operational amplifier OP's is defeated
Outlet is grounded successively through the sampling switch S6 and the first capacitance C1, control terminal and the control of the sampling switch S6
Circuit 230 is connected；Connection section between the input terminal of the wave filter 210 and the sampling switch S6 and the first capacitance C1
Point is connected, and the output terminal of the wave filter 210 is connected with reference voltage output end VBG, and the wave filter 210 is used to filter out first
Voltage fluctuation on capacitance C1 is exported the average voltage to the reference voltage output end VBG with forming average voltage.
In N number of bipolar transistor, the first connecting pin of each bipolar transistor with the switch combination circuit
220 are connected, and second connection end is connected and is grounded with the control terminal of its own；The control circuit 230 controls the switch
Combinational circuit 220 so that the first connecting pin of each bipolar transistor it is selectable among the first intermediate node A or second
Node B is connected, wherein, N is more than or equal to 2.The control circuit 230 controls the switch combination circuit 220, in different time sections
In so that N number of bipolar transistor is connected to the second intermediate node B in turn one by one, and makes remaining (N-1) a bipolar transistor
It is parallel capacitances connected in parallel to the first intermediate node A.In each period, if the first connecting pin of a bipolar transistor is connected to
Second intermediate node B, and first connecting pin of remaining (N-1) a bipolar transistor is parallel capacitances connected in parallel to the first intermediate node A
Afterwards, the control circuit 230 controls sampling switch S6 conductings, with the voltage of the output terminal of sampled operational amplifier OP to the first electricity
Hold on C1, after sampling, the control circuit 230 controls sampling switch S6 shutdowns.
In specific embodiment shown in Fig. 2, the band gap reference voltage source circuit further includes first resistor R1 and second
Resistance R2.One end of the first resistor R1 is connected with the output terminal of operational amplifier OP, the other end and operational amplifier OP
The second input terminal and the 3rd resistor R3 between connecting node be connected；One end of the second resistance R2 and operation amplifier
The output terminal of device OP is connected, and the other end is connected with the first input end of operational amplifier OP.
In specific embodiment shown in Fig. 2, N is equal to 5, Fig. 2 and is designed to the same bipolar transistor using 5 altogether
Q1~Q5 is made of the Q1 in isoboles 14 bipolar transistors therein, is made of remaining 1 bipolar transistor
Imitate Fig. 1 in Q2, i.e., with the bipolar transistor that the first intermediate node A is connected with and the second intermediate node B be connected it is ambipolar
The ratio between emitter area of transistor is 4:1.But in different time sections, the bipolar transistor allowed respectively in Fig. 2 connects
The second intermediate node B is connected to, and other four bipolar transistors are connected to the first intermediate node A, in this way, equivalent operation circuit
Schematic diagram it is similar to Fig. 1, only Q1~Q5 bipolar transistors are constantly recycled replacement to the second intermediate node B one by one.
In specific embodiment shown in Fig. 2, the switch combination circuit 220 includes 5 switching groups (221~225), often
A switching group corresponds to a bipolar transistor, and the control circuit 230 is by controlling each switching group, so that with the switch
First connecting pin of the corresponding bipolar transistor of group is selectable to be connected with the first intermediate node A or the second intermediate node B.Example
Such as, switching group 221 is corresponding with bipolar transistor Q1, by the way that switching group 221 is controlled to may be such that the first of bipolar transistor Q1
Connecting pin is selectable to be connected with the first intermediate node A or the second intermediate node B；Q2 pairs of switching group 222 and bipolar transistor
Should, by control switching group 222 may be such that the first connecting pin of bipolar transistor Q2 it is selectable with the first intermediate node A or
Second intermediate node B is connected；Switching group 223 is corresponding with bipolar transistor Q3, ambipolar by the way that switching group 223 is controlled to may be such that
The first connecting pin of transistor Q3 is selectable to be connected with the first intermediate node A or the second intermediate node B；Switching group 224 with it is double
Bipolar transistor Q4 correspond to, by control switching group 224 may be such that the first connecting pin of bipolar transistor Q4 it is selectable with
First intermediate node A or the second intermediate node B are connected；Switching group 225 is corresponding with bipolar transistor Q5, by controlling switching group
225 may be such that the first connecting pin of bipolar transistor Q5 is selectable with the first intermediate node A or the second intermediate node B phases
Even.
In specific embodiment shown in Fig. 2, each switching group includes a first switch and a second switch,
In, one end of first switch is connected with the first connecting pin of corresponding bipolar transistor, the other end and the first intermediate node A
It is connected；One end of second switch is connected with the first connecting pin of corresponding bipolar transistor, the other end and the second middle node
Point B is connected.For example, switching group 221 include first switch S1a and second switch S1b, wherein, one end of first switch S1a with it is right
The first connecting pin of the bipolar transistor Q1 answered is connected, and the other end is connected with the first intermediate node A, second switch S1b's
One end is connected with the first connecting pin of corresponding bipolar transistor Q1, and the other end is connected with the second intermediate node B；Switching group
222 include first switch S2a and second switch S2b, wherein, one end of first switch S2a and corresponding bipolar transistor Q2
The first connecting pin be connected, the other end is connected with the first intermediate node A, one end of second switch S2b with it is corresponding ambipolar
The first connecting pin of transistor Q2 is connected, and the other end is connected with the second intermediate node B；Switching group 223 includes first switch S3a
With second switch S3b, wherein, one end of first switch S3a is connected with the first connecting pin of corresponding bipolar transistor Q3,
The other end is connected with the first intermediate node A, the first connecting pin of one end of second switch S3b and corresponding bipolar transistor Q3
It is connected, the other end is connected with the second intermediate node B；Switching group 224 includes first switch S4a and second switch S4b, wherein,
One end of first switch S4a is connected with the first connecting pin of corresponding bipolar transistor Q4, the other end and the first middle node
Point A is connected, and one end of second switch S4b is connected with the first connecting pin of corresponding bipolar transistor Q4, the other end and
Two intermediate node B are connected；Switching group 225 includes first switch S5a and second switch S5b, wherein, one end of first switch S5a
It is connected with the first connecting pin of corresponding bipolar transistor Q5, the other end is connected with the first intermediate node A, second switch
One end of S5b is connected with the first connecting pin of corresponding bipolar transistor Q5, and the other end is connected with the second intermediate node B.
In specific embodiment shown in Fig. 2, the control circuit 230 is oscillator, and the oscillator 230 generates clock
Signal CK1, CK1B, CK2, CK2B, CK3, CK3B, CK4, CK4B, CK5, CK5B, CK6, clock signal CK1B and CK1 respectively with
First switch S1a in switching group 221 is connected with the control terminal of second switch S1b, clock signal CK2B and CK2 respectively with switch
Group 222 in first switch S2a be connected with the control terminal of second switch S2b, clock signal CK3B and CK3 respectively with switching group
First switch S3a in 223 is connected with the control terminal of second switch S3b, clock signal CK4B and CK4 respectively with switching group 224
In first switch S4a be connected with the control terminal of second switch S4b, clock signal CK5B and CK5 respectively in switching group 225
First switch S5a is connected with the control terminal of second switch S5b.
In Fig. 2, clock signal CK1B and CK1 inversion signal each other, i.e., CK1B is low level when CK1 is high level, and CK1 is
CK1B is high level during low level；CK2B and CK2 inversion signal each other, i.e., CK2B is low level when CK2 is high level, and CK2 is
CK2B is high level during low level；CK3B and CK3 inversion signal each other, i.e., CK3B is low level when CK3 is high level, and CK3 is
CK3B is high level during low level；CK4B and CK4 inversion signal each other, i.e., CK4B is low level when CK4 is high level, and CK4 is
CK4B is high level during low level；CK5B and CK5 inversion signal each other, i.e., CK5B is low level when CK5 is high level, and CK5 is
CK5B is high level during low level.When these clock signals are all for high level (or being the first logic level), control is connected
Switch conduction；When these clocks are low level (or being the second logic level), connected switch is controlled to disconnect and (is not led
It is logical).It may also be said that the control circuit 230 exports clock signal CK1-CK5 respectively to switching group 221-225, work as clock signal
When CK1-CK5 is the first logic level so that first switch cut-off, second switch conducting in corresponding switching group 221-225,
When clock signal CK1-CK5 is the second logic level so that the first switch conducting in corresponding switching group, second switch are cut
Only.
It is the oscillogram of clock signal in one embodiment in Fig. 2 shown in please referring to Fig.3, from the figure 3, it may be seen that when
The high level (or for the first logic level) of clock signal CK1-CK5 does not overlap, and it (or is first that saltus step, which be high level, successively
Logic level).In specific embodiment shown in Fig. 3, it (or is first that clock signal CK1-CK5, which has identical high level,
Logic level) time, and phase lags a predetermined time successively, which is equal to the phase that clock signal CK1-CK5 has
Same high level time.
It can be realized according to Fig. 3 waveforms, one in bipolar transistor Q1~Q5 is connected to the second middle node in turn
Point B, and other four bipolar transistors are parallel capacitances connected in parallel to the first intermediate node A.In addition, sampled clock signal CK6 is in office
All there is high level (the first logic level) in the high level (or first logic level) of what CK1~CK5 in the period, but it rises
Along delay Td times (as shown in Figure 3), i.e., described sampled clock signal CK6 is (i.e. high for the time of high level by low transition
The initial time of level) high level time section than CK1~CK5 where it by time that low transition is high level
(i.e. the initial time of high level) delay scheduled time Td.When this delay time Td is to ensure rotation bipolar transistor,
Circuit enough time is left for so as to the output voltage (VS) of operational amplifier OP to stablize.After VS voltage stabilizations, opened by sampling
It closes S6 to sample on this voltage to capacitance C1, due to the presence of mismatch, leads to sample the voltage on C1 in different clocks phase
There are fluctuations, and fluctuation can be filtered out by the wave filter 210 being made of the 4th resistance R4 and the second capacitance C2, form average electricity
Pressure.By this rotation and average effect, it can realize that the mismatch between bipolar transistor is averaged out, it therefore, can be with
Realize higher output voltage precision, reducing is influenced by bipolar transistor mismatch.
It should be strongly noted that in the embodiment shown in Figure 2, the first input end of the operational amplifier OP and
Two input terminals are respectively the positive input and inverse output terminal of operational amplifier OP；N number of bipolar transistor is positive-negative-positive
Transistor, the first connecting pin, second connection end and the control terminal of the bipolar transistor be respectively the emitter-base bandgap grading of PNP transistor,
Collector and base stage.
The present invention not only can be adapted for band-gap reference source structure shown in Fig. 2, be also applied for other any band-gap references
Source structure.Shown in please referring to Fig.4, the circuit signal for the band gap reference voltage source circuit of the present invention in another embodiment
Figure.Band gap reference voltage source circuit shown in Fig. 4 includes 3rd resistor R3, operational amplifier OP, the first intermediate node A, second
Intermediate node B, sampling switch S6, the first capacitance C1, wave filter 310, reference voltage output end VBG, switch combination circuit 320, N
A bipolar transistor and control circuit 330.
Wherein, the first input end of the operational amplifier OP is connected with the second intermediate node B, the operation amplifier
The second input terminal of device OP is connected through the 3rd resistor R3 with the first intermediate node A, and the operational amplifier OP's is defeated
Outlet is grounded successively through the sampling switch S6 and the first capacitance C1, control terminal and the control of the sampling switch S6
Circuit 330 is connected；Connection section between the input terminal of the wave filter 310 and the sampling switch S6 and the first capacitance C1
Point is connected, and the output terminal of the wave filter 310 is connected with reference voltage output end VBG, and the wave filter 310 is used to filter out first
Voltage fluctuation on capacitance C1 is exported the average voltage to the reference voltage output end VBG with forming average voltage.
In N number of bipolar transistor, the first connecting pin of each bipolar transistor with the switch combination circuit 320
It is connected, second connection end is connected and is grounded with the control terminal of its own；The control circuit 330 controls the switch combination
Circuit 320, so that the first connecting pin of each bipolar transistor is selectable with the first intermediate node A or the second intermediate node
B is connected, wherein, N is more than or equal to 2.The control circuit 330 controls the switch combination circuit 320, in different time sections,
So that N number of bipolar transistor is connected to the second intermediate node B in turn one by one, and make remaining (N-1) a bipolar transistor quilt
It is connected in parallel to the first intermediate node A.In each period, if the first connecting pin of a bipolar transistor is connected to B
Point, and after first connecting pin of remaining (N-1) a bipolar transistor is parallel capacitances connected in parallel to A points, the control circuit 330 controls
Sampling switch S6 is connected, described after sampling on the voltage of the output terminal of sampled operational amplifier OP to the first capacitance C1
Control circuit 330 controls sampling switch S6 shutdowns.
In specific embodiment shown in Fig. 4, the band gap reference voltage source circuit further includes second resistance R2, first
The first connecting pin of metal-oxide-semiconductor MP1 and the second metal-oxide-semiconductor MP2, the first metal-oxide-semiconductor MP1 and the second metal-oxide-semiconductor MP2 are and power end
VIN is connected, and the control terminal of the first metal-oxide-semiconductor MP1 is connected with the control terminal of the second metal-oxide-semiconductor MP2, the second connection of the first metal-oxide-semiconductor MP1
End is connected with the connecting node between the second connection end of operational amplifier OP and 3rd resistor R3；The control of second metal-oxide-semiconductor MP2
End is connected with the output terminal of the operational amplifier OP, and the second connection end of the second metal-oxide-semiconductor MP2 is put through second resistance R2 with operation
The first input end of big device OP is connected.
In specific embodiment shown in Fig. 4, N is equal to 3, Fig. 4 and is designed to the same bipolar transistor using 3 altogether
Q1~Q3 is made of the Q1 in isoboles 12 bipolar transistors therein, is made of remaining 1 bipolar transistor
Imitate Fig. 1 in Q2, i.e., with the bipolar transistor that the first intermediate node A is connected with and the second intermediate node B be connected it is ambipolar
The ratio between emitter area of transistor is 2:1.But in different time sections, the bipolar transistor allowed respectively in Fig. 4 connects
The second intermediate node B is connected to, and other two bipolar transistors are connected to the first intermediate node A, in this way, equivalent operation circuit
Schematic diagram it is similar to Fig. 1, only Q1~Q3 bipolar transistors are constantly recycled replacement to the second intermediate node B one by one.
In the embodiment shown in fig. 4 and the bipolar transistors that are connected of the first intermediate node A with and the second intermediate node
The ratio between emitter area of bipolar transistor that B is connected is 2:1, but other any values can be taken in practice, larger ratio
It may realize better effect, because rotation effects are more preferable, and the difference of the base emitter voltage of two-way bipolar transistor is more
Greatly, can reduce is influenced, therefore precision is more preferably by operational amplifier input mismatch.
In specific embodiment shown in Fig. 4, the switch combination circuit 320 includes 3 switching groups (321~323), often
A switching group corresponds to a bipolar transistor, and the control circuit 330 is by controlling each switching group, so that with the switch
First connecting pin of the corresponding bipolar transistor of group is selectable to be connected with the first intermediate node A or the second intermediate node B.Example
Such as, switching group 321 is corresponding with bipolar transistor Q1, by the way that switching group 321 is controlled to may be such that the first of bipolar transistor Q1
Connecting pin is selectable to be connected with the first intermediate node A or the second intermediate node B；Q2 pairs of switching group 322 and bipolar transistor
Should, by control switching group 322 may be such that the first connecting pin of bipolar transistor Q2 it is selectable with the first intermediate node A or
Second intermediate node B is connected；Switching group 323 is corresponding with bipolar transistor Q3, ambipolar by the way that switching group 323 is controlled to may be such that
The first connecting pin of transistor Q3 is selectable to be connected with the first intermediate node A or the second intermediate node B.
In specific embodiment shown in Fig. 4, each switching group includes a first switch and a second switch,
In, one end of first switch is connected with the first connecting pin of corresponding bipolar transistor, the other end and the first intermediate node A
It is connected；One end of second switch is connected with the first connecting pin of corresponding bipolar transistor, the other end and the second middle node
Point B is connected.For example, switching group 321 include first switch S1a and second switch S1b, wherein, one end of first switch S1a with it is right
The first connecting pin of the bipolar transistor Q1 answered is connected, and the other end is connected with the first intermediate node A, second switch S1b's
One end is connected with the first connecting pin of corresponding bipolar transistor Q1, and the other end is connected with the second intermediate node B；Switching group
322 include first switch S2a and second switch S2b, wherein, one end of first switch S2a and corresponding bipolar transistor Q2
The first connecting pin be connected, the other end is connected with the first intermediate node A, one end of second switch S2b with it is corresponding ambipolar
The first connecting pin of transistor Q2 is connected, and the other end is connected with the second intermediate node B；Switching group 323 includes first switch S3a
With second switch S3b, wherein, one end of first switch S3a is connected with the first connecting pin of corresponding bipolar transistor Q3,
The other end is connected with the first intermediate node A, the first connecting pin of one end of second switch S3b and corresponding bipolar transistor Q3
It is connected, the other end is connected with the second intermediate node B.
In specific embodiment shown in Fig. 4, the control circuit 330 is oscillator, and the oscillator 330 generates clock
Signal CK1, CK1B, CK2, CK2B, CK3, CK3B, CK6, clock signal CK1B and CK1 are opened respectively with first in switching group 321
Close S1a be connected with the control terminal of second switch S1b, clock signal CK2B and CK2 respectively with the first switch in switching group 322
S2a is connected with the control terminal of second switch S2b, clock signal CK3B and CK3 respectively with the first switch S3a in switching group 323
It is connected with the control terminal of second switch S3b.
In Fig. 4, clock signal CK1B and CK1 inversion signal each other, i.e., CK1B is low level when CK1 is high level, and CK1 is
CK1B is high level during low level；CK2B and CK2 inversion signal each other, i.e., CK2B is low level when CK2 is high level, and CK2 is
CK2B is high level during low level；CK3B and CK3 inversion signal each other, i.e., CK3B is low level when CK3 is high level, and CK3 is
CK3B is high level during low level.When these clock signals are all for high level (or being the first logic level), control is connected
Switch conduction；When these clocks are low level (or being the second logic level), connected switch is controlled to disconnect and (is not led
It is logical).It may also be said that the control circuit 330 exports clock signal CK1-CK3 respectively to switching group 321-323, work as clock signal
When CK1-CK3 is the first logic level so that first switch cut-off, second switch conducting in corresponding switching group 321-323,
When clock signal CK1-CK3 is the second logic level so that the first switch conducting in corresponding switching group, second switch are cut
Only.
It please refers to shown in Fig. 5, is the oscillogram of clock signal in one embodiment in Fig. 4, as shown in Figure 5, when
The high level (or for the first logic level) of clock signal CK1-CK3 does not overlap, and it (or is first that saltus step, which be high level, successively
Logic level).In specific embodiment shown in Fig. 5, it (or is first that clock signal CK1-CK3, which has identical high level,
Logic level) time, and phase lags a predetermined time successively, which is equal to the phase that clock signal CK1-CK3 has
Same high level time.
It can be realized according to Fig. 5 waveforms, one in bipolar transistor Q1~Q3 is connected to the second middle node in turn
Point B, and other two bipolar transistors are parallel capacitances connected in parallel to the first intermediate node A.In addition, sampled clock signal CK6 is in office
All there is high level (the first logic level) in the high level (or first logic level) of what CK1~CK3 in the period, but it rises
Along delay Td times (as shown in Figure 5), i.e., described sampled clock signal CK6 is (i.e. high for the time of high level by low transition
The initial time of level) high level time section than CK1~CK3 where it by time that low transition is high level
(i.e. the initial time of high level) delay scheduled time Td.When this delay time Td is to ensure rotation bipolar transistor,
Circuit enough time is left for so as to the output voltage (VS) of operational amplifier OP to stablize.After VS voltage stabilizations, opened by sampling
It closes S6 to sample on this voltage to capacitance C1, due to the presence of mismatch, leads to sample the voltage on C1 in different clocks phase
There are fluctuations, and fluctuation can be filtered out by the wave filter 210 being made of the 4th resistance R4 and the second capacitance C2, form average electricity
Pressure.By this rotation and average effect, it can realize that the mismatch between bipolar transistor is averaged out, it therefore, can be with
Realize higher output voltage precision, reducing is influenced by bipolar transistor mismatch.
It should be strongly noted that in the embodiment shown in fig. 4, the first input end of the operational amplifier OP and
Two output terminals are respectively the reverse input end of operational amplifier OP and positive output terminal；N number of bipolar transistor is positive-negative-positive
Transistor, the first connecting pin, second connection end and the control terminal of the bipolar transistor be respectively the emitter-base bandgap grading of PNP transistor,
Collector and base stage；The first metal-oxide-semiconductor MP1 and the second metal-oxide-semiconductor MP2 is PMOS transistor, and the first metal-oxide-semiconductor MP1 and
The first connecting pin, second connection end and the control terminal of two metal-oxide-semiconductor MP2 is respectively the source electrode of PMOS transistor, drain and gate.
In the present invention, the word that the expressions such as " connection ", connected, " company ", " connecing " are electrical connected, unless otherwise instructed, then
Represent direct or indirect electric connection.
It should be pointed out that any change that one skilled in the art does the specific embodiment of the present invention
All without departing from the range of claims of the present invention.Correspondingly, the scope of the claims of the invention is also not merely limited to
In previous embodiment.
Claims (8)
1. a kind of band gap reference voltage source circuit, which is characterized in that it includes operational amplifier, 3rd resistor, the first middle node
It is point, the second intermediate node, sampling switch, the first capacitance, wave filter, reference voltage output end, switch combination circuit, N number of bipolar
Transistor npn npn and control circuit,
Wherein, the first input end of operational amplifier is connected with the second intermediate node, and the second input terminal of operational amplifier is through
Three resistance are connected with the first intermediate node, the output terminal of operational amplifier successively through the sampling switch and the first capacity earth,
The control terminal of the sampling switch is connected with control circuit, the input terminal of the wave filter and the sampling switch and the first capacitance
Between connecting node be connected, the output terminal of the wave filter is connected with the reference voltage output end,
First connecting pin of each bipolar transistor in N number of bipolar transistor is connected with the switch combination circuit,
Its second connection end is connected and is grounded with the control terminal of its own, and the control circuit controls the switch combination circuit, with
It is connected so that the first connecting pin of each bipolar transistor is selectable with the first intermediate node or the second intermediate node, N is more than
Equal to 2.
2. band gap reference voltage source circuit according to claim 1, which is characterized in that
The control circuit controls the switch combination circuit, in different time sections so that N number of bipolar transistor is taken turns one by one
Stream is connected to the second intermediate node, and first connecting pin of remaining (N-1) a bipolar transistor is parallel capacitances connected in parallel among first
Node,
In each period, if the first connecting pin of a bipolar transistor is connected to the second intermediate node, remaining (N-1)
First connecting pin of a bipolar transistor is parallel capacitances connected in parallel to the first intermediate node, and the control circuit control sampling is opened
Conducting is closed, on the voltage of the output terminal of sampled operational amplifier to the first capacitance, after sampling, the control circuit controls
The sampling switch shutdown.
3. band gap voltage source circuit according to claim 2, which is characterized in that
The switch combination circuit includes N number of switching group, and each switching group corresponds to a bipolar transistor, the control circuit
By controlling each switching group, so that the first connecting pin of bipolar transistor corresponding with the switching group is selectable with first
Intermediate node or the second intermediate node are connected.
4. band gap voltage source circuit according to claim 3, which is characterized in that
Each switching group includes a first switch and a second switch, wherein, one end of first switch with it is corresponding bipolar
First connecting pin of transistor npn npn is connected, and the other end is connected with the first intermediate node；One end of second switch with it is corresponding double
First connecting pin of bipolar transistor is connected, and the other end is connected with the second intermediate node,
The control circuit is oscillator, and the oscillator exports the first clock signal to N clock signals respectively to N number of switch
Group, when the clock signal is the first logic level at that time so that the first switch cut-off in corresponding switching group, second switch are led
It is logical, when clock signal is the second logic level so that the first switch conducting in corresponding switching group, second switch cut-off,
The oscillator exports control terminal of the sampled clock signal to the sampling switch, when the sampled clock signal is first
During logic level so that the sampling switch conducting, when the sampled clock signal is the second logic level so that described to adopt
Sample switch cut-off.
5. band gap voltage source circuit according to claim 4, which is characterized in that
First logic level of the first clock signal to N clock signals does not overlap, and saltus step is the first logic level successively,
The sampling clock can occur within each first logic level period of the first clock signal to N clock signals
First logic level of signal, and the initial time of the first logic level of the sampled clock signal than where it first when
The initial time of clock signal to the first logic level period of N clock signals postponed for the first predetermined time.
6. band gap voltage source circuit according to claim 4, which is characterized in that
N number of bipolar transistor is identical,
First clock signal to N clock signals have the first identical logic level time, and phase lags second in advance successively
It fixes time, second predetermined time is equal to the first clock signal to the first logic level time of N clock signals；
The filter circuit includes the second capacitance and the 4th resistance, one end and the first capacitance and the sampling of the 4th resistance
Connecting node between switch is connected, and the other end is connected with the reference voltage output end；Second capacitance connection is in institute
It states between reference voltage output end and ground terminal.
7. the band gap voltage source circuit according to claim 1-6, which is characterized in that it further includes first resistor and the second electricity
Resistance,
One end of the first resistor is connected with the output terminal of the operational amplifier, the other end and the operational amplifier
Connecting node between second output terminal and the 3rd resistor is connected；
One end of the second resistance is connected with the output terminal of the operational amplifier, the other end and the operational amplifier
First output terminal is connected.
8. band gap voltage source circuit according to claim 7, which is characterized in that
The first input end and second output terminal of the operational amplifier be respectively operational amplifier positive fan-in and
Inverse output terminal,
N number of bipolar transistor is PNP transistor, the first connecting pin of the bipolar transistor, second connection end and
Control terminal is respectively the emitter-base bandgap grading, collector and base stage of PNP transistor.
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| CN201711418389.1A CN108227805A (en) | 2017-12-25 | 2017-12-25 | A kind of band gap reference voltage source circuit |
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| CN201711418389.1A CN108227805A (en) | 2017-12-25 | 2017-12-25 | A kind of band gap reference voltage source circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110471481A (en) * | 2019-09-16 | 2019-11-19 | 南京中感微电子有限公司 | A kind of high-precision pressure regulator |
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| CN102165696A (en) * | 2008-09-29 | 2011-08-24 | 松下电器产业株式会社 | Signal generation circuit, and single-slope AD converter and camera using the same |
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| CN203930569U (en) * | 2014-06-13 | 2014-11-05 | 无锡中星微电子有限公司 | Low imbalance band-gap reference source circuit and low imbalance buffer circuit |
| CN104460803A (en) * | 2014-12-01 | 2015-03-25 | 无锡中星微电子有限公司 | Band-gap reference voltage generating circuit |
| CN104901359A (en) * | 2015-05-13 | 2015-09-09 | 无锡中星微电子有限公司 | Charging and discharging control device with battery current detection circuit |
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| CN102165696A (en) * | 2008-09-29 | 2011-08-24 | 松下电器产业株式会社 | Signal generation circuit, and single-slope AD converter and camera using the same |
| CN102176187A (en) * | 2009-10-08 | 2011-09-07 | 英特赛尔美国股份有限公司 | Circuits and methods to produce a vptat and/or a bandgap voltage with low-glitch preconditioning |
| CN203930569U (en) * | 2014-06-13 | 2014-11-05 | 无锡中星微电子有限公司 | Low imbalance band-gap reference source circuit and low imbalance buffer circuit |
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Application publication date: 20180629 |