CN108269782A - 高电容值金属隔离金属电容 - Google Patents
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- 229910052751 metal Inorganic materials 0.000 title claims abstract description 126
- 239000002184 metal Substances 0.000 title claims abstract description 126
- 239000000758 substrate Substances 0.000 claims abstract description 14
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 15
- 229910052802 copper Inorganic materials 0.000 claims description 15
- 239000010949 copper Substances 0.000 claims description 15
- 230000001788 irregular Effects 0.000 claims description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 2
- 239000010931 gold Substances 0.000 claims description 2
- 229910052737 gold Inorganic materials 0.000 claims description 2
- 230000002093 peripheral effect Effects 0.000 claims description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 13
- 238000000034 method Methods 0.000 description 10
- 239000004065 semiconductor Substances 0.000 description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 7
- 239000000463 material Substances 0.000 description 6
- 230000008569 process Effects 0.000 description 6
- 239000011521 glass Substances 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 238000009713 electroplating Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 2
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910002244 LaAlO3 Inorganic materials 0.000 description 1
- 229910004205 SiNX Inorganic materials 0.000 description 1
- 229910002370 SrTiO3 Inorganic materials 0.000 description 1
- 229910010303 TiOxNy Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 229910003134 ZrOx Inorganic materials 0.000 description 1
- 238000002679 ablation Methods 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 238000000231 atomic layer deposition Methods 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 229910052593 corundum Inorganic materials 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum oxide Inorganic materials [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- KTUFCUMIWABKDW-UHFFFAOYSA-N oxo(oxolanthaniooxy)lanthanum Chemical compound O=[La]O[La]=O KTUFCUMIWABKDW-UHFFFAOYSA-N 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 229910001845 yogo sapphire Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
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- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
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- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
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Abstract
本发明公开了一种金属隔离金属电容，包含一衬底，其上设有一第一介电层；一下电极，埋设于所述第一介电层中，所述下电极包含一金属盘及凸出于所述金属盘一上表面的一三维金属结构；一第二介电层，围绕所述三维金属结构；一电容介电层，覆盖所述三维金属结构及所述第二介电层；以及一上电极，设于所述电容介电层上，所述上电极包含与所述三维金属结构指叉互合的鳍状结构。
Description
技术领域
本发明涉及半导体技术领域，特别是涉及一种半导体结构，包含一高电容值金属隔离金属电容结构，及其制造方法。
背景技术
芯片上金属隔离金属电容乃公知技术，其通常被整合在混合信号电路或射频电路芯片中，作为去耦合电容，于电源分布网络中提供较佳的电压调节及抗噪能力。
为了达到最低要求的电容值，芯片上金属隔离金属电容通常需占用不少芯片面积，导致芯片尺寸及成本增加。因此，所述技术领域仍需要一种高电容值金属隔离金属电容结构，不会增加芯片尺寸及成本。
发明内容
本发明的主要目的在提供一三维金属隔离金属电容结构，具有高电容值，而能解决上述背景技术的不足与缺点。
根据本发明实施例，提供一种金属隔离金属电容，包含一衬底，其上设有一第一介电层；一下电极，埋设于所述第一介电层中，所述下电极包含一金属盘及凸出于所述金属盘一上表面的一三维金属结构；一第二介电层，围绕所述三维金属结构；一电容介电层，覆盖所述三维金属结构及所述第二介电层；以及一上电极，设于所述电容介电层上，所述上电极包含与所述三维金属结构指叉互合的鳍状结构。
为让本发明的上述目的、特征及优点能更明显易懂，下文特举优选实施方式，并配合附图，作详细说明如下。然而如下的优选实施方式与附图仅供参考与说明用，并非用来对本发明加以限制。
附图说明
图1至图9是剖面示意图，其是依据本发明实施例所绘示的金属隔离金属电容结构的例示作法。
其中，附图标记说明如下：
100 衬底
100a 主表面
110 介电层
110a 上表面
112 镶嵌金属盘
112a 上表面
114 镶嵌金属导线
114a 上表面
120a、120b 铜金属层
122a、122b 扩散阻挡层
130 晶种层
132 光刻胶层
132a 开孔
140 三维金属结构
150 介电层
160 光刻胶层
160a 开孔
162 凹陷结构
170 介电层
210 下电极
220 电容介电层
230 上电极
230a 鳍状结构
412、414 镶嵌金属内联机
422、424 导孔
CR 电容形成区域
具体实施方式
在下文中，加以陈述本发明的具体实施方式，所述具体实施方式可参考相对应的附图，使所述附图构成实施方式的一部分。同时也借由说明，公开本发明可据以施行的方式。所述等实施例已被清楚地描述足够的细节，俾使本领域技术人员可据以实施本发明。其他实施例亦可被加以施行，且对于其结构上所做的改变仍属本发明所涵盖的范畴。
因此，下文的细节描述将不被视为一种限定，且本发明所涵盖的范畴仅被所附的权利要求书以及其同意义的涵盖范围。本发明的一或多个实施例将参照附图描述，其中，相同元件符号始终用以表示相同元件，且其中阐述的结构未必按比例所绘制。
文中所使用的用语“晶圆”及“衬底”包括任何具有暴露表面的结构，根据本发明，在所述表面上可沉积有一至少层材料，例如，形成例如重分布层的电路结构。用语“衬底”被理解为包括半导体晶圆，但不限在此。用语“衬底”亦可用以指加工过程中的半导体结构，且可包括已被制造在其上的其它层。
请参阅图1至图9，其是依据本发明实施例所绘示的金属隔离金属电容结构的例示作法。
如图1所示，首先提供一衬底100。衬底100可以包含一半导体衬底，例如硅衬底。然而，应理解衬底100也可以包含掺杂或未掺杂的半导体材料、由一半导体基材或一隔离材支撑的外延半导体层，或所述技术领域所公知的其它半导体结构。
根据本发明实施例，衬底100包含一主表面100a。例如，在主表面100a上，可以形成多个半导体元件，如MOS晶体管(图未示)。根据本发明实施例，在主表面100a上沉积有至少一介电层110，例如，金属层间介电层。例如，介电层110可以包含氧化硅、氮化硅、氮氧化硅、硼磷硅玻璃(BPSG)、磷硅玻璃(PSG)，但不限在此。
根据本发明实施例，在一电容形成区域CR内，至少形成有一镶嵌金属盘112，埋设于介电层110中。在电容形成区域CR外，可选择形成一镶嵌金属导线114，埋设于介电层110中。根据本发明实施例，镶嵌金属盘112及镶嵌金属导线114可以利用铜镶嵌工艺制造而成。根据本发明实施例，镶嵌金属盘112及镶嵌金属导线114可以形成于第一层金属(M1)中，但不限在此。
例如，镶嵌金属盘112可以包含一铜金属层120a及一包围铜金属层120a的扩散阻挡层122a。扩散阻挡层122b，如钛、氮化钛、钽、氮化钽等，可以避免铜金属扩散进入到介电层110中。同样的，镶嵌金属导线114可以包含一铜金属层120b及一包围铜金属层120b的扩散阻挡层122b。
通常，在铜镶嵌工艺中，可以包含进行一化学机械抛光工艺，以从介电层110的上表面110a上去除多余的铜金属。所以，此时镶嵌金属盘112的上表面112a及镶嵌金属导线114的上表面114a与介电层110的上表面110a齐平。
如图2所示，接着于镶嵌金属盘112的上表面112a、镶嵌金属导线114的上表面114a及介电层110的上表面110a上沉积一晶种层130，如铜晶种层。接着，于晶种层130上形成一光刻胶层132。
如图3所示，进行一光刻工艺，包括，但不限于，一曝光工艺及一显影工艺，以于光刻胶层132中形成开孔132a。开孔132a的图案可以包括，但不限于，一导孔型沟槽、一线型沟槽、一波浪型沟槽、一同心圆型沟槽或一不规则型沟槽。根据本发明实施例，开孔132a是直接形成在镶嵌金属盘112正上方，并且仅形成在电容形成区域CR内。
如图4所示，接着进行一电镀工艺，例如，自对准电镀(self-alignment plating，SAP)，于开孔132a内形成三维金属结构140。根据本发明实施例，三维金属结构140包含铜，但不限于此。根据本发明实施例，三维金属结构140具有一冠状剖面结构，但不限于此。根据本发明实施例，三维金属结构140不会形成在光刻胶层132的一上表面。借由调整电镀工艺的参数，可以将三维金属结构140位于镶嵌金属盘112的上表面112a以上的高度控制在开孔132a深度的70％～100％之间。
如图5所示，在形成三维金属结构140之后，接着将光刻胶层132去除，以显露出三维金属结构140的侧壁。根据定义于光刻胶层132的开孔132a的图案，三维金属结构140可以是一导孔型结构、一线型结构、一波浪型结构、一同心圆型结构或一不规则型结构。在移除光刻胶层132之后，未被三维金属结构140覆盖的晶种层130可以被蚀除，显露出部分镶嵌金属盘112的上表面112a、镶嵌金属导线114的上表面114a及介电层110的上表面110a。
此时，三维金属结构140凸出镶嵌金属盘112的上表面112a。根据本发明实施例，三维金属结构140及镶嵌金属盘112共同构成一金属隔离金属电容的下电极210。
如图6所示，接着于衬底100上沉积一介电层150，覆盖三维金属结构140、镶嵌金属盘112的上表面112a、镶嵌金属导线114的上表面114a及介电层110的上表面110a。介电层150可以包含一金属层间介电层，例如氧化硅、氮化硅、氮氧化硅、硼磷硅玻璃、磷硅玻璃、低介电常数材料，但不限于此。后续，可以进行一化学机械抛光工艺，平坦化介电层150，直到三维金属结构140的上表面显露出来。
如图7所示，接着于介电层150上形成一光刻胶层160。光刻胶层160包含一开孔160a，位于电容形成区域CR内。开孔160a显露出三维金属结构140的上表面及部分的介电层150。接着，进行一蚀刻工艺，例如干蚀刻，经由开孔160a蚀刻掉显露出来的介电层150，在三维金属结构140的侧壁间形成凹陷结构162。接着将光刻胶层160去除。剩余的介电层150覆盖镶嵌金属盘112的上表面112a的一外围区域。
如图8所示，接着于三维金属结构140上及凹陷结构162内顺形的沉积一电容介电层220。电容介电层220也会沉积在介电层150上。根据本发明实施例，电容介电层220可以利用化学气相沉积法、原子层沉积法或任何合适的方法形成。根据本发明实施例，电容介电层220不会全部填满凹陷结构162。
根据本发明实施例，电容介电层220可以是一高介电常数材料，其介电常数高于二氧化硅。例如，上述高介电常数材料可以包括，但不限于，HfO2、ZrO2、La2O3、Al2O3、TiO2、SrTiO3、LaAlO3、Y2O3、HfOxNy、ZrOxNy、La2OxNy、Al2OxNy、TiOxNy、SrTiOxNy、LaAlOxNy、Y2OxNy、SiON、SiNX、硅玻璃或合金。
接着，于电容形成区域CR内的电容介电层220上形成一上电极230。上电极230完全填满凹陷结构162的剩余空间，如此形成与三维金属结构140指叉互合的鳍状结构230a。透过电容介电层220，上电极130电容耦合至下电极210。
上电极130可以利用如先前所述与形成三维金属结构140相同或类似的方法来制造。例如，先全面沉积一晶种层(图未示)，再于晶种层上形成一光刻胶层，接着进行自对准电镀工艺。移除光刻胶层后，多余的晶种层可以被去除。
如图9所示，接着于电容介电层220上全面沉积一介电层170。介电层170覆盖上电极230及电容介电层220。接着，利用铜镶嵌工艺于介电层170中形成镶嵌金属内联机412及414。镶嵌金属内联机412形成在电容形成区域CR内，且可以包括一导孔422，电连接至上电极230。镶嵌金属内联机414可包括一导孔424，电连接至镶嵌金属导线114。导孔424贯穿电容介电层220及介电层150。
以上所述仅为本发明的优选实施例而已，并不用于限制本发明，对于本领域的技术人员来说，本发明可以有各种更改和变化。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。
Claims (10)
1.一种金属隔离金属电容，其特征在于，包含：
一衬底，其上设有一第一介电层；
一下电极，埋设于所述第一介电层中，所述下电极包含一金属盘及凸出于所述金属盘一上表面的一三维金属结构；
一第二介电层，围绕所述三维金属结构；
一电容介电层，覆盖所述三维金属结构及所述第二介电层；以及
一上电极，设于所述电容介电层上，所述上电极包含与所述三维金属结构指叉互合的鳍状结构。
2.根据权利要求1所述的金属隔离金属电容，其特征在于，所述金属盘是一镶嵌金属盘。
3.根据权利要求1所述的金属隔离金属电容，其特征在于，所述第二介电层覆盖所述金属盘所述上表面的一外围区域。
4.根据权利要求1所述的金属隔离金属电容，其特征在于，另包含一第三介电层，覆盖所述上电极及所述电容介电层。
5.根据权利要求4所述的金属隔离金属电容，其特征在于，另包含一镶嵌金属内联机，埋设于所述第三介电层中，且与所述上电极电连接。
6.根据权利要求1所述的金属隔离金属电容，其特征在于，所述三维金属结构包含一导孔型结构、一线型结构、一波浪型结构、一同心圆型结构或一不规则型结构。
7.根据权利要求1所述的金属隔离金属电容，其特征在于，所述金属盘包含铜。
8.根据权利要求1所述的金属隔离金属电容，其特征在于，所述三维金属结构包含铜。
9.根据权利要求1所述的金属隔离金属电容，其特征在于，所述上电极包含铜。
10.根据权利要求1所述的金属隔离金属电容，其特征在于，另包含一晶种层，介于所述三维金属结构及所述金属盘之间。
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| US15/396,828 | 2017-01-03 | ||
| US15/396,828 US20180190761A1 (en) | 2017-01-03 | 2017-01-03 | Mim capacitor with enhanced capacitance |
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| US10651053B2 (en) * | 2017-11-22 | 2020-05-12 | Taiwan Semiconductor Manufacturing Co., Ltd. | Embedded metal insulator metal structure |
| US10546915B2 (en) * | 2017-12-26 | 2020-01-28 | International Business Machines Corporation | Buried MIM capacitor structure with landing pads |
| US10832944B2 (en) * | 2018-11-01 | 2020-11-10 | Globalfoundries Inc. | Interconnect structure having reduced resistance variation and method of forming same |
| TWI696268B (zh) * | 2019-01-04 | 2020-06-11 | 力晶積成電子製造股份有限公司 | 靜態隨機存取記憶體及其製作方法 |
| US11563079B2 (en) * | 2020-01-08 | 2023-01-24 | Taiwan Semiconductor Manufacturing Company Ltd. | Metal insulator metal (MIM) structure and manufacturing method thereof |
| TWI737258B (zh) | 2020-04-13 | 2021-08-21 | 力晶積成電子製造股份有限公司 | 半導體結構及其製造方法 |
| KR20220159521A (ko) | 2021-05-25 | 2022-12-05 | 삼성전자주식회사 | 금속-절연체-금속 커패시터 |
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| US20180190761A1 (en) | 2018-07-05 |
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