CN108231557A - 在半导体器件中形成复合中心 - Google Patents

在半导体器件中形成复合中心 Download PDF

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Publication number
CN108231557A
CN108231557A CN201711403503.3A CN201711403503A CN108231557A CN 108231557 A CN108231557 A CN 108231557A CN 201711403503 A CN201711403503 A CN 201711403503A CN 108231557 A CN108231557 A CN 108231557A
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China
Prior art keywords
semiconductor body
layer
region
contact hole
complex centre
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CN201711403503.3A
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CN108231557B (zh
Inventor
A.宾特
O.布兰克
P.菲舍尔
W.扬切
R.K.约希
K.佩科尔
M.皮潘
A.里格勒
W.舒施特雷德
J.施泰因布伦纳
W.M.塞德
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Infineon Technologies Austria AG
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Infineon Technologies Austria AG
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Abstract

本发明公开了在半导体器件中形成复合中心。公开的是一种方法。所述方法包括：经由形成在半导体主体的顶部上的绝缘层中的至少一个接触孔把复合中心粒子注入到半导体主体中；在所述至少一个接触孔中形成电气连接到半导体主体的接触电极；以及对半导体主体进行退火以使复合中心粒子在半导体主体中扩散。形成接触电极包括在半导体主体的在所述至少一个接触孔中暴露的区段上形成屏障层，其中所述屏障层被配置成阻止复合中心粒子扩散到半导体主体之外。

Description

在半导体器件中形成复合中心
技术领域
本公开内容总体上涉及一种在功率半导体器件中形成复合中心的方法。
背景技术
诸如功率MOSFET（金属氧化物场效应晶体管）、功率IGBT（绝缘栅双极型晶体管）、功率二极管或功率晶闸管之类的功率半导体器件被广泛地使用在工业、汽车、家庭或消费电子应用中。功率半导体器件包括主要限定半导体器件的电压阻断能力的漂移区（其也可以被称作基极区）。功率半导体器件可以被操作在双极型导通模式下，其中在漂移区中存在具有一种类型的电荷载流子（电子或空穴）和互补类型的电荷载流子的电荷载流子等离子体。例如当由漂移区和邻接的主体区形成的内部主体二极管被正向偏置并且导通时，MOSFET处于双极型导通状态。当器件从双极型导通状态改变到阻断状态时，所述电荷载流子等离子体被移除。移除该电荷载流子等离子体所花费的持续时间（即，器件从双极型导通状态改变到阻断状态所花费的持续时间）依赖于形成等离子体的电荷载流子的浓度。
通过在漂移区中形成复合中心可以调节电荷载流子浓度，并且从而调节半导体器件在从双极型导通状态改变到阻断状态时的特性。这些复合中心促进漂移中的电子和空穴的复合，并且因此帮助调节等离子体浓度。形成复合中心可以包括在半导体器件的制造过程期间把复合中心原子（诸如铂原子）引入到漂移区中。然而，这些复合中心原子当中的一些可能在后续处理期间扩散到半导体主体之外，并且可能污染处理设备。
因此需要在半导体器件中产生复合中心，同时降低处理设备的污染风险。
发明内容
一个示例涉及一种方法。所述方法包括：经由形成在半导体主体的顶部上的绝缘层中的至少一个接触孔把复合中心粒子注入到半导体主体中；在所述至少一个接触孔中形成电气连接到半导体主体的接触电极；以及对半导体主体进行退火以使复合中心粒子在半导体主体中扩散。形成接触电极包括在半导体主体的在所述至少一个接触孔中暴露的区段上形成屏障层，其中所述屏障层被配置成阻止复合中心粒子扩散到半导体主体之外。
附图说明
下面参照附图解释示例。附图用来说明某些原理，因此仅图示对于理解这些原理所必要的方面。附图并非按比例的。在附图中，相同的参考符号表示相似的特征。
图1A到1D示出用于在半导体主体中形成复合中心的方法的一个示例；
图2A到2B图示在图1A到1B中图示的方法的修改；
图3A到3B图示在图1A到1D中图示的方法的另一修改；
图4A到4B图示在图1A到1D中图示的方法的又另一修改；
图5图示包括复合中心和接触电极的二极管的一个区段的垂直横截面视图；
图6图示包括复合中心和接触电极的MOSFET的一个区段的垂直横截面视图；
图7图示包括复合中心和接触电极的IGBT的一个区段的垂直横截面视图；
图8A到8B图示图6中图示的类型的MOSFET的不同截平面中的水平横截面视图；
图9A到9E图示用于在形成复合中心之前产生晶体管单元的有源器件区和栅极电极的方法的一个示例；以及
图10图示边缘区中的晶体管器件的一个区段的垂直横截面视图。
具体实施方式
在下面的详细描述中参照附图。附图形成描述的一部分，并且通过说明的方式示出可以在其中实践本发明的具体实施例。应当理解的是，除非具体地另行指出，否则本文中所描述的各个实施例的特征可以彼此组合。
图1A到1D图示用于在半导体主体100中形成复合中心并且用于形成电气连接到半导体主体100的接触插塞30的方法的一个示例。图1A到1D当中的每一幅示出半导体主体100的一个区段的垂直横截面视图。半导体主体100具有第一表面101。图1A到1D当中的每一幅示出垂直于第一表面101的截平面中的半导体主体100。半导体主体100可以包括常规半导体材料，诸如硅（Si）、碳化硅（SiC）、砷化镓（GaAs）、氮化镓（GaN）等等。
参照图1A，半导体主体100是半导体布置的部分，所述半导体布置，除了半导体主体100之外，还包括第一表面101的顶部上的绝缘层20。绝缘层20包括诸如氧化物、氮化物等的电气绝缘材料。根据一个示例，绝缘层20仅包括一种类型的材料，诸如氧化物或氮化物。根据另一个示例（在图1A到1D中未明确示出），绝缘层20包括具有不同类型材料的至少两个层的层堆叠。诸如晶体管器件的栅极电极之类的导体（在图1A到1D中未示出）可以被嵌入在绝缘层20中。下面进一步参照本文中的示例对此进行解释。
参照图1A，绝缘层20包括接触孔（接触开口）21。在图1A所示出的示例中，该接触孔21向下延伸到半导体主体100的第一表面101，使得在接触孔21的底部暴露半导体主体100的第一表面101的区段。在半导体主体100中形成复合中心包括经由接触孔21把复合中心粒子注入到半导体主体100中。在图1A中示意性地图示并且用参考符号11标示半导体主体100中的在其中所注入的复合中心粒子静止下来的区。该区可以被称作注入的范围末端区。范围末端区11与第一表面101间隔开多远依赖于在所述方法中使用的注入能量和复合中心粒子的类型。复合中心粒子的示例包括但不限于从以下化学元素当中选择的原子或离子：铂（Pt）、金（Au）、钯（Pd）、铱（Ir）、银（Ag）、铜（Cu）、汞（Hg）或铼（Re）。当然，可以注入这些不同化学元素当中的多于一种的原子。
在第一表面101的由绝缘层20覆盖的区段中，绝缘层20基本上防止复合中心粒子被注入到半导体主体100中。
参照图1B，形成所述接触插塞（其也可以被称作接触电极）包括至少在半导体主体100的被绝缘层20暴露的那些区上形成导电屏障层31。屏障层31被配置成阻止或者尽可能地阻止复合中心粒子经由第一表面101扩散到半导体主体100之外。根据一个示例，屏障层31不仅被形成在第一表面101上，而且还至少在接触孔21的侧壁上覆盖绝缘层20。在图1B所示出的示例中，屏障层31在接触孔21的底部、接触孔21的侧壁以及绝缘层20的与半导体主体100的第一表面101相对的表面处覆盖半导体主体100。
根据一个示例，所述屏障层仅包括一种类型的材料。这种类型的材料的示例包括但不限于：钛（Ti）、氮化钛（TiN）、钽（Ta）、氮化钽（TaN）、钛钨合金（TiW）、氮化钛钨（titanium tungsten nitride，TiWN）。根据另一个示例，屏障层31包括具有不同类型材料的两个或更多子层的层堆叠。根据一个示例，屏障层31包括诸如Ti层、Ta层或TiW层之类的金属层作为被形成为与半导体主体100和绝缘层20直接接触的第一子层，以及诸如TiN层或TaN层之类的氮化物层作为形成在所述金属层上的第二子层。根据一个示例，形成所述层堆叠的金属层和氮化物层二者包括沉积工艺。本文中所使用的沉积工艺可以是诸如溅射沉积工艺之类的物理沉积工艺或者诸如化学气相沉积（CVD）工艺之类的化学沉积工艺。根据另一个示例，形成所述层堆叠包括通过沉积工艺形成金属层并且在含氮气氛（诸如，含气态氨（NH3）的气氛）中对金属层进行退火，使得金属层的区段被变换成氮化物层。200°C，Wolfram450°C，AlCu 350°C，Pt-Diffusion ab 700-750°C。
参照图1C，所述方法还包括对半导体主体100进行退火，以使得所注入的复合中心粒子在半导体主体100中扩散。在扩散工艺之后，复合中心粒子遍及半导体主体100分布，在那里它们形成复合中心。这些复合中心在图1C中通过圆圈示意性地图示。根据一个示例，所述退火工艺是快速热退火（RTA）工艺。该退火工艺中的温度可以从700°C与1200°C之间、特别是900°C与1100°C之间的范围选择，并且该退火工艺的持续时间可以从30秒与几分钟之间、特别是30秒与2分钟之间的范围选择。在RTA工艺中，可以使用灯或激光对半导体主体100进行加热。根据另一个示例，所述退火工艺是熔炉工艺，使得在退火工艺期间将半导体主体放置在熔炉中。该退火工艺中的温度可以从750°C与950°C之间、特别是800°C与900°C之间的范围选择，并且该退火工艺的持续时间可以从2分钟与90分钟之间、特别是5分钟与60分钟之间的范围选择。
屏障层31防止复合中心粒子经由包括屏障层31和接触层32的接触电极30扩散到半导体主体100之外。
参照图1D，形成接触电极30还包括在屏障层31上形成导电材料的电极层32。根据一个示例，电极层31包括以下各项中的至少一项：钨（W）层、铝（Al）层、铜（Cu）层、铝铜合金（AlCu）层、多晶硅（Si）层、或者铝硅铜合金（AlSiCu）层。根据另一个示例，形成电极层32包括在屏障层31上一个在另一个上面地形成至少两个子层。根据一个示例（在图1D中用虚线图示），形成电极层32包括在屏障层31上形成第一子层321并且在第一子层321上形成第二子层322。根据一个示例，第一子层321包括钨（W）或多晶硅（Si），并且第二子层包括铜（Cu）、铝铜合金（AlCu）或铝硅铜合金（AlSiCu）之一。然而，这仅仅是一个示例。也可以使用其他类型的子层以及多于两个子层。形成第一子层321和第二子层322当中的每一个可以包括物理或化学沉积工艺。
在参照图1A到1D解释的示例中，退火工艺在形成了屏障层31之后但是在形成电极层32之前发生。例如如果电极层32不耐受在退火工艺中使用的温度，则可以使用该工艺顺序。然而如果电极层32被配置成耐受退火工艺中的温度，则可以在形成了电极层32之后执行退火工艺。
根据又另一个示例（未示出），在形成屏障层31之前执行退火工艺。在这种情况下，可以在半导体主体100的在接触孔21中暴露的那些区段上形成氧化物层，其中所述氧化物层防止复合中心粒子在退火工艺期间扩散到半导体主体100之外。根据一个示例，所述氧化物层是沉积层，诸如基于TEOS（正硅酸乙酯）的层，并且退火在诸如含氮气氛之类的惰性气氛中发生。根据另一个示例，退火在氧化（含氧）气氛中发生使得所述氧化物层在退火工艺的开始时形成。
图2A和2B图示参照图1A到1D解释的方法的修改。参照图2A，该方法包括在半导体主体100的第一表面101中形成接触孔110。该接触孔110邻接绝缘层20中的接触孔21。根据一个示例，半导体主体100中的接触孔110通过蚀刻工艺形成，所述蚀刻工艺使用绝缘层20作为蚀刻掩模。在该工艺中，在未被绝缘层20覆盖的那些区中（也就是说，在接触孔21的底部）对半导体主体100进行蚀刻。图2A图示注入复合中心粒子之后的半导体主体100。根据一个示例，半导体主体100中的接触孔110在复合中心粒子已被注入到范围末端区11中之后形成。根据另一个示例，半导体主体100中的接触孔110在注入复合中心粒子之前形成。在该示例中，复合中心粒子经由绝缘层20中的接触孔和半导体主体100中的接触孔110被注入到半导体主体100中。
图2B示出在使复合中心粒子扩散并且形成具有屏障层31和电极层32的接触电极30之后的布置。在该示例中，接触电极30，在半导体主体100上的先前的接触孔110中，延伸到半导体主体100中，并且在接触孔110的底部和侧壁处电气连接到半导体主体100。
图3A到3B图示参照图1A到1D解释的方法的另一修改。参照图3A，这种方法包括在注入复合中心粒子之前至少在绝缘层20上形成牺牲层51。根据一个示例，牺牲层51是通过沉积工艺形成的氧化物层。在注入工艺中，复合中心粒子不仅经由接触孔21被注入到半导体主体100中，而且复合中心粒子还在绝缘层20的顶部上被注入到牺牲层51中。在注入工艺之后至少部分地移除牺牲层51。移除牺牲层51可以包括蚀刻工艺。
在注入工艺之后至少部分地移除牺牲层51还移除已被注入到牺牲层51中的复合中心粒子。这减少半导体主体100之外的复合中心粒子的数量，并且从而降低了被半导体主体100之外的这些复合中心粒子污染的风险。根据一个示例，移除牺牲层的工艺被控制成使得它完全移除牺牲层并且还移除绝缘层20的最上方区段。通过这种方式，可能通过牺牲层51被注入到绝缘层20的上方区段中的复合中心粒子也被移除。根据一个示例，这一工艺是蚀刻工艺。
根据在图3A中用虚线图示的一个示例，牺牲层51不仅被形成在绝缘层20上，而且还被形成在半导体主体100的在接触孔21中的第一表面101上。在该示例中，复合中心通过牺牲层被注入到半导体主体100的第一表面101中。根据一个示例，牺牲层51被形成为在绝缘层51上比在接触孔21中更厚，以便广泛地避免复合中心粒子通过牺牲层51被注入到绝缘层20中。作为使得牺牲层51在绝缘层20的顶部上更厚的替换或补充，在移除牺牲层51时移除绝缘层20的最上方层，以便至少部分地移除可能已被注入到绝缘层20中的复合中心粒子。
图3B示出移除牺牲层51之后的半导体布置。根据一个示例（如示出的），在退火工艺之前移除牺牲层51。根据另一个示例（未示出），在退火工艺之后移除牺牲层51。根据一个示例，在移除牺牲层51之后在半导体主体100中形成接触孔110。该接触孔110在图3B中用虚线图示。根据另一个示例（未示出），在形成牺牲层51并且注入复合中心粒子之前形成接触孔110。
图4A和4B示出参照图1A到1D解释的方法的另一修改。参照图4A，该方法还包括在接触孔21之外的绝缘层20的顶部上形成注入掩模52。根据一个示例，注入掩模52包括光致抗蚀剂，诸如负性光致抗蚀剂。该注入掩模52被配置成防止复合中心粒子被注入到绝缘层20的由注入掩模52覆盖的那些区中。该注入掩模52在注入工艺之后被移除。图4B图示注入工艺之后以及移除了注入掩模52之后的布置。注入掩模52可以在退火工艺之前被移除，如图4A和4B中所示出的那样。如前面所解释的那样，接触孔110可以在注入工艺之后被形成在半导体主体100中。在图4B中用虚线图示在注入工艺之后形成这样的接触孔110。根据另一个示例（未示出），接触孔110在注入工艺之前形成。
参照图4A，作为对牺牲层51的补充可以形成注入掩模52，而牺牲层51可以至少覆盖接触孔21的未被注入掩模52覆盖的侧壁。
可以使用以上解释的方法中的任一种来在各种类型的半导体器件中生成复合中心并且产生接触电极。下面参照图5到7来解释根据之前所解释的方法中的一种在其中形成了复合中心和接触电极30的不同类型的半导体器件。这些附图当中的每一幅示出半导体器件的一个区段的垂直横截面视图。这些半导体器件当中的每一个包括半导体主体100中的有源器件区，其中这些有源器件区当中的至少一个电气连接到接触电极30。未在以上解释的示例中图示的有源器件区可以在注入复合中心粒子之前被形成在半导体主体100中。
图5示出二极管。该二极管包括第一掺杂类型（导电类型）的基极区61以及与第一掺杂类型互补的第二掺杂类型的第一发射极区62。第一发射极区62邻接基极区61并且与基极区61形成pn结。接触电极30电气连接到第一发射极区62。所述二极管还包括与基极区61相同掺杂类型但是比基极区61更高度掺杂的第二发射极区63。第二发射极区63与第一发射极区62间隔开，并且通过基极区61与第一发射极区62分离。在图5中示出的示例中，第二发射极区63在半导体主体100的垂直方向上与第一发射极区62间隔开，所述垂直方向是垂直于第一表面101的方向。根据一个示例，基极区61是n型区，第一发射极区62是p型区，并且第二发射极区63是n型区。在该示例中，接触电极30形成阳极或者连接到二极管的阳极A，并且第二发射极区63连接到阴极K（这在图5中仅被示意性地图示）。
图6示出晶体管器件的一个示例。所述晶体管器件被实施成MOSFET。半导体主体100中的MOSFET的有源器件区包括第一掺杂类型的漂移区71、第二掺杂类型的主体区72、第一掺杂类型的源极区73以及第一掺杂类型的漏极区74。主体区72邻接漂移区71并且与漂移区71形成pn结。源极区73通过主体区72与漂移区71分离。漏极区74与源极区73和主体72间隔开，并且通过漂移区71与主体区72分离。在图6所示出的示例中，漏极区74在半导体主体100的垂直方向上与源极区73间隔开。
在该晶体管器件中，接触电极30形成MOSFET的源极电极，并且电气连接到源极区73和主体区72二者。可选地，主体区72包括第二掺杂类型的接触区72’。该接触区72’邻接接触电极30，并且具有足够高以在接触电极30与接触区72’之间形成欧姆接触的掺杂浓度。漏极区74连接到漏极节点D（这在图6中仅仅被示意性地图示）。
参照图6，MOSFET还包括栅极电极81。栅极电极81邻近主体区72，并且通过栅极电介质82与主体区72、源极区73和漂移区71介电绝缘。在该示例中，栅极电极81被布置在第一表面101的顶部上。栅极电极81被嵌入在绝缘层20中（由绝缘层20覆盖）并且电气连接到栅极节点G（这在图6中仅仅被示意性地图示）。可选地，MOSFET还包括第二掺杂类型的补偿区75。在该示例中，该补偿区75邻接主体区72和漂移区71并且被布置在主体区72与漏极区74之间。
图7示出晶体管器件的另一个示例。图7中示出的晶体管器件被实施成IGBT。该IGBT与图6中示出的MOSFET的不同之处在于：漏极区76，其也可以被称作集电极区，具有与漂移区71的掺杂类型互补的第二掺杂。可选地，第一掺杂类型的一个多个发射极短区77穿过漏极区76延伸到漂移区71或者延伸到漂移区71中，并且连接到漏极节点D。包括那些发射极短区77的IGBT可以被称作反向导通（RC）IGBT。没有那些发射极短区77的IGBT可以被称作反向阻断（RB）IGBT。参照图6中示出的MOSFET解释过的别的一切相应地适用于图7中示出的IGBT。
参照图5到7解释的半导体器件中的每一个可以被操作在双极型导通模式下。当在阳极A与阴极K之间施加电压以使第一发射极区62与基极区61之间的pn结正向偏置时，图5中示出的二极管处于双极型导通模式。在该双极型导通模式下，具有第一类型电荷载流子和第二类型电荷载流子的电荷载流子等离子体形成在基极区61中。该电荷载流子等离子体的浓度依赖于基极区61中的电荷载流子的复合速率，其中该复合速率可能受到形成在半导体主体100中的复合中心的影响。
当在漏极节点D与源极节点S之间施加电压使得主体区72与漂移区71之间的pn结被正向偏置时，图6中示出的MOSFET处于双极型导通模式。由主体区72和漂移区71形成的双极型二极管也被称作主体二极管。当在漏极节点D与源极节点S之间施加电压以使漏极区76与漂移71之间的pn结反向偏置时，并且当在栅极节点G与源极节点S之间施加电压以使在源极区73与漂移区71之间的主体区72中生成导电沟道时，图7中示出的IGBT处于双极型导通模式。
图6和7仅仅分别示出MOSFET和IGBT的一个区段。这些晶体管器件当中的每一个可以包括多个晶体管单元，其中每一个晶体管单元包括源极区73、主体区72、栅极电极81和栅极电介质82、漂移区71以及漏极区74或76。所述多个晶体管单元可以共享漂移区71和漏极区74并且连接到漏极节点D。两个或更多晶体管单元可以共享一个主体区72。所述多个晶体管单元的源极区73连接到源极节点S，并且所述多个晶体管单元的栅极电极81连接到栅极节点G，使得各个晶体管单元并联连接。
根据一个示例，各个晶体管单元的主体区72和源极区73在垂直于图6和7中示出的截平面的方向上伸长。这在图8A中图示，图8A示出图6中所示类型的并且具有多个细长的主体和源极区72、73的MOSFET的水平横截面视图。图8B示出切穿栅极电极81的截平面B-B中的该晶体管器件的水平横截面视图。参照图8A和8B，沿着一个细长主体区73可以存在延伸到该主体区73中的多个接触孔。在该示例（如图8B中所示）中，栅极电极81是一个平面电极，其包括多个开口，在其中接触电极30的插塞穿过栅极电极81延伸到主体区73中，而这些接触插塞通过绝缘层20的区段与栅极电极81介电绝缘。那些插塞可以如在图8A和8B中的左侧示出的那样是点状的，或者如在图8A和8B中的右侧示出的那样是细长的。
图9A到9E图示可以被用来在注入复合中心粒子之前形成主体区72、源极区73和可选的接触区72’以及具有嵌入的栅极电极81的绝缘层20的工艺顺序。图9A到9E当中的每一幅图示半导体主体100的一个区段的垂直横截面视图。参照前文，半导体主体100可以包括多个主体区72和可选的补偿区75。然而，在图9A到9E中示出仅一个主体区72和仅一个可选的补偿区75。主体区72和可选的补偿区75可以在形成栅极电介质82之前被形成在半导体主体100中。形成主体区72可以包括注入工艺，其中掺杂剂粒子（掺杂剂原子）经由第一表面101被注入到半导体主体100中。根据一个示例，在多外延工艺中形成包括漂移区71、可选的补偿区75和主体区72的半导体主体100的层。在这种类型的工艺中，在衬底上一个在另一个上面地生长多个外延层（其可以形成完成的器件中的漏极区74、76），并且将掺杂剂原子注入到各个外延层中。在退火工艺中，所注入的掺杂剂原子被激活。
图9A示出在半导体主体100中形成漂移区71、主体区72和可选的补偿区75之后并且在半导体主体100的第一表面101上形成栅极电介质82以及在栅极电介质82上形成栅极电极81之后的半导体布置。根据一个示例，栅极电介质82是氧化物。根据一个示例，所述氧化物是在热氧化工艺中在第一表面101上生长的热氧化物。栅极电极81例如是金属或者高度掺杂的多晶半导体材料（诸如多晶硅）。栅极电极81可以在物理或化学沉积工艺中被形成在栅极电介质82上。
参照图9B，栅极电极81和栅极电介质82被图案化。“图案化”栅极电极81和栅极电介质82包括在栅极电极81和栅极电介质82中在主体区72上方形成至少一个接触孔。这可以包括蚀刻工艺，所述蚀刻工艺对未被形成在栅极电极81的顶部上的蚀刻掩模201覆盖的那些区中的栅极电极81和栅极电介质82进行蚀刻。
参照图9C，使用栅极电极81和栅极电介质82作为注入掩模将掺杂剂原子注入到主体区72中。也就是说，掺杂剂原子仅被注入到主体区72的未被栅极电极81和栅极电介质82覆盖的那些区中。在此工艺中注入的掺杂剂原子形成源极区73。在图9C中，源极区72被绘制成已被完全形成。然而，这仅仅是一个示例。除了注入掺杂剂原子之外，形成源极区73还包括退火工艺，其中使所注入的掺杂剂原子扩散并且电气激活。这一退火工艺不一定在注入工艺之后直接执行。替代地，可以存在一个共同的退火工艺，其使被注入以形成源极区73的掺杂剂原子扩散并且激活，而且还使被注入以形成其他器件区（诸如接触区72’）的其他掺杂剂原子扩散并且激活。可选地，在注入工艺之前，在半导体主体100的栅极电极81和第一表面101上形成保护层24。掺杂剂原子穿过所述保护层被注入到主体区72中。该保护层24在退火工艺中保护栅极电极81。根据一个示例，所述保护层是沉积的氧化物层。
参照图9D，所述方法还包括在通过栅极电极81和栅极电介质82形成的接触孔的侧壁上形成间隔物22。通过使用栅极电极81和该间隔物22作为注入掩模，与主体区72相同掺杂类型的掺杂剂原子被注入到半导体主体100中。这些掺杂剂原子在图9C的上下文中解释的退火工艺之后形成可选的接触区72’。可选地，在形成间隔物22之后，不仅注入形成接触区72’的掺杂剂原子，而且还注入形成源极区73的附加的掺杂剂原子。
形成间隔物22可以包括遍及栅极电极81以及第一表面101的被暴露的区段沉积间隔物层，以及各向异性地蚀刻该间隔物层使得间隔物22保留。根据一个示例，所述间隔物层是氧化物层。形成该氧化物层可以包括沉积工艺。
参照图9E，在栅极电极81的顶部上形成绝缘层23。该绝缘层23、间隔物22和可选的散射层24一起形成绝缘层20。此外，在绝缘层20中形成之前所解释的接触孔21。形成接触孔21可以包括使用形成在绝缘层20的顶部上的蚀刻掩模203进行的蚀刻工艺。
参照前文，诸如参照图6所解释的MOSFET或者参照图7所解释的IGBT之类的晶体管器件可以包括多个晶体管单元，每一个晶体管单元包括主体区72、源极区73和可选的接触区72’。参照图10，其示出包括晶体管器件的半导体布置的一个区段的水平横截面视图，这些晶体管单元被布置在半导体主体100的内部区中。内部区120，在图10中未示出的水平平面中，被边缘区130围绕，而所述边缘区是半导体主体100的内部区120与边缘表面103之间的区。图10示出边缘区130和内部区120的一个区段。
边缘区130可以包括边缘终止结构。参照图10，所述边缘终止结构可以包括第一场环91，其被布置在绝缘层20上、与第一表面101间隔开并且通过电气连接过孔93电气连接到栅极电极81。所述边缘终止结构还可以包括第二场环92，其处于绝缘层20上方、与第一表面101间隔开并且通过过孔94和可选的接触区95电气连接到漂移区71，所述可选的接触区95具有与漂移区71相同的掺杂类型但是更高度掺杂。所述边缘区还可以包括经修改的晶体管单元，其包括主体区72和可选的接触区72’但是其不包括源极区。该经修改的晶体管单元的主体区还连接到源极电极30。
参照前文，注入复合中心粒子可以包括在注入复合中心粒子之前在绝缘层20的顶部上形成注入掩模（图4A中的52）。参照图4A，该注入掩模52可以靠近接触孔21被形成在绝缘层20上，使得在具有多个接触孔21的器件中，掩模层52的区段被布置在接触孔21之间的绝缘层20的顶部上。根据一个示例，所述掩模还被形成在图10中示出的边缘区130上方的绝缘层20上，以便防止复合中心粒子被注入到边缘区130中。所述注入掩模可以被形成为使得复合中心粒子被注入或者使得复合中心粒子不被注入到以上解释的经修改的晶体管单元的接触孔中。
根据一个示例，所述注入掩模被形成为使其覆盖（未经修改的）晶体管单元的多个接触孔当中的一些，以便复合中心粒子不被注入到每一个接触孔中。根据一个示例，被注入掩模覆盖的那些接触孔定位得靠近边缘区130。
图10中示出的场电极91、92可以在其中形成接触电极30的相同工艺中被形成，使得当复合中心粒子被注入时（也就是说，当在绝缘层20上形成可选的掩模层52以防止复合中心粒子被注入时）这些场电极91、92还未被形成。

Claims (20)

1.一种方法，包括：
经由形成在半导体主体的顶部上的绝缘层中的至少一个接触孔把复合中心粒子注入到半导体主体中；
在所述至少一个接触孔中形成电气连接到半导体主体的接触电极；以及
对半导体主体进行退火以使复合中心粒子在半导体主体中扩散，
其中，形成接触电极包括在半导体主体的在所述至少一个接触孔中暴露的区段上形成屏障层，其中所述屏障层被配置成阻止复合中心粒子扩散到半导体主体之外。
2.根据权利要求1所述的方法，其中，形成接触电极还包括：
在屏障层上形成至少一个电极层。
3.根据权利要求2所述的方法，其中，所述退火在形成屏障层之后并且在形成所述至少一个电极层之前发生。
4.根据权利要求1或2所述的方法，其中，所述退火在形成屏障层之前发生。
5.根据前述权利要求中的一项所述的方法，还包括：
在注入复合中心之前至少在绝缘层上形成牺牲层；以及
在形成接触电极之前移除牺牲层。
6.根据权利要求5所述的方法，其中，形成牺牲层包括在绝缘层上并且在接触孔中的半导体主体上形成牺牲层。
7.根据权利要求5或6所述的方法，其中，所述牺牲层包括氧化物层。
8.根据前述权利要求中的一项所述的方法，还包括：
在注入复合中心粒子之前在绝缘层上形成注入掩模；以及
在注入复合中心粒子之后移除所述注入。
9.根据权利要求1到8中的一项所述的方法，
其中，所述半导体主体包括邻接绝缘层中的所述至少一个接触孔的接触孔；并且
其中，复合中心粒子被注入到半导体主体的接触孔中。
10.根据权利要求1到8中的一项所述的方法，还包括：
在注入复合中心粒子之后并且在形成接触电极之前，在半导体主体中形成邻接绝缘层中的所述至少一个接触孔的接触孔。
11.根据权利要求10所述的方法，其中，形成接触孔包括使用绝缘层作为蚀刻掩模对半导体进行蚀刻。
12.根据权利要求1到11中的一项所述的方法，其中，所述半导体主体包括：
第一掺杂类型的漂移区；
具有与第一掺杂类型互补的第二掺杂类型并且邻接漂移区的主体区；
通过主体区与漂移区分离的第一掺杂类型的源极区，
其中，形成接触电极包括形成要被连接到源极区和主体区的接触电极。
13.根据权利要求12所述的方法，其中，所述半导体主体还包括比漂移区更高度掺杂并且通过漂移区与主体区分离的第一掺杂类型的漏极区。
14.根据权利要求12所述的方法，其中，所述半导体主体还包括比漂移区更高度掺杂并且通过漂移区与主体区分离的第二掺杂类型的集电极区。
15.根据权利要求1到11中的一项所述的方法，其中，所述半导体主体包括：
第一掺杂类型的基极区；以及
与第一掺杂类型互补的第二掺杂类型的第一发射极区，并且
其中，形成接触电极包括形成要被电气连接到第一发射极区的接触电极。
16.根据前述权利要求中的一项所述的方法，
其中，所述屏障层包括至少一个层，
其中，所述至少一个层包括以下各项当中的至少一项：钛（Ti）、氮化钛（TiN）、钽（Ta）、氮化钽（TaN）、钛钨合金（TiW）、氮化钛钨（TiWN）。
17.根据权利要求2到16中的一项所述的方法，所述至少一个电极层包括从由以下各项构成的组当中选择的材料：
钨（W）；
铝铜合金（AlCu）；以及
铝硅铜合金（AlSiCu）。
18.根据权利要求1到17中的一项所述的方法，其中，对半导体主体进行退火包括RTA工艺。
19.根据权利要求1到17中的一项所述的方法，其中，对半导体主体进行退火包括熔炉工艺。
20.根据前述权利要求中的一项所述的方法，其中，所述复合中心粒子包括从由以下各项构成的组当中选择的一种或多种化学元素的原子或离子：
铂（Pt）；
金（Au）；
钯（Pd）；
铱（Ir）；
银（Ag）；
铜（Cu）；
汞（Hg）；以及
铼（Re）。
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Publication number Priority date Publication date Assignee Title
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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20080089063A (ko) * 2007-03-31 2008-10-06 주식회사 하이닉스반도체 불순물의 외확산을 억제하는 반도체소자의 제조 방법
CN102263020A (zh) * 2010-05-25 2011-11-30 科轩微电子股份有限公司 低栅极阻抗的功率半导体结构的制造方法
CN103165460A (zh) * 2011-12-16 2013-06-19 中芯国际集成电路制造(上海)有限公司 Ldnmos及ldpmos的制造方法
US20150294975A1 (en) * 2012-11-14 2015-10-15 Ps5 Luxco S.A.R.L. Semiconductor device and method of manufacturing the same
CN105580112A (zh) * 2013-09-25 2016-05-11 住友电气工业株式会社 制造碳化硅半导体器件的方法
CN106104755A (zh) * 2013-09-13 2016-11-09 离子射线服务公司 包括通过离子注入掺杂和沉积向外扩散阻挡物的用于制备太阳能电池的方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8558308B1 (en) 2012-06-14 2013-10-15 Infineon Technologies Austria Ag Method of manufacturing a semiconductor device using a contact implant and a metallic recombination element and semiconductor
US8975662B2 (en) * 2012-06-14 2015-03-10 Infineon Technologies Austria Ag Method of manufacturing a semiconductor device using an impurity source containing a metallic recombination element and semiconductor device
US9214521B2 (en) * 2012-06-21 2015-12-15 Infineon Technologies Ag Reverse conducting IGBT
US20140374882A1 (en) * 2013-06-21 2014-12-25 Infineon Technologies Austria Ag Semiconductor Device with Recombination Centers and Method of Manufacturing
JP6237902B2 (ja) * 2014-07-17 2017-11-29 富士電機株式会社 半導体装置および半導体装置の製造方法
US9209027B1 (en) * 2014-08-14 2015-12-08 Infineon Technologies Ag Adjusting the charge carrier lifetime in a bipolar semiconductor device

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20080089063A (ko) * 2007-03-31 2008-10-06 주식회사 하이닉스반도체 불순물의 외확산을 억제하는 반도체소자의 제조 방법
CN102263020A (zh) * 2010-05-25 2011-11-30 科轩微电子股份有限公司 低栅极阻抗的功率半导体结构的制造方法
CN103165460A (zh) * 2011-12-16 2013-06-19 中芯国际集成电路制造(上海)有限公司 Ldnmos及ldpmos的制造方法
US20150294975A1 (en) * 2012-11-14 2015-10-15 Ps5 Luxco S.A.R.L. Semiconductor device and method of manufacturing the same
CN106104755A (zh) * 2013-09-13 2016-11-09 离子射线服务公司 包括通过离子注入掺杂和沉积向外扩散阻挡物的用于制备太阳能电池的方法
CN105580112A (zh) * 2013-09-25 2016-05-11 住友电气工业株式会社 制造碳化硅半导体器件的方法

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
LI, HJ; BENNETT, J; ZEITZOFF, P; 等.: "Indium out-diffusion from silicon during rapid thermal annealing", 《IEEE ELECTRON DEVICE LETTERS》 *
马万里等: "沟槽型VDMOS源区的不同制作方法研究 ", 《半导体技术》 *

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