CN108198915B - LED preparation process - Google Patents
LED preparation process Download PDFInfo
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- CN108198915B CN108198915B CN201810012661.4A CN201810012661A CN108198915B CN 108198915 B CN108198915 B CN 108198915B CN 201810012661 A CN201810012661 A CN 201810012661A CN 108198915 B CN108198915 B CN 108198915B
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- 238000002360 preparation method Methods 0.000 title abstract description 6
- 230000004888 barrier function Effects 0.000 claims abstract description 96
- 229910002601 GaN Inorganic materials 0.000 claims abstract description 61
- 238000000034 method Methods 0.000 claims abstract description 25
- 230000008569 process Effects 0.000 claims abstract description 25
- 239000000758 substrate Substances 0.000 claims abstract description 24
- 238000005229 chemical vapour deposition Methods 0.000 claims abstract description 6
- 229910052751 metal Inorganic materials 0.000 claims abstract description 6
- 239000002184 metal Substances 0.000 claims abstract description 6
- 238000004519 manufacturing process Methods 0.000 claims description 16
- NWAIGJYBQQYSPW-UHFFFAOYSA-N azanylidyneindigane Chemical compound [In]#N NWAIGJYBQQYSPW-UHFFFAOYSA-N 0.000 claims description 13
- RNQKDQAVIXDKAG-UHFFFAOYSA-N aluminum gallium Chemical compound [Al].[Ga] RNQKDQAVIXDKAG-UHFFFAOYSA-N 0.000 claims description 8
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 abstract description 21
- 229910052738 indium Inorganic materials 0.000 abstract description 20
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 abstract description 12
- 238000002425 crystallisation Methods 0.000 abstract description 7
- 230000008025 crystallization Effects 0.000 abstract description 7
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 15
- 238000000151 deposition Methods 0.000 description 12
- 229910021389 graphene Inorganic materials 0.000 description 10
- 238000010438 heat treatment Methods 0.000 description 6
- 229910002704 AlGaN Inorganic materials 0.000 description 5
- 238000000407 epitaxy Methods 0.000 description 5
- FYYHWMGAXLPEAU-UHFFFAOYSA-N Magnesium Chemical compound [Mg] FYYHWMGAXLPEAU-UHFFFAOYSA-N 0.000 description 4
- 229910052799 carbon Inorganic materials 0.000 description 4
- 238000011109 contamination Methods 0.000 description 4
- 229910052749 magnesium Inorganic materials 0.000 description 4
- 239000011777 magnesium Substances 0.000 description 4
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- 239000000463 material Substances 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 238000005286 illumination Methods 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 229910052594 sapphire Inorganic materials 0.000 description 2
- 239000010980 sapphire Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 229910017083 AlN Inorganic materials 0.000 description 1
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- 239000012159 carrier gas Substances 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
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- 239000011554 ferrofluid Substances 0.000 description 1
- 229910002804 graphite Inorganic materials 0.000 description 1
- 239000010439 graphite Substances 0.000 description 1
- 238000004020 luminiscence type Methods 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 1
- 230000010287 polarization Effects 0.000 description 1
- 239000012495 reaction gas Substances 0.000 description 1
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- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- RGGPNXQUMRMPRA-UHFFFAOYSA-N triethylgallium Chemical compound CC[Ga](CC)CC RGGPNXQUMRMPRA-UHFFFAOYSA-N 0.000 description 1
- JLTRXTDYQLMHGR-UHFFFAOYSA-N trimethylaluminium Chemical compound C[Al](C)C JLTRXTDYQLMHGR-UHFFFAOYSA-N 0.000 description 1
- XCZXGTMEAKBVPV-UHFFFAOYSA-N trimethylgallium Chemical compound C[Ga](C)C XCZXGTMEAKBVPV-UHFFFAOYSA-N 0.000 description 1
- IBEFSUTVZWZJEL-UHFFFAOYSA-N trimethylindium Chemical compound C[In](C)C IBEFSUTVZWZJEL-UHFFFAOYSA-N 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
- H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
- H01L33/06—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/26—Materials of the light emitting region
- H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
- H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen
- H01L33/325—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen characterised by the doping materials
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Led Devices (AREA)
Abstract
The invention provides a preparation process of an LED, which comprises a buffer layer, an N-type GaN layer, a light-emitting layer and a P-type GaN layer which are sequentially deposited on a substrate through a metal organic chemical vapor deposition process; the substrate is arranged on a rotating wafer carrying disc, the light emitting layer comprises a quantum well layer and a quantum barrier layer which are periodically stacked, at least one of the quantum well layer and the quantum barrier layer which are periodically stacked is a high-speed quantum well layer and a low-speed quantum barrier layer, and the rotating speed of the wafer carrying disc when the high-speed quantum well layer is formed is larger than that when the low-speed quantum barrier layer is formed. According to the invention, indium is doped into gallium nitride by increasing the rotating speed, so that the doping amount of indium is prevented from being increased by reducing the growth temperature, the quantum well layer can be deposited at a higher temperature, and the obtained quantum well layer has better crystallization quality; meanwhile, the cost is low, and the implementation is easy.
Description
Technical Field
The invention relates to the technical field of illumination, in particular to a preparation process of an LED.
Background
An led (lighting emitting diode) lighting is a semiconductor solid state light emitting device. The solid semiconductor chip is used as a luminescent material, and the carriers are compounded in the semiconductor to release excess energy to cause photon emission, so that red, yellow, blue and green light is directly emitted. An illumination device manufactured by using an LED as a light source is an LED lamp.
The LED manufacturing process comprises the steps of epitaxy, a chip front section, a chip rear end, packaging and the like, wherein the epitaxy is used for depositing a buffer layer, an N-type GaN layer, a light emitting layer and a P-type GaN layer on a sapphire substrate in sequence through a metal organic chemical vapor deposition process to obtain an epitaxy structure, then the chips with different versions are obtained through the chip front section and rear end manufacturing processes, and finally different lighting appliances are manufactured through packaging.
The epitaxy, as an initial part of the whole process, has a decisive influence on the luminous efficiency of the lighting fixture. Under the action of external current, electrons generated by the N-type GaN layer and holes generated by the P-type GaN layer are recombined in the light-emitting layer to emit light, so that the light-emitting layer structure has important influence on epitaxy. The light emitting layer generally comprises a periodically stacked quantum well layer and a quantum barrier layer, the quantum well layer is formed by doping indium into a gallium nitride layer to form indium gallium nitride, the quantum barrier layer is a gallium nitride layer, the indium is difficult to dope into the gallium nitride due to the overhigh temperature, the temperature for forming the quantum well layer is generally lower than the temperature for forming the quantum barrier layer, and the temperature difference is about 60-160 ℃.
Application number CN201710388641.2 discloses an epitaxial wafer of a light emitting diode and a manufacturing method thereof, in which a graphene thin film layer is disposed between adjacent quantum well layers and quantum barrier layers, and the graphene thin film layer is used to prevent indium atoms in the quantum well layers from diffusing into the quantum barrier layers, so as to improve effective doping of indium in the quantum well layers, and prevent indium from being separated out due to higher growth temperature of the quantum well layers, thereby growing the quantum well layers at higher temperature, improving growth quality of the quantum well layers, improving interface polarization, and improving light emitting efficiency of the light emitting diode. However, in the existing stage, the graphene film layer is high in preparation cost and complex in process, and cannot be commercially produced, and meanwhile, the graphene film layer is easy to cause carbon contamination and other problems, and other alternative means are required to be found to improve the light emitting efficiency of the LED.
Disclosure of Invention
The invention aims to provide an LED preparation process, which can grow a quantum well layer at high temperature on the premise of low cost.
The technical problem to be solved by the invention is realized by adopting the following technical scheme:
An LED manufacturing process, comprising: the buffer layer, the N-type GaN layer, the light emitting layer and the P-type GaN layer are sequentially deposited on the substrate through a metal organic chemical vapor deposition process; the substrate is arranged on a rotating wafer carrying disc, the light emitting layer comprises a quantum well layer and a quantum barrier layer which are periodically stacked, at least one of the quantum well layer and the quantum barrier layer which are periodically stacked is a high-speed quantum well layer and a low-speed quantum barrier layer, and the rotating speed of the wafer carrying disc when the high-speed quantum well layer is formed is larger than that when the low-speed quantum barrier layer is formed.
optionally, the temperature for forming the high-speed quantum well layer is equal to the temperature for forming the low-speed quantum barrier layer.
Optionally, the high-speed quantum well layer and the low-speed quantum barrier layer are adjacent quantum well layers and quantum barrier layers.
Optionally, a distance between the high-speed quantum well layer and the low-speed quantum barrier layer and the P-type GaN layer is less than a distance between the high-speed quantum well layer and the low-speed quantum barrier layer and the N-type GaN layer.
optionally, an indium nitride layer is disposed between at least one of the high-speed quantum well layer and the low-speed quantum barrier layer.
Optionally, an aluminum gallium nitride layer is disposed between the indium nitride layer and the low-speed quantum barrier layer.
Optionally, the rotation speed and temperature for forming the indium nitride layer chip carrying disc are equal to the rotation speed and temperature for forming the high-speed quantum well layer chip carrying disc, and the rotation speed and temperature for forming the aluminum-gallium-nitrogen layer chip carrying disc are equal to the rotation speed and temperature for forming the low-speed quantum barrier layer chip carrying disc.
Optionally, the rotation speed of the high-speed quantum well layer chip carrying disc is 600-1200 rpm, and the rotation speed of the low-speed quantum barrier layer chip carrying disc is 100-500 rpm.
Optionally, the temperature for forming the high-speed quantum well layer is 700-1000 ℃, and the temperature for forming the low-speed quantum barrier layer is 700-1000 ℃.
Optionally, the rotation speed and the temperature for forming the high-speed quantum well layer chip carrier plate are respectively 900rpm and 850 ℃, and the rotation speed and the temperature for forming the low-speed quantum barrier layer chip carrier plate are respectively 300rpm and 850 ℃.
the invention has the beneficial effects that: the rotating speed of the slide disc when the high-speed quantum well layer is formed is larger than that of the slide disc when the low-speed quantum barrier layer is formed, more indium is doped into gallium nitride by using vortex generated by the slide disc rotating at high speed, the doping amount of the indium is prevented from being increased by reducing the growth temperature, the quantum well layer with the required wavelength can be deposited at higher temperature, the higher rotating speed is favorable for improving the crystallization quality, the crystallization quality of the obtained quantum well layer is better, and the half widths of the 002 surface and the 102 surface are smaller than that of the LED structure obtained at normal rotating speed through XRD test; the quantum well layer grows at a higher temperature, the temperature difference between the quantum well layer and the growth temperature of the quantum barrier layer is reduced, the smaller temperature difference can realize the quick switching from the growth of the quantum well layer to the growth of the quantum barrier layer on one hand, the whole process period is shortened, and on the other hand, the epitaxial warping caused by temperature fluctuation when the quantum well layer and the quantum barrier layer grow can be effectively reduced; repeated experiments prove that the indium is doped into the gallium nitride at a high rotating speed, and the content of the indium component in the obtained quantum well layer is more stable and uniform, so that the wavelength is more controllable and the uniformity is better; compared with the graphene layer, the graphene layer has the advantages that the production cost and the process complexity are greatly reduced, and the problem of carbon contamination does not exist.
Drawings
FIG. 1 is a simplified schematic diagram of an MOCVD apparatus for fabricating LEDs;
FIG. 2 is a top view of a slide tray with a substrate mounted thereon;
FIG. 3 is a schematic diagram of an LED structure;
FIG. 4 is a graph of the rotation speed and temperature during the formation of a quantum well layer and a quantum barrier layer according to the prior art;
FIG. 5 is a flow chart of a process for manufacturing an LED according to the present invention;
FIGS. 6-9 are graphs of the rotation speed and temperature when the quantum well layer and the quantum barrier layer are formed according to different embodiments in the manufacturing process provided by the present invention;
Fig. 10 and 11 are schematic diagrams of other two LED structures in the manufacturing process provided by the present invention.
Detailed Description
A more detailed description of one LED fabrication process provided by the present invention is provided below in conjunction with examples, wherein preferred embodiments of the present invention are shown, it being understood that one skilled in the art could modify the invention described herein while still achieving the advantageous effects of the present invention. Accordingly, the following description should be construed as broadly as possible to those skilled in the art and not as limiting the invention.
The invention is described in more detail in the following paragraphs by way of example with reference to the accompanying drawings. Advantages and features of the present invention will become apparent from the following description and from the claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Example one
Referring to fig. 1 and 2, when an LED is manufactured by MOCVD (Metal Organic Chemical Vapor Deposition) equipment, a substrate 110 is first placed in grooves 109 uniformly distributed on a slide plate 108, the depth of the grooves 109 is slightly greater than the thickness of the substrate 110, the size of the substrate 110 may be two inches, four inches or six inches, and the slide plate 108 is made of a high temperature resistant material, such as graphite. Then a slide tray 108 with a substrate 110 is conveyed into a reaction chamber 104, the reaction chamber 104 is a closed structure formed by an upper cover 101, a side wall 102 and a base 103, an air inlet pipe 105 is uniformly distributed on the upper cover 101, and a reaction gas, a carrier gas (NH3, N2, H2, and the like) and an MO source (trimethyl gallium, triethyl gallium, trimethyl aluminum, trimethyl indium, magnesium, and the like) enter the reaction chamber 104 through the air inlet pipe 105 to react and then deposit on the substrate 110, a heating module 107 is arranged on the base 103 and below the slide tray 108, the heating module 107 can adopt a heating wire or radio frequency heating, the slide tray 108 and the reaction chamber 104 are heated through the heating module 107, a concave central groove 112 is arranged on the back of the slide tray 108, a rotating shaft 111 penetrates through the base 103 through a ferrofluid sealing element, one end of the rotating shaft 111 in the reaction chamber 104 is in contact with the central groove 112 to jack up the slide tray 108, so that a gap is generated between the slide tray 108 and the heating module 107, the rotating shaft 111 is located at one end outside the reaction chamber 104 and is connected with a driving device (not shown in the figure), the driving device drives the slide glass tray 108 to rotate in the reaction chamber 104 through the rotating shaft 111 and controls the rotating speed of the slide glass tray 108 through a controller, and the exhaust holes 106 are arranged around the base 103 at intervals along the circumferential direction. The device realizes the control of the pressure of the reaction chamber 104 and the temperature of the slide plate 108 through PID control, and the temperatures mentioned below are the surface temperatures of the slide plate 108 and are not described again.
Referring to fig. 3, a buffer layer 2, an N-type GaN layer 3, a light emitting layer 4, and a P-type GaN layer 5 are sequentially deposited on a substrate 1 by a metal organic chemical vapor deposition process; the light emitting layer 4 includes a quantum well layer 41 and a quantum barrier layer 42 which are periodically stacked, the rotation speed and the temperature of the slide plate 108 in the prior art are shown in fig. 4 when the quantum well layer 41 and the quantum barrier layer 42 are formed (in the figure, a horizontal solid line located above represents the rotation speed, and a horizontal dotted line located below represents the temperature, which are consistent in description in subsequent corresponding figures and are not repeated), the rotation speed of the slide plate 108 is equal (usually 500rpm) when the quantum well layer 41 and the quantum barrier layer 42 are formed, and the temperature for forming the quantum well layer 41 is lower than the temperature for forming the quantum barrier layer 42 (the temperature difference is about 60-160 ℃) so that indium can be doped into the quantum well layer 41.
The core idea of the invention is that the invention provides an LED manufacturing process, as shown in fig. 5 and 3, comprising the following steps:
Step S1, providing a substrate 1 and placing the substrate on the slide disc 108;
step S2, depositing a buffer layer 2 on the substrate 1;
Step S3, depositing an N-type GaN layer 3 on the buffer layer 2;
Step S4, depositing a light emitting layer 4 on the N-type GaN layer 3;
Step S5, depositing a P-type GaN layer 5 on the light emitting layer 4;
The light emitting layer 4 includes a periodically stacked quantum well layer 41 and a quantum barrier layer 42, at least one of the periodically stacked quantum well layer 41 and the periodically stacked quantum barrier layer 42 is a high-speed quantum well layer 41H and a low-speed quantum barrier layer 42L, and the rotation speed of the chip carrier 108 when the high-speed quantum well layer 41H is formed is greater than the rotation speed of the chip carrier 108 when the low-speed quantum barrier layer 42L is formed, as shown in fig. 6.
According to the invention, the rotating speed of the slide plate disc when the high-speed quantum well layer is formed is greater than that when the quantum well layer is formed, the rotating speed of the slide plate disc when the low-speed quantum barrier layer is formed is equal to or less than that when the quantum barrier layer is formed (shown in figures 6 and 7), the rotating speed of the slide plate disc when the high-speed quantum well layer is formed is greater than that when the low-speed quantum barrier layer is formed, more indium is doped into gallium nitride by using vortex generated by the slide plate rotating at high speed, the doping amount of the indium is prevented from being increased by reducing the growth temperature, the quantum well layer with the required wavelength can be deposited at higher temperature, the higher rotating speed is favorable for improving the crystallization quality, the obtained quantum well layer has better crystallization quality, and the half widths of the 002 surface and the 102 surface are both less than that of an LED structure obtained at normal rotating speed through XRD test; the quantum well layer grows at a higher temperature, the temperature difference between the quantum well layer and the growth temperature of the quantum barrier layer is reduced, the smaller temperature difference can realize the quick switching from the growth of the quantum well layer to the growth of the quantum barrier layer on one hand, the whole process period is shortened, and on the other hand, the epitaxial warping caused by temperature fluctuation when the quantum well layer and the quantum barrier layer grow can be effectively reduced; repeated experiments prove that the indium is doped into the gallium nitride at a high rotating speed, and the content of the indium component in the obtained quantum well layer is more stable and uniform, so that the wavelength is more controllable and the uniformity is better; compared with the graphene layer, the graphene layer has the advantages that the production cost and the process complexity are greatly reduced, and the problem of carbon contamination does not exist.
In this embodiment, as shown in fig. 8, the temperature at which the high-speed quantum well layer 41H is formed is preferably equal to the temperature at which the low-speed quantum barrier layer 42L is formed, and the high-speed quantum well layer 41H and the low-speed quantum barrier layer 42L are adjacent quantum well layers and quantum barrier layers. The temperature when the high-speed quantum well layer 41H is formed is set to be equal to the temperature when the low-speed quantum barrier layer 42L is formed, so that the temperature difference between the high-speed quantum well layer 41H and the low-speed quantum barrier layer 42L can be reduced to zero, continuous deposition is realized, the process period is greatly shortened, and warping caused by the temperature difference is greatly reduced; in the prior art, different deposition rates are adopted when depositing the quantum well layer 41 and the quantum barrier layer 42, generally, the rate of depositing the quantum well layer 41 is smaller than that of the quantum barrier layer 42 (the former is about 1/2-1/4 of the latter), the different deposition rates enable larger interface energy to be generated on the contact surface of the quantum well layer 41 and the quantum barrier layer 42, the high-speed quantum well layer 41H and the low-speed quantum barrier layer 42L are arranged as the adjacent quantum well layer and the adjacent quantum barrier layer, when switching from depositing the high-speed quantum well layer 41H to depositing the low-speed quantum barrier layer 42L, the rotating speed of a slide plate is gradually reduced, the interface energy caused by part of growth rate difference is made up, the contact interface stress of the high-speed quantum well layer 41H and the low-speed quantum barrier layer 42L is small, and the dislocation.
In this embodiment, the distance between the high-speed quantum well layer 41H and the low-speed quantum barrier layer 42L and the P-type GaN layer 5 is smaller than the distance between the high-speed quantum well layer and the N-type GaN layer 3. The electron mobility generated by the N-type GaN layer 3 is higher than the hole mobility generated by the P-type GaN layer 5, the electron and hole composite luminescence in the luminescent layer 4 is mainly concentrated on the side close to the P-type GaN layer 5, and the high-speed quantum well layer 41H and the low-speed quantum barrier layer 42L are arranged on the side close to the P-type GaN layer 5, so that the luminescent efficiency is improved.
In another embodiment, as shown in fig. 9, the quantum well layer 41 and the quantum barrier layer 42 are a high-speed quantum well layer 41H and a low-speed quantum barrier layer 42L.
In another embodiment, as shown in fig. 10, an indium nitride layer 41a is provided between at least one of the high-speed quantum well layers 41H and the low-speed quantum barrier layers 42L, and the rotation speed and temperature of the chip tray 108 for forming the indium nitride layer 41a are preferably equal to the rotation speed and temperature of the chip tray 108 for forming the high-speed quantum well layers 41H. The indium nitride layer 41a can further reduce the interface energy generated at the contact interface between the high-speed quantum well layer 41H and the low-speed quantum barrier layer 42L, and can reduce the dislocation density and the defect density.
In another embodiment, as shown in fig. 11, an aluminum gallium nitride layer 42a is disposed between indium nitride layer 41a and low-speed quantum barrier layer 42L, and the rotation speed and temperature of wafer carrying plate 108 for forming aluminum gallium nitride layer 42a are preferably equal to the rotation speed and temperature of wafer carrying plate 108 for forming low-speed quantum barrier layer 42L. The aluminum gallium nitride layer 42a can reduce the mobility of electrons in the light-emitting layer 4, prevent the electrons from overflowing to the P-type GaN layer 5, and further improve the light-emitting efficiency.
Example two
the following further detailed description of the LED manufacturing process provided by the present invention is provided for clearly illustrating the contents of the present invention, and it should be understood that the contents of the present invention are not limited to the following examples, and other modifications by conventional technical means of those skilled in the art are within the scope of the idea of the present invention.
as shown in fig. 5, first, step S1 is performed to provide a substrate 1 and place it on the slide tray 108. The substrate 1 can be made of a sapphire substrate, a GaN substrate, a silicon substrate or a silicon carbide substrate, and the size of the substrate 1 is two inches, four inches or six inches.
Then, step S2 is performed to deposit a buffer layer 2 on the substrate 1. The material of the buffer layer 2 is GaN, AlN or AlGaN, the rotating speed of the slide plate 108 forming the buffer layer 2 is 400-800 rpm, the temperature is 450-650 ℃, and the thickness is 15-50 nm.
Next, step S3 is performed to deposit an N-type GaN layer 3 on the buffer layer 2. The rotating speed of the wafer carrying disc 108 for forming the N-type GaN layer 3 is 1000-1300 rpm, the temperature is 700-1200 ℃, the thickness is 1.5-4.5 um, and the silicon doping concentration of the N-type GaN layer 3 is 1e18cm-3～3e19cm-3。
In actual production, an undoped GaN layer is deposited between the buffer layer 2 and the N-type GaN layer 3. The rotating speed of the undoped GaN layer wafer carrying disc 108 is 1000-1300 rpm, the temperature is 900-1200 ℃, and the thickness is 1.5-4.5 um.
Next, step S4 is performed to deposit a light emitting layer 4 on the N-type GaN layer 3. The light emitting layer 4 includes a quantum well layer 41 and a quantum barrier layer 42 sequentially stacked on the N-type GaN layer 3. At least one of the periodically stacked quantum well layers 41 and the quantum barrier layers 42 is a high-speed quantum well layer 41H and a low-speed quantum barrier layer 42L, and the rotating speed of the slide plate 108 for forming the high-speed quantum well layer 41H is greater than the rotating speed of the slide plate 108 for forming the low-speed quantum barrier layer 42L.
The rotation speed of the chip carrying disc 108 for forming the quantum well layer 41 and the quantum barrier layer 42 is 300-500 rpm, and the temperature is 700-1000 ℃.
In one embodiment, the rotation speed for forming the high-speed quantum well layer 41H slide plate 108 is 600-1200 rpm, and the rotation speed for forming the low-speed quantum barrier layer 42L slide plate 108 is 100-500 rpm. The temperature for forming the high-speed quantum well layer 41H and the low-speed quantum barrier layer 42L is 700 to 1000 ℃.
preferably, the rotation speed and the temperature for forming the high-speed quantum well layer 41H slide plate 108 are 900rpm and 850 ℃, respectively, and the rotation speed and the temperature for forming the low-speed quantum barrier layer 42L slide plate 108 are 300rpm and 850 ℃, respectively.
preferably, the light emitting layer 4 is composed of 5 to 18 quantum well layers 41 and quantum barrier layers 42 which are periodically stacked. The thickness of the quantum well layer 41 is 2.0 nm-4.0 nm, and the thickness of the quantum barrier layer 42 is 3.0 nm-12.0 nm.
preferably, an indium nitride layer 41a is provided between at least one of the high-speed quantum well layer 41H and the low-speed quantum barrier layer 42L. The rotation speed and temperature of the indium nitride layer 41a formed chip tray 108 are preferably equal to the rotation speed and temperature of the high-speed quantum well layer 41H formed chip tray 108.
preferably, an aluminum gallium nitride layer 42a is disposed between the indium nitride layer 41a and the low-speed quantum barrier layer 42L, and the rotation speed and temperature of the wafer carrying plate 108 for forming the aluminum gallium nitride layer 42a are preferably equal to the rotation speed and temperature of the wafer carrying plate 108 for forming the low-speed quantum barrier layer 42L.
Finally, step S5 is performed to deposit a P-type GaN layer 5 on the light emitting layer 4. The rotating speed of the wafer carrying disc 108 for forming the P-type GaN layer 5 is 400-700 rpm, the temperature is 700-1100 ℃, the growth thickness is 30-500 nm, and the magnesium doping concentration of the P-type GaN layer 5 is 5e18cm-3～5e20cm-3。
In actual production, an undoped AlGaN layer, a low-temperature P-type GaN layer, and a P-type electron blocking layer are sequentially stacked between the light emitting layer 4 and the P-type GaN layer 5. Preferably, the Al component of the undoped AlGaN layer is between 2 and 20 percent, and the growth thickness is between 20 and 35 nm. The growth thickness of the low-temperature P-type GaN layer is 10-100 nm, and the magnesium doping concentration is 5e18cm-3～5e20cm-3the growth temperature is lower than that of the P-type GaN layer 5. The P-type electron blocking layer is of a P-type AlGaN, P-type InAlGaN or P-type AlGaN/GaN superlattice structure, the growth thickness of the P-type electron blocking layer is 30 nm-80 nm, and the magnesium doping concentration is 5e18cm-3～5e20cm-3。
In conclusion, the rotating speed of the slide disc when the high-speed quantum well layer is formed is greater than that of the slide disc when the low-speed quantum barrier layer is formed, more indium is doped into gallium nitride by using the vortex generated by the slide disc rotating at high speed, the doping amount of the indium is prevented from being increased by reducing the growth temperature, the quantum well layer with the required wavelength can be deposited at higher temperature, the higher rotating speed is favorable for improving the crystallization quality, the crystallization quality of the obtained quantum well layer is better, and the half widths of the 002 surface and the 102 surface are smaller than that of the LED structure obtained at normal rotating speed through XRD test; the quantum well layer grows at a higher temperature, the temperature difference between the quantum well layer and the growth temperature of the quantum barrier layer is reduced, the smaller temperature difference can realize the quick switching from the growth of the quantum well layer to the growth of the quantum barrier layer on one hand, the whole process period is shortened, and on the other hand, the epitaxial warping caused by temperature fluctuation when the quantum well layer and the quantum barrier layer grow can be effectively reduced; repeated experiments prove that the indium is doped into the gallium nitride at a high rotating speed, and the content of the indium component in the obtained quantum well layer is more stable and uniform, so that the wavelength is more controllable and the uniformity is better; compared with the graphene layer, the graphene layer has the advantages that the production cost and the process complexity are greatly reduced, and the problem of carbon contamination does not exist.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (10)
1. An LED manufacturing process, comprising: the buffer layer, the N-type GaN layer, the light emitting layer and the P-type GaN layer are sequentially deposited on the substrate through a metal organic chemical vapor deposition process; the substrate is arranged on a rotating wafer carrying disc, the light emitting layer comprises a quantum well layer and a quantum barrier layer which are periodically stacked, at least one of the quantum well layer and the quantum barrier layer which are periodically stacked is a high-speed quantum well layer and a low-speed quantum barrier layer, and the rotating speed of the wafer carrying disc when the high-speed quantum well layer is formed is larger than that when the low-speed quantum barrier layer is formed.
2. The process of claim 1, wherein the high-speed quantum well layer is formed at a temperature equal to a temperature at which the low-speed quantum barrier layer is formed.
3. The process of claim 1 or 2, wherein the high-speed quantum well layer and the low-speed quantum barrier layer are adjacent quantum well layers and quantum barrier layers.
4. the process of claim 3, wherein the distance between the high-speed quantum well layer and the low-speed quantum barrier layer is less than the distance between the high-speed quantum well layer and the low-speed quantum barrier layer and the P-type GaN layer.
5. The process of claim 3, wherein an indium nitride layer is disposed between at least one of the high-speed quantum well layers and the low-speed quantum barrier layers.
6. The process of claim 5, wherein an aluminum gallium nitride layer is disposed between the indium nitride layer and the low-velocity quantum barrier layer.
7. The process of claim 6, wherein the rotation speed and temperature for forming the indium nitride layer chip carrier plate are equal to the rotation speed and temperature for forming the high-speed quantum well layer chip carrier plate, and the rotation speed and temperature for forming the aluminum gallium nitride layer chip carrier plate are equal to the rotation speed and temperature for forming the low-speed quantum barrier layer chip carrier plate.
8. The process of claim 1, wherein the high-speed quantum well layer chip carrier plate is formed at a speed of 600-1200 rpm, and the low-speed quantum barrier layer chip carrier plate is formed at a speed of 100-500 rpm.
9. The process of claim 8, wherein the high-speed quantum well layer is formed at a temperature of 700-1000 ℃ and the low-speed quantum barrier layer is formed at a temperature of 700-1000 ℃.
10. The process of claim 9, wherein the high-speed quantum well layer chip carrier plate is formed at a speed of 900rpm and a temperature of 850 ℃, and the low-speed quantum barrier layer chip carrier plate is formed at a speed of 300rpm and a temperature of 850 ℃.
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