WO2007123262A1

WO2007123262A1 - Method for manufacturing group iii nitride semiconductor light emitting element

Info

Publication number: WO2007123262A1
Application number: PCT/JP2007/059001
Authority: WO
Inventors: Tetsuo Sakurai
Original assignee: Showa Denko K.K.
Priority date: 2006-04-19
Filing date: 2007-04-19
Publication date: 2007-11-01
Also published as: TW200812111A; JP2007288052A

Abstract

Provided is a method for manufacturing a group III nitride semiconductor light emitting element having a high light emission output and a low drive voltage. In the method, an n-type semiconductor layer, a light emitting layer and a p-type semiconductor layer, which are composed of a group III nitride semiconductor, are grown in this order on a substrate. Then, at the time of forming a negative electrode and a positive electrode on the n-type semiconductor layer and the p-type semiconductor layer to manufacture the group III nitride semiconductor light emitting element, the growing speed of the p-type semiconductor layer is adjusted to 8-20nm/min.

Description

Specification

I I Group I Nitride Semiconductor Light-Emitting Device Manufacturing Method Technical Field

The present invention is characterized in that the light emission output is high and the driving voltage is low.

The present invention relates to a method for manufacturing a group I I I nitride semiconductor light emitting device. Background art

A group III nitride semiconductor light-emitting device is configured such that an n-type semiconductor layer and a P-type semiconductor layer are arranged with a light-emitting layer sandwiched therebetween, and holes are formed from a negative electrode and a positive electrode provided in contact with each other. Light is emitted by injecting electrons and recombining them at the PN junction in the semiconductor layer. Since the intensity of this light emission is proportional to the number of carriers of holes and electrons to be recombined, the light emission output of the light emitting element becomes higher as more current flows. However, in actuality, since there is heat generation due to the bulk resistance of the semiconductor layer and the resistance of the electrode constituent material, it is not practical to increase the applied current in order to increase the light emission output.

Therefore, when evaluating the characteristics of a light-emitting element, it is good to compare the light-emission output when a constant current (referred to as the rated current) is supplied and the forward voltage at that time (this is called the drive voltage V f). That is, in the rated current I _f, the place where the lower drive voltage v _f a and the light emitting output is high this aim as good characteristics of the light-emitting element.

When the electrode material constituting the light emitting element is constant, the driving voltage V depends on the configuration of the n-type semiconductor layer and the p-type semiconductor layer. In particular, since the p-type semiconductor layer has a wide contact area with the electrode material, the resistance generated by the P-type semiconductor layer must be as low as possible in order to reduce the drive voltage V ( It is necessary to suppress.

For example, by inserting a second p-type semiconductor layer (p-type contact layer) doped with impurities at a high concentration between the P-type semiconductor layer and the electrode material, the ohmic property with the electrode material is improved. Thus, the drive voltage _Vf is lowered (see, for example, the publication of Japanese Patent Laid-Open No. 8-9741). However, the decrease in drive voltage V _f is still insufficient. Disclosure of the invention

In view of the above situation, an object of the present invention is to provide a group III nitride semiconductor light emitting device having a high light emission output and a low driving voltage. FIG. 1 shows a forward direction of a group III nitride semiconductor light emitting device. The current-voltage characteristic diagram of In this figure, the voltage V. The driving voltage V _f of the rated current I _f, which is an intersection between the rated current I _f (line A in the figure) the ideal characteristics of the current - voltage characteristic And the ohmic voltage V _c between the p-type semiconductor layer and the electrode material. Therefore, the voltage V is used to reduce the drive voltage V _f at the rated current. And voltage V. Must be lowered.

Since the voltage V _e depends on the type of electrode material used, it is substantially determined by the selection. Therefore, in order to use a wide range of electrode materials, it is necessary to lower the voltage V _fl instead of V _e . Current Speaking of the graph of voltage characteristics, the voltage is V under a constant current. Lowering the value increases the slope of the straight line A, which is the ideal line. The following formula (1) is often used to represent the ideal characteristics of light-emitting elements.

I = I ₀ (EXP (q VXn-k T)-l) (1) This equation represents the straight line A in the forward current vs. voltage characteristic diagram of Fig. 1. The slope of the straight line A is i Zn · k T in the equation. This n is the force s, voltage V, which is called the n value in this equation. Decreasing the value means increasing the slope of the straight line A, that is, reducing the n value.

When the present inventors grow a p-type semiconductor layer of a group III nitride semiconductor under a growth condition such that the growth rate is 8 to 20 nmZ, the p-type III having excellent crystallinity. A group nitride semiconductor layer was obtained, and the present invention was completed by finding that the above-mentioned n-value was as extremely low as 2 or less.

That is, the present invention provides the following inventions.

(1) After growing an n-type semiconductor layer, a light-emitting layer, and a P-type semiconductor layer made of a group III nitride semiconductor on the substrate in this order, a negative electrode and a p-type semiconductor layer are formed on the n-type semiconductor layer and the P-type semiconductor layer. A method of manufacturing a group III nitride semiconductor light-emitting device comprising forming each positive electrode, wherein the growth rate of the p-type semiconductor layer is 8 to 2 O nmZ, Production method.

(2) The manufacturing method according to the above item (1), wherein the pressure in the growth apparatus when growing the p-type semiconductor layer is 10 to 5 O k Pa.

(3) A group I I I nitride semiconductor light-emitting device manufactured by the manufacturing method according to item 1 or 2.

(4) An n-type semiconductor layer, a light-emitting layer, and a P-type semiconductor layer made of a group III nitride semiconductor are stacked in this order on the substrate, and the positive electrode and the negative electrode are in contact with the P-type semiconductor layer and the n-type semiconductor layer, respectively. The group III nitride semiconductor light emitting device, wherein the n value of the current-voltage curve of the light emitting device represented by the following formula (1) is 2 or less in the provided light emitting device.

I = I ₀ (EXP (q V / n-k T)-l) (1) (5) A lamp comprising the group III nitride semiconductor light-emitting device according to item 3 or 4.

(6) An electronic device in which the lamp described in item 5 above is incorporated. (7) A mechanical device in which the electronic device described in the above item 6 is incorporated. According to the present invention, which is based on controlling the growth rate of the p-type semiconductor layer to 8 to 20 nm Z, a p-type group III nitride semiconductor layer having excellent crystallinity is obtained. As a result, drive voltage is low and light output is high II

A group I nitride semiconductor light emitting device is obtained. Brief Description of Drawings

FIG. 1 is a diagram for explaining forward current-voltage characteristics of a light emitting device. FIG. 2 is a schematic diagram showing a cross section of a group II I nitride semiconductor light emitting device of the present invention.

FIG. 3 is a graph showing the measurement result of the current-voltage characteristic curve of the light-emitting element obtained in Example 1.

FIG. 4 is a graph showing the measurement result of the current-voltage characteristic curve of the light-emitting element obtained in Example 2.

FIG. 5 is a graph showing the measurement result of the current-voltage characteristic curve of the light emitting device obtained in Comparative Example 1.

FIG. 6 is a graph showing the measurement result of the current-voltage characteristic curve of the light-emitting element obtained in Comparative Example 2. BEST MODE FOR CARRYING OUT THE INVENTION

The present invention provides a method for manufacturing a group III nitride semiconductor light emitting device, wherein the growth rate of the P type semiconductor layer is set to 8 ZO nm Z in the P type group III nitride semiconductor layer. The detailed contents of the invention will be described below.

FIG. 2 is a schematic view showing a cross section of an I I I group nitride semiconductor light emitting device having a p-type semiconductor layer according to the present invention. In this figure, reference numeral 7 denotes a positive electrode, which is composed of a light-transmitting or reflective positive electrode 7 and a bonding pad layer 7b. Reference numeral 5 denotes a p-type semiconductor layer, which is composed of a p-type cladding layer 5 a and a p-type contact layer 5 b. 1 is a substrate, 2 is a buffer layer, 3 is an n-type semiconductor layer, 4 is a light emitting layer, and 6 is a negative electrode.

In the present invention, the substrate 1 includes a sapphire single crystal (A 1 ₂ 0 ₃ ; A plane, C plane, M plane, R plane), spinel single crystal (Mg Al ₂ 0 ₄ ), Z η θ single crystal. , L i A l 0 ₂ single crystal, L i G a 0 ₂ single crystal, Mg 0 single crystal or oxide single crystal substrate such as G a ₂ 0 ₃ single crystal, and S i single crystal, S i C single crystal, G a a s single crystal, a 1 N single crystal, G a N single crystal or Z r non-oxide single-crystal substrate or we selected known substrate material such as boride single crystal such as B ₂ Can be used without any limitation. The plane orientation of the substrate is not particularly limited, and the off-angle may be arbitrarily selected.

The group III nitride semiconductors that make up the buffer layer, n-type semiconductor layer, light-emitting layer, and p-type semiconductor layer include the general formula A lx I ny G a ^ — _y N (0≤ x≤ 1, 0≤ y < Semiconductors of various compositions represented by 1, 0≤ x + y≤ 1) are known. In the group III nitride semiconductor constituting the buffer layer, the n-type semiconductor layer, the light-emitting layer, and the p-type semiconductor layer in the present invention, the general formula A 1 _x I _y G a _y N (0≤ x≤ 1 , 0≤ y <1, 0≤ x + y≤ 1), semiconductors with various compositions can be used without any limitation.

Methods for growing these III-nitride semiconductors include organic metal vapor phase epitaxy (MO C VD), molecular beam epitaxy (MB) E) and hydride vapor phase epitaxy (HVPE). Desirably, the composition control is easy and the MO CVD method with mass productivity is suitable, but it is not necessarily limited to this method.

When the MO C VD method is adopted as the method for growing the semiconductor layer, trimethyl gallium (TMG a) or triethyl gallium (TEG a), which is an organometallic material, is used as a raw material for Group III Ga. Trimethylaluminum (TMA 1) or triethylaluminum (TEA 1) is mainly used as the raw material for the group A 1. In addition, as a raw material for In, which is a constituent material of the light emitting layer, trimethylindium (TMI) or triethylindium (TEI) is used. Ammonia (NH ₃ ) or hydrazine (N ₂ H ₄ ) is used as the Group V N source.

Si or Ge is used as a dopant material for the n-type semiconductor layer. Monosilane (S i H ₄₎ or disilane (S i 2 H ₆₎ as the S i raw material, using germane (G e H ₄₎ or an organic gel Maniumu compound as G e material. In the p-type semiconductor layer, Mg is used as a dopant. As the raw material, for example, biscyclopentadienyl magnesium (C p ₂ Mg) or bisethyl cyclopentadienyl magnesium ((E t C p) ₂ Mg) is used.

Next, we describe each semiconductor layer that employs the general MO C VD method as a growth method.

(Buffer layer)

As the buffer layer, the low temperature buffer layer disclosed in Japanese Patent No. 3 0 2 6 0 8 7 or the like may be the high temperature buffer layer disclosed in Japanese Patent Application Laid-Open No. 2 0 0 3-2 4 3 3 0 2 or the like. These buffer layers can be used without any limitation.

The substrate for growth 1 can be selected from the previous list, but here The case where a sapphire substrate is used will be described. The substrate is placed on a SiC film-coated jig (susceptor) installed in a reaction space where the temperature and pressure can be controlled, and hydrogen carrier gas and nitrogen carrier gas are placed there. At the same time, send NH ₃ gas and TMA 1. The Graphite jig with SiC film is heated to the required temperature by induction heating with an RF coil, and an A 1 N buffer layer is formed on the substrate. In order to grow a low temperature buffer of A 1 N, the temperature is controlled from 5 00 ° C. to 700 ° C., and then raised to a temperature around 1 100 ° C. for crystallization. When growing a high-temperature A 1 N buffer layer, it is not possible to perform two-step heating, but at a temperature of 100 ° C. to 120 ° C. at a time. When using the A 1 N single crystal substrate or the GaN single crystal substrate described above, it is not always necessary to grow a buffer layer, and an n-type semiconductor layer described later is directly grown on the substrate.

(n-type semiconductor layer)

As the n-type semiconductor layer, those having various compositions and structures are known, and those having any composition and structure can be used in the present invention, including those known. Usually, the n-type semiconductor layer includes an underlayer composed of an ampere G a N layer, an n-type dopant such as Si or Ge, and more than the n-type contact layer and the light-emitting layer in which the negative electrode is provided. It consists of an n-type cladding layer with a large band gap energy. The n-type contact layer can double as the n-type cladding layer and the Z or underlayer.

Subsequent to the formation of the buffer layer, an underlayer composed of an undoped GaN layer is grown on the buffer layer. Temperature is set to 1 0 0 0-1 2 0 0, under pressure control, Komu feeding NH ₃ gas and TMG a to both the buffer layer and the carrier gas. TMG a supply flow at the same time Although limited by the ratio with NH ₃ , controlling the growth rate between 1 Am / hour and 3 ^ mZ is effective in suppressing the occurrence of crystal defects such as dislocations. As for the growth pressure, the region of 20 to 60 kPa (20 00 to 60 mb ar) is optimal for securing the above growth rate.

Then, following the growth of the G a N layer, the n-type contact layer is grown. The growth conditions are the same as those for the undoped GaN layer. The dopant is supplied together with the carrier gas, but the supply concentration is controlled by the ratio with the TMG a supply amount. In the present invention, the driving voltage of the light emitting element is lowered by forming a p-type semiconductor layer to be described later at a specific growth rate. However, the driving voltage is naturally affected by the concentration of dopant in the n-type contact layer. Therefore, the droop concentration of the n-type contact layer is determined according to the growth conditions of the p-type semiconductor layer. As a supply condition for the first punch, the M / Ga ratio (M = S i or G e

) Becomes a 1. oxi cr ³ can be ~ 6, 0 X low driving voltage by the 1 0 ³ range.

The thicknesses of the undoped GaN layer and the dopant-containing n-type semiconductor layer are preferably 1 to 4 m, but are not necessarily limited to this range. As a means to suppress the propagation of crystal defects from the substrate and buffer layer to the upper layer, it is possible to increase the film thickness of the undoped GaN layer and / or the dopant-containing n-type semiconductor layer. Filming induces warpage of the wafer itself, which is not a good idea. In the present invention, it is preferable to set the film thickness of each layer within the above range.

(Light emitting layer)

As the light emitting layer, those having various compositions and structures are known, and in the present invention, any composition and structure including these known ones are known. Can also be used.

For example, a light emitting layer having a multiple quantum well structure is formed by alternately laminating n-type G a N layers as barrier layers and G aln N layers as well layers. For carrier gas, select N ₂ or H ₂ for use. NH ₃ and TEG a or TMG a are supplied together with this carrier gas.

TM I is further supplied for the growth of the GaInN layer. In other words, it takes a process of supplying In intermittently while controlling the growth time. Since the control of I n concentration is difficult by H ₂ is interposed in the carrier gas in the growth of G a I n N layer, it is not advisable to use of H ₂ as a carrier gas at this layer. The film thickness of the barrier layer (n-type G a N layer) and well layer (G a I n N layer) is selected so that the light emission output is the highest. Once the optimal film thickness has been determined, select the Group III material supply and growth time appropriately. The amount of dopant in the barrier layer also depends on the driving voltage of the light emitting element, and the concentration is selected according to the growth conditions of the p-type semiconductor layer. Either S i or G e can be used as the target.

The growth temperature is preferably between 700 ° C. and 100 ° C., but is not necessarily limited to this range. However, in the growth of the well layer, at a high temperature, it becomes difficult for In to be taken into the growth film, and it is difficult to form the well layer substantially. Therefore, the growth temperature should be selected within a range that does not increase too much. In the present invention, the growth temperature of the light emitting layer is set in the range of 700 ° C. to 100 ° C., but there is no problem even if the growth temperature of the barrier layer and the well layer is changed. The growth pressure is set in balance with the growth rate. In the present invention, the growth pressure is preferably between 20 kPa (20 00 mb a r) and 60 k Pa (60 m mb a), but is not necessarily limited to this range.

It is the number of well layers and barrier layers. Although not necessarily limited to this range. The light-emitting layer is finished by finally growing the barrier layer (final barrier layer). This barrier layer prevents the carrier from overflowing from the well layer, and also prevents the elimination of In from the final well layer in the subsequent growth of the P-type semiconductor layer.

(P-type semiconductor layer)

The P-type semiconductor layer is also known in various compositions and structures, and in the present invention, those having any composition and structure can be used including those known. The P-type semiconductor layer is formed of mm, a P-type contact layer on which a positive electrode is formed, and a P-type cladding layer having a bandgap energy larger than that of the light emitting layer. P-type contact layer can also serve as P-type cladding layer

In the present invention, the P-type semiconductor layer whose growth rate is controlled to 8 to 20 nm is a P-type contact layer on which a positive electrode is formed.

The growth rate of the P-type cladding layer does not necessarily need to be within this range. The concentration of the Mg-and-pan cake in the P-type composite layer with a controlled growth rate is not particularly limited, but it has good crystallinity. in order to ensure the concentration of M g de one pan I ^{0. 9 X 1 0 2 0} ~ 2 X 1 0 2 ° atoms Z cm ³ Dearuko and are preferred. The P-type configuration Yuku coat layer in water atom may be present in a concentration of about ^{1 X 1 0 1 8 ~ 1} X 1 0 2 1 atom / cm ³ with M g dopant.

In the growth of the P-type semiconductor layer, first, the P-type cladding layer, which is directly in contact with the final barrier layer of the light-emitting layer, is controlled on the growth rate of 8 to 20 nm / min. Layer. It is preferable to use G a N or G a A 1 N for the p-type cladding layer. In addition, the ρ-type cladding layer may be formed by alternately stacking layers having different compositions or lattice constants, and the thickness of the layer and the concentration of Mg as a dopant may be changed. It is preferable to use Ga A 1 N for the p-type contact layer whose growth rate is controlled to 8 to 20 nm / min according to the present invention. The growth is carried out as follows. TMG a, TMA 1 and dopant C p ₂ Mg are fed onto the above p-type cladding layer together with a carrier gas (hydrogen or nitrogen, or a mixture of both) and NH ₃ gas.

The growth temperature at this time is preferably in the range of 980 to 1100 ° C = 9 8

When the temperature is lower than 0 ° C., an epitaxial layer having low crystallinity is formed, and the drive voltage is increased due to crystal defects. Also 1

At a higher temperature at 100, the well layer is placed in a high temperature environment during the growth process of the P-type semiconductor layer among the lower light emitting layers.

There is a possibility of receiving heat damage. In this case, there is a risk of causing a decrease in strength at the time of making the light emitting device or a deterioration in strength under a resistance test.

The growth pressure is not particularly limited, but preferably 50 k Pa (50 mbar) or less. The reason for this is that if grown below this pressure, the in-plane A 1 concentration in the p-type semiconductor layer can be made uniform, and if necessary, the A 1 composition of Ga A 1 N can be increased. This is because control is easy when growing the changed p-type semiconductor layer. Under conditions higher than this pressure, the reaction between the supplied TMA 1 and NH ₃ becomes prominent, and TM A 1 is consumed before reaching the substrate in the middle of growth, and the desired A 1 composition is obtained. Becomes difficult. The same can be said for Mg sent as a dopant. That is, when the growth condition is 50 k Pa (50 0 mbar) or less, the Mg concentration distribution in the two-dimensional direction (in-plane direction of the growth substrate) in the p-type semiconductor layer is uniform (the growth substrate surface). Internal uniformity).

It is also known that the distribution of A 1 composition and Mg concentration in the in-plane direction of the Ga A 1 N contact layer changes depending on the carrier gas flow rate used. The However, it was found that the in-plane uniformity of the A 1 composition and Mg in the contact layer was greatly influenced by the growth pressure condition rather than the carrier gas condition. Therefore, it is appropriate to set the growth pressure below 50 k Pa (50 00 mbar) and above 10 k Pa (lOOmbar) .The growth rate of the p-type semiconductor layer is mainly from the Ga source. Depends on the amount of TMG a supplied. If the TMGa supply amount per unit time is increased, the desired film thickness can be obtained in such a short time. The supply amount of the dopant raw material may be increased as well. However, the p-type semiconductor layer with a high growth rate is likely to introduce crystal defects, and even if the required concentration of doppins is included, donor levels increase due to crystal defects, resulting in a driving voltage V _f will not go down. On the other hand, if the growth rate is too low, the growth time until the target film thickness is reached becomes longer, and there is a risk of increasing thermal damage to the light emitting layer during the growth period. The inventor examined the supply amount of TMGa per unit time, limited the growth rate of the p-type semiconductor to a certain range, and changed the dopant supply amount condition in accordance with the growth rate. The growth condition of the p-type contact layer that satisfies the low drive voltage V _f and the absence of thermal damage to the light emitting layer is that the growth rate is 8 to 20 nmZ. Was found to be preferable.

The growth rate is determined by measuring the thickness of the P-type contact layer by electron microscope (TEM) observation of the UA-8 cross section and dividing it by the growth time. Therefore, the necessary growth conditions are determined in advance by preparing samples for observation with different conditions and investigating the relationship between the growth rate and the supply amount of TMGa per unit time in advance. Can.

After the growth of the P-type contact layer, the substrate heating is stopped and N Infeed ₂ gas, as well as purge the reaction space, cooled Ueha, cooled until taken out to the outside of the growth apparatus. In this method, the P-type semiconductor layer was confirmed to be the target P-type at this point. Therefore, heat treatment for activation after this is not indispensable.

Next, the negative electrode and the positive electrode provided on the n-type contact layer and the p-type contact layer will be described.

(Negative electrode)

As the negative electrode, those having various compositions and structures are known, and those of any composition and structure including these known ones can be used in the present invention. Various production methods are known as the production method, and these known methods can be used.

A known photolithography technique and a general etching technique can be used for producing the negative electrode forming surface on the n-type contact layer. With these technologies, it is possible to dig from the uppermost layer of We 18 to the position of the n-type contact layer, and to expose the n-type contact layer in the region where the negative electrode is to be formed. As the negative electrode material, metal materials such as Cr, W, and V as well as Al, Ti, Ni, and Au can be used as the contact metal in contact with the n-type contact layer. In order to improve adhesion to the n-type contact layer, a multilayer structure in which a plurality of contact metals are selected from the above metals may be used. When the outermost surface is Au, the bonding property is good.

(Positive electrode)

As the positive electrode provided on the P-type contact layer, light-transmitting or reflective positive electrodes having various compositions and structures are known, and the present invention also has any composition and structure including those known. Can be used. Various manufacturing methods are well known, and those public Knowledge methods can be used.

In the present invention, when light-transmitting ITO is used as the positive electrode material, it is preferable because the effect of reducing the driving voltage is great. It is preferable that the composition of I T O is 50% ≦ I n <100% and 0% and S n ≦ 50%. Within this range, low film resistance and high light transmittance can be satisfied. It is particularly preferable that I n is 90% and S n is 10%. ITO may contain elements of Group I, Group I, Group I, Group I or Group V as impurities. In addition, SnO, ZnO, or InO can be used instead of ITO.

The thickness of the I T O film is desirably 50 to 500 nm. If it is 50 nm or less, the film resistance of the ITO film itself increases and the drive voltage increases. Conversely, if it is thicker than 50 O nm, the extraction efficiency of light emission to the upper surface is lowered, and the light emission output does not increase.

As a method for forming the ITO film, a known vacuum deposition method or sputtering method can be used. There are resistance heating methods and electron beam heating methods for vacuum deposition, but electron beam heating methods are suitable for the deposition of materials other than metals. In addition, a method can be used in which the compound as a raw material is made liquid and applied to the surface to form an oxide film by appropriate treatment.

In the vapor deposition method, the crystallinity of the I T O film is affected by conditions, but this is not the case if the conditions are properly selected. If an ITO film is prepared at room temperature, heat treatment for transparency is required.

In the sputtering method, the surface of the p-type contact layer is easily damaged by the plasma because it is placed in a high-energy plasma environment, so the contact resistance tends to increase. By doing so, the influence on the surface of the p-type contact layer can be reduced. Usually, after forming a light transmissive or reflective positive electrode, a bonding pad layer constituting a bonding pad portion is formed on a part of the surface. Together with the bonding pad layer, a positive electrode is formed. As the material for the bonding pad layer, materials having various structures are known, and these well-known materials can be used in the present invention without any particular limitation. In addition to A 1, T i, N i and A u used for the negative electrode material, Cr, W and V can be used without any limitation. However, it is desirable to use a material having good adhesion to the light transmissive or reflective positive electrode used. The thickness must be sufficiently thick so as not to damage the light-transmitting or reflective positive electrode against the stress during bonding. The outermost layer is preferably made of a material having good adhesion to the bonding pole, such as Au.

The I I I group nitride semiconductor light-emitting device of the present invention can be formed into a lamp by providing a transparent cover by means well known in the art, for example. In addition, a white lamp can be manufactured by combining the gallium nitride compound semiconductor light emitting device of the present invention and a force bar having a phosphor.

In addition, a lamp manufactured from the Group III nitride semiconductor light-emitting device of the present invention has a low driving voltage and a high light-emitting output. Therefore, electronic devices such as mobile phones, displays, and panels incorporating lamps manufactured by this technology Mechanical devices such as automobiles, computers, and game machines that incorporate the electronic devices can be driven with low power and can achieve high characteristics. In particular, it can save power in battery-powered devices such as mobile phones, game machines, toys, and automobile parts. Example

Hereinafter, the present invention will be described in detail with reference to Examples and Comparative Examples. The invention is not limited to these examples.

(Example 1)

Set the sapphire substrate on the reactor susceptor and set the pressure inside the reactor.

20 k Pa (2 0 mbar), substrate temperature is controlled to 1 100 ° C, TMA 1 and NH ₃ are sent onto the substrate together with H ₂ carrier gas, and A 1 N buffer layer is formed did. The growth time was 10 minutes.

Then, TMG a and NH ₃ were supplied at a pressure of 40 k Pa (4 0 0 mbar), a temperature of 10 0 30 ° C, and an ampere G a N was formed on the A 1 N buffer layer. The formation was grown for 3 hours. Next, while maintaining pressure and temperature, tetramethyl germanium was supplied as an n-type dopant, and an n-type GaN layer was grown for 1 hour. The supply amount of tetramethylgermanium was adjusted so that the carrier concentration of the n-type GaN layer was 4.0 × 10 ¹⁸ cm− ³ . As a result, an n-type contact layer was formed.

After this, the pressure is 40 kPa (400 mbar), the temperature is 7500 ° C, the carrier gas is switched from H ₂ to N ₂ , TEG a and NH ₃ , and Si H ₄ as the dopant are supplied While growing the barrier layer for 7 minutes, the well layer was further grown for 5 minutes by supplying TMIn. This growth of the barrier layer and well layer was repeated five times alternately, and finally the final barrier layer was grown to form a light emitting layer. The amount of Si H _{4 in} the dopant was adjusted so that the Si concentration in the barrier layer and well layer was 2.0 X 10 ¹⁷ atoms / cm ³ .

After this, the pressure is 20 k Pa (2 00 mbar), the temperature is 10 00 ° C., the carrier gas is switched to H ₂ again, TMG a and TMA 1 are supplied, and C p _{2 is used} as a dopant. A p-type cladding layer made of G ao. ₉₅ A 10. _{Q 5} N was grown for 3 minutes by feeding Mg.

After this, while maintaining the pressure and temperature, it consists of G a _Q. ₉₈ A 1 _D. Q ₂ N A p-type contact layer was grown. As the condition, the TMG a supply amount was fixed so that the growth rate was 8 nm. The growth time was 15 minutes. The supply amount of C p ₂ Mg was adjusted so that the Mg concentration in the p-type contact layer would be 1 X 10 ^{2 Q} atom Z cm ³ .

Thereafter, stop power supply to the induction coil, cooling the heating was stopped Canon Riagasu switch to N _2, until a group III nitride semiconductor multilayer structure obtained with purging the furnace to a temperature that can be extracted from the furnace did.

A part of the n-type contact layer of the I II I nitride semiconductor laminate taken out of the furnace was exposed by photolithography and dry etching, and a negative electrode composed of a Cr and Ti metal layer was formed thereon. On the p-type contact layer, an IT ○ film (In: Sn = 9: 1) with a thickness of 3500 nm was fabricated by vapor deposition, and Ti, Au, A A bonding pad layer in which 1 and Au were laminated in this order was fabricated and used as the positive electrode. Thereafter, the substrate back surface was polished and scribed, and then divided into light emitting elements.

The obtained light emitting device was caused to emit light by passing a current of 20 mA, and the drive voltage V _f and the light emission output were measured and found to be 3.2 V and 9 mW. Figure 3 shows the measurement results of the current-voltage characteristic curve. From this figure, the n value obtained using the above equation (1) was 1.8. These results are summarized in Table 1 below together with other examples and comparative examples.

(Example 2)

A group I I I nitride semiconductor light emitting device was fabricated in the same manner as in Example 1 except that the growth conditions of the P-type contact layer were set to 20 nmZ for the growth rate and 6 minutes for the growth time.

When the obtained light emitting device was evaluated in the same manner as in Example 1, the driving voltage was Was 3.2 V and the light output was 9 mW. Figure 4 shows the measurement results of the current-voltage characteristic curve. From this figure, the n value obtained using the above equation (1) was 2.0.

(Comparative Example 1)

A II-I group nitride semiconductor light-emitting device was fabricated in the same manner as in Example 1 except that the growth conditions of the p-type contact layer were set to 7 nmZ for the growth rate and 17.2 minutes for the growth time.

The obtained light emitting device was evaluated in the same manner as in Example 1. As a result, the driving voltage was 3.3 V and the light emission output was 8 mW. Figure 5 shows the measurement results of the current-voltage characteristic curve. From this figure, the n value obtained using the above equation (1) was 2.6.

(Comparative Example 2)

A II-I group nitride semiconductor light-emitting device was fabricated in the same manner as in Example 1 except that the growth conditions of the P-type contact layer were set to 21 nm mZ and the growth time was 5.7 min.

When the obtained light emitting device was evaluated in the same manner as in Example 1, the drive voltage was 3.4 V and the light emission output was 8 mW. Figure 6 shows the measurement results of the current-voltage characteristic curve. From this figure, the n value obtained using the above equation (1) was 3.1. table 1

Industrial applicability The Group III nitride semiconductor light-emitting device of the present invention has a good light output and a low driving voltage, and thus has a very high industrial utility value.

Claims

FCT / JP2007 / 058001 O 2007/123262 PCT / JP2007 / 059001 Request scope

1. After a η-type semiconductor layer, a light emitting layer, and a saddle-type semiconductor layer made of a group III nitride semiconductor are grown in this order on a substrate, a negative electrode and a positive electrode are formed on the η-type semiconductor layer and the saddle-type semiconductor layer. In the method for producing a group III nitride semiconductor light-emitting device comprising forming each, the growth rate of the ρ-type semiconductor layer is 8 to 2 O nm / min.

I Group I nitride semiconductor light emitting device manufacturing method.

2. The manufacturing method according to claim 1, wherein the pressure in the growth apparatus when growing the p-type semiconductor layer is 10 to 50 kPa.

3. A group I I I nitride semiconductor light-emitting device manufactured by the manufacturing method according to claim 1.

4. An n-type semiconductor layer, a light emitting layer, and a p-type semiconductor layer made of a group III nitride semiconductor are stacked in this order on the substrate, and the positive electrode and the negative electrode are in contact with the p-type semiconductor layer and the n-type semiconductor layer, respectively. In the provided light emitting device, the current-voltage curve of the light emitting device represented by the following formula (1)

N value of 2 or less is a group I I I nitride semiconductor light emitting device.

I = I ₀ (EXP (q V / n-k T)-l) (1)

5. A lamp comprising the I I I group nitride semiconductor light-emitting device according to claim 3 or 4.

6. An electronic device in which the lamp according to claim 5 is incorporated.

7. A mechanical device in which the electronic device according to claim 6 is incorporated.