CN108198798A - 一种三极管以及其封装方法 - Google Patents
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Abstract
本发明涉及三极管和三极管封装领域,具体为一种三极管以及其封装方法,所述三极管包括三极管芯片、引线框架,包括基板、引脚、中筋和底筋、键合铜丝和环氧模塑料,采用黄铜作为引线框架基板的材料,所述引线框架预镀有金属镍镀层,所述金属镍镀层上镀一层纯铜;一种三极管封装工艺,依次包括划片、粘片、压焊、塑封、后固化、去溢料、打标、电镀锡、切中筋、切粒、测试、包装。本发明三极管和常规的三极管性能相近,通过本发明的技术手段,节省了企业成本,创造了经济效益。
Description
技术领域
本发明涉及半导体器件领域,尤其涉及一种三极管以及其封装方法。
背景技术
在现有技术中,三极管,全称应为半导体三极管,也称双极型晶体管、晶体三极管,是一种控制电流的半导体器件其作用是把微弱信号放大成幅度值较大的电信号,也用作无触点开关。晶体三极管,是半导体基本元器件之一,具有电流放大作用,是电子电路的核心元件。
随着电子技术的发展,三极管的使用越来越广泛,对于企业来说保证三极管质量的情况下,如何降低三极管的生产、封装成本,成为亟待解决的技术问题。
现有技术中,塑封三极管主要由三极管芯片、环氧模塑料、引线框架和键合丝构成。引线框架一般用KFC、C19400和C19200等磷青铜材料制成,因此,引线框架在塑封三极管总成本中所占比例较高。另外,引线框架在三极管封装成型后形成的引脚部分需电镀锡层以供装配时容易焊接。
文献CN 101404261A提出,通过在三极管封装时,减少框架厚度,例如降低框架引脚厚度为0.36-0.44mm,实现节约材料以降低物料成本,同时降低了产品的重量,使单个产品的运输费用降低。
然而上述方法,降低了引脚框架的厚度,从一方面来说增大了加工难度,另一方面必然会降低三极管的某些使用性能,例如强度等。
发明内容
针对现有技术中存在的缺陷或不足,本发明所要解决的技术问题是:提供一种性能不会出现降低、而制造成本降低的三极管以及其封装方法。
为了实现上述目的,本发明采取的技术方案为提供一种三极管,包括三极管芯片,环氧模塑料,引线框架和键合铜丝,其中引线框架包括框架基板、引脚、中筋、底筋,其特征在于,所述引线框架采用黄铜制作,所述引线框架预镀镍,镍层上再镀纯铜,纯铜层外镀锡。
作为本发明的一种改进,所述黄铜为单相黄铜或者双相黄铜。
作为本发明的一种改进,所述黄铜为H96-H65、H63-H59、H62。
作为本发明的一种改进,所述黄铜为成分为63.5%~68%的铜,杂质含量不大于0.3%,其余成分为锌。
为了实现本发明的目的,本发明还提供一种三极管封装方法。
一种三极管的封装方法,依次包括以下制造步骤:
1)划片;
2)粘片,将三极管芯片粘贴在引线框架的基板上,使三极管的集电极与基板实现欧姆接触;
3)压焊,将键合铜丝焊接在三极管芯片正面电极与引线框架的引脚上;
4)塑封,使用环氧模塑料对引线框架上的三极管芯片进行塑封成型保护;
5)后固化、去溢料、打标;
6)电镀锡;
7)切中筋、切粒,在三极管成型后将连接引线框架引脚间的中筋用冲压的方法切除,裸露切口处黄铜,在三极管成型后将连接引线框架引脚间的底筋用自动切粒机上高速转动的切粒刀切除以形成单个的三极管;
8)测试、包装。
作为本发明的一种改进,所述粘片共晶工艺温度为380-470℃。
作为本发明的一种改进,所述压焊主要工艺参数为超声功率为20-60mW,键合压力为50-120g,键合时间为6-20ms,保护气体氮气流量为400-800mL/min。
作为本发明的一种改进,所述塑封模具温度为165-195℃,合模压力大于等于9.65MPa,转进压力大于等于1.4MPa,转进时间为1-20s,纯固化时间大于等于40s。
本发明的有益效果是:
1)本发明的三极管性能较常规的三极管没有降低,生产成本约降低15%;
2)采用本发明的封装三极管的方法,可以有效阻止镀锡时锡层晶须产生,而且不影响三极管引脚的焊接性能。
附图说明
图1粘片、压焊后的引线框架;
图2实施例1中切中筋前的三极管;
图3实施例1中切中筋后的三极管;
图4实施例1中切中筋后并镀锡的三极管以及剖面图;
图5实施例1成型的三极管;
图6实施例2切中筋的三极管;
图7实施例2切中筋、底筋后成型的三极管。
具体实施方式
下面结合附图说明及具体实施方式对本发明进一步说明。
图1至图7中的附图标号为:引线框架基板1,三极管芯片2,键合铜丝3,引脚101,中筋102,底筋103,黄铜基体1010,镍层1011,纯铜层1012,锡层1013。
一种三极管,包括三极管芯片2,环氧模塑料,引线框架和键合铜丝3,其中引线框架包括框架基板1、引脚101、中筋102、底筋103,其特征在于,所述引线框架采用黄铜基板1010制作,所述引线框架预镀镍1011,镍层上再镀纯铜1012,纯铜层外镀锡1013,切中筋,切粒工序设置在在镀锡层之后,切口裸露黄铜。
实施例1:
如图1-5所示,一种三极管,经过粘片、压焊之后的三极管的引线框架基板1包括三极管芯片2,键合铜丝3,引脚101,中筋102,底筋103;
附图2是采用黄铜作为引线框架基板材料之后,采用常规三极管封装流程制备得到的切中筋102、底筋103前的三极管,以及该引线框架的截面图,内层基体为黄铜1010,外面第一层为镍层1011,第二层为纯铜层1012。
附图3为采用黄铜作为引线框架基板材料之后,采用常规的三极管封装流程切除中筋102之后的三极管,该三极管在切除中筋处裸露出了黄铜基体1010。
附图4为采用黄铜作为引线框架基板材料之后,采用常规的三极管封装流程切除中筋102之后,镀锡后的三极管,以及在切除中筋102处的截面图和其他位置的截面图,可以看出,在镀锡后引线框架中筋102切口处的金属层分布情况为镀锡层直接接触黄铜基体;其他位置则为基体黄铜1010-镀镍层1011-纯铜层1012-镀锡层1013。
附图5为采用黄铜作为引线框架基板材料之后最终成型的三极管。
附图1-5为本发明的制备三极管的方法之一,然而按照该方法制备的三极管,在切中筋后,切口处为黄铜裸露而没有镍层阻挡,引线框架其它部分仍是有镍层阻挡并被纯铜包裹着,镀锡后,切口处锡层直接覆盖住黄铜表面,而引线框架其它部分则是黄铜+镍+纯铜+锡。这样,切口处黄铜中的锌析出后便很会比较容易促使锡表面晶须产生,而引线框架其它部分因有镍层阻挡则不容易使锡表面产生晶须。
实施例2:
作为本发明制备三极管的另一种方法参见说明书附图6-7,申请人发现,其他步骤和流程1中相同,然而将切中筋102步骤改在电镀锡后进行,令人惊讶地发现,如图6所示,切口处裸露的引线框架黄铜基体而没有锡,其他部分均有镍镀层1011,锡层1013表面较难长出晶须。
附图7为采用本发明另外一个方法封装的三极管的示意图,中筋切口位置距离引脚焊点有足够的距离,切口处的裸露黄铜并不影响引脚的可焊性。
实施例3:
一种三极管的封装方法,依次包括以下制造步骤:
1)划片;
2)粘片,将三极管芯片用高温的方法直接粘贴在引线框架基板上,以使三极管背面(集电极)与基板实现欧姆接触,粘片共晶工艺温度为380-470℃;
3)压焊,采用超声球焊的方法将键合铜丝分别焊接在三极管芯片正面铝电极(基极和发射极)与引线框架的引脚上,从而实现三极管的基极和发射极与引脚相连。压焊主要工艺参数:超声功率为20-60mW,键合压力为50-120g,键合时间为6-20ms,保护气体氮气流量为400-800mL/min。
4)塑封,使用环氧模塑料对引线框架上的三极管芯片进行塑封成型保护;塑封模具温度为165-195℃,合模压力为9.65MPa及以上,转进压力为1.4MPa及以上,转进时间为1-20s,纯固化时间40s及以上。
5)后固化、去溢料、打标;
6)电镀锡;
7)切中筋、切粒,在三极管成型后将连接引线框架引脚间的中筋用冲压的方法切除,裸露切口处黄铜,在三极管成型后将连接引线框架引脚间的底筋用自动切粒机上高速转动的切粒刀切除以形成单个的三极管;
8)测试、包装。
采用黄铜作为引线框架基体材料,节省材料成本约15%,并且不影响三极管的性能。
以上内容是结合具体的优选实施方式对本发明所作的进一步详细说明,不能认定本发明的具体实施只局限于这些说明。对于本发明所属技术领域的普通技术人员来说,在不脱离本发明构思的前提下,还可以做出若干简单推演或替换,都应当视为属于本发明的保护范围。
Claims (8)
1.一种三极管,包括三极管芯片,环氧模塑料,引线框架和键合铜丝,其中引线框架包括基板、引脚、中筋和底筋,其特征在于,所述引线框架采用黄铜制作,所述引线框架预镀镍,镍层上再镀纯铜,纯铜层外镀锡。
2.根据权利要求1所述的三极管,其特征在于,所述黄铜为单相黄铜或者双相黄铜。
3.根据权利要求2所述的三极管,其特征在于,所述黄铜为H96-H65、H63-H59、H62。
4.根据权利要求1所述的三极管,其特征在于,所述黄铜为成分为63.5%~68%的铜,杂质含量不大于0.3%,其余成分为锌。
5.一种如权利要求1的三极管的封装方法,其特征在于,依次包括以下制造步骤:
1)划片;
2)粘片,将三极管芯片粘贴在引线框架的基板上,使三极管的集电极与基板实现欧姆接触;
3)压焊,将键合铜丝焊接在三极管芯片正面电极与引线框架的引脚上;
4)塑封,使用环氧模塑料对引线框架上的三极管芯片进行塑封成型保护;
5)后固化、去溢料、打标;
6)电镀锡;
7)切中筋、切粒,在三极管成型后将连接引线框架引脚间的中筋用冲压的方法切除,裸露切口处黄铜,在三极管成型后将连接引线框架引脚间的底筋用自动切粒机上高速转动的切粒刀切除以形成单个的三极管;
8)测试、包装。
6.根据权利要求5所述的三极管制备方法,其特征在于:所述粘片共晶工艺温度为380-470℃。
7.根据权利要求5所述的三极管制备方法,其特征在于:所述压焊主要工艺参数为超声功率为20-60mW,键合压力为50-120g,键合时间为6-20ms,保护气体氮气流量为400-800mL/min。
8.根据权利要求5所述的三极管制备方法,其特征在于:所述塑封模具温度为165-195℃,合模压力大于等于9.65MPa,转进压力大于等于1.4MPa,转进时间为1-20s,纯固化时间大于等于40s。
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Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20030178707A1 (en) * | 2002-03-21 | 2003-09-25 | Abbott Donald C. | Preplated stamped small outline no-lead leadframes having etched profiles |
US20040183166A1 (en) * | 2003-03-17 | 2004-09-23 | Abbott Donald C. | Preplated leadframe without precious metal |
US20060125062A1 (en) * | 2004-12-15 | 2006-06-15 | Zuniga-Ortiz Edgar R | Semiconductor package having improved adhesion and solderability |
CN101901789A (zh) * | 2010-06-28 | 2010-12-01 | 启东市捷捷微电子有限公司 | 内绝缘型塑封半导体器件及其制造方法 |
CN103187382A (zh) * | 2011-12-27 | 2013-07-03 | 万国半导体(开曼)股份有限公司 | 应用在功率半导体元器件中的铝合金引线框架 |
-
2018
- 2018-01-12 CN CN201810029660.0A patent/CN108198798A/zh active Pending
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20030178707A1 (en) * | 2002-03-21 | 2003-09-25 | Abbott Donald C. | Preplated stamped small outline no-lead leadframes having etched profiles |
US20040183166A1 (en) * | 2003-03-17 | 2004-09-23 | Abbott Donald C. | Preplated leadframe without precious metal |
US20060125062A1 (en) * | 2004-12-15 | 2006-06-15 | Zuniga-Ortiz Edgar R | Semiconductor package having improved adhesion and solderability |
CN101901789A (zh) * | 2010-06-28 | 2010-12-01 | 启东市捷捷微电子有限公司 | 内绝缘型塑封半导体器件及其制造方法 |
CN103187382A (zh) * | 2011-12-27 | 2013-07-03 | 万国半导体(开曼)股份有限公司 | 应用在功率半导体元器件中的铝合金引线框架 |
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