CN108124494B - 半导体装置 - Google Patents
半导体装置 Download PDFInfo
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- CN108124494B CN108124494B CN201680009069.8A CN201680009069A CN108124494B CN 108124494 B CN108124494 B CN 108124494B CN 201680009069 A CN201680009069 A CN 201680009069A CN 108124494 B CN108124494 B CN 108124494B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 223
- 239000004020 conductor Substances 0.000 claims abstract description 60
- 239000002019 doping agent Substances 0.000 claims abstract description 35
- 238000009792 diffusion process Methods 0.000 claims description 47
- 239000000758 substrate Substances 0.000 claims description 35
- 230000002093 peripheral effect Effects 0.000 claims description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 7
- 229920005591 polysilicon Polymers 0.000 claims description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 5
- 230000004888 barrier function Effects 0.000 claims description 4
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 4
- 230000000149 penetrating effect Effects 0.000 claims description 3
- 150000002500 ions Chemical class 0.000 description 6
- 230000004048 modification Effects 0.000 description 6
- 238000012986 modification Methods 0.000 description 6
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 5
- 229910052796 boron Inorganic materials 0.000 description 5
- 230000015556 catabolic process Effects 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 229910001415 sodium ion Inorganic materials 0.000 description 2
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000007792 addition Methods 0.000 description 1
- 230000002730 additional effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 238000012217 deletion Methods 0.000 description 1
- 230000037430 deletion Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
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Abstract
【课题】提供一种能够抑制过电压保护二极管的耐压变动的半导体装置。【解决手段】实施方式涉及的半导体装置1包括:绝缘膜4,被形成在耐压区域B上;过电压保护二极管5,具有被交替地相邻配置在所述第一绝缘膜上的N型半导体层5a与P型半导体层5b;导体部6、7、8、9,被形成在绝缘膜4上,并且与过电压保护二极管5电气连接;绝缘膜15,覆盖过电压保护二极管5以及导体部6、7、8、9;以及高电位部17,经由绝缘膜15被配置在过电压保护二极管5的上方,其中,P型半导体层5b的P型掺杂物浓度比N型半导体层5a的N型掺杂物浓度更低,高电位部17被构成为:在反向偏置施加状态下,具有比位于高电位部17正下方的P型半导体层5b的电位更高的电位。
Description
技术领域
本发明涉及半导体装置,具体为涉及设置有过电压保护二极管的半导体装置。
背景技术
以往,具有IGBT(Insulated Gate Bipolar Transistor)或MOSFET(MOS FieldEffect Transistor)等的,所谓具有MOS(Metal-Oxide-Semiconductor)构造的半导体装置已被普遍认知。在这样的MOS型半导体装置中,作为过电压保护的应对措施,使用的是由串联而成的稳压二极管(Zener diode)构成的过电压保护二极管。具体来说,该过电压保护二极管是由交替地相邻配置的N型半导体层与P型半导体层所构成的(例如参照专利文献1)。而IGBT则是在集电极端子与栅极端子之间,或栅极端子与发射极端子之间设置有过电压保护二极管。
如图8所示,过电压保护二极管的P型半导体层50b(以及N型半导体层)在被配置在形成于半导体基板120上的绝缘膜140上的同时,被绝缘膜150所覆盖。
通常,在过电压保护二极管中,P型半导体层中的P型掺杂物浓度比N型半导体层中的N型掺杂物浓度更低。因此,过电压保护二极管的耐压(齐纳电压)是通过P型掺杂物浓度的高浓度区域(浓度最高值)的位置而决定的。以往的过电压保护二极管如图8所示,P型掺杂物的浓度在P型半导体层50b与绝缘膜150之间的界面区域F10处为最大值。即,界面区域F10处的P型掺杂物浓度比内部区域G10处的P型掺杂物浓度更高。因此,过电压保护二极管会在界面区域F10处齐纳击穿()。
先行技术文献
专利文献1:特开2009-111304号公报
然而,在MOS型半导体装置的制造过程(加热工序等)中,会发生:绝缘膜150中含有的纳等的可动离子以及硼等的掺杂物移动到P型半导体层50b中、或相反地,P型半导体层50b的界面区域F10中的硼等的掺杂物移动到绝缘膜150中。像这样,可动离子以及掺杂物的移动会导致界面区域F10的电位发生变化,从而导致P型半导体层50b中的载流子浓度的分布发生变化。这样就与P型掺杂物浓度的高浓度区域的位置发生变动成为了同样的状态。其结果就是:过电压保护二极管的耐压会发生大的变动。以往,对可动离子以及掺杂物的移动进行控制是较为困难的,因此也就很难使过电压保护二极管的耐压处于稳定状态。
本发明鉴于上述课题,目的是提供一种能够对过电压保护二极管的耐压变动进行控制的半导体装置。
发明内容
本发明涉及的半导体装置,在半导体基板的一方的主面与另一方的主面之间流通主电流,其特征在于:
在所述半导体基板的所述一方的主面上,设置有:流通所述主电流的活性区域、以及将所述活性区域包围并且的,并且包含所述半导体基板的周缘部的耐压区域,
所述半导体装置,包括:
第一绝缘膜,被形成在所述耐压区域上;
过电压保护二极管,具有被交替地相邻配置在所述第一绝缘膜上的N型半导体层与P型半导体层;
多条导体部,被形成在所述第一绝缘膜上,并且与所述过电压保护二极管电气连接;
第二绝缘膜,覆盖所述过电压保护二极管以及所述导体部;以及
高电位部,经由所述第二绝缘膜被配置在所述过电压保护二极管的上方,
其中,所述P型半导体层的P型掺杂物浓度比所述N型半导体层的N型掺杂物浓度更低,
所述高电位部被构成为:在反向偏置施加状态下,具有比位于所述高电位部正下方的P型半导体层的电位更高的电位。
另外,在所述半导体装置中,也可以是:
在所述反向偏置施加状态下,所述P型半导体层的与所述第二绝缘膜之间的界面区域中的正电荷浓度,低于比所述P型半导体层的所述界面区域更靠近内部的区域中的正电荷浓度。
另外,在所述半导体装置中,也可以是:
所述高电位被形成在所述第二绝缘膜上。
另外,在所述半导体装置中,也可以是:
所述高电位部的正下方包含有多个所述P型半导体层。
另外,在所述半导体装置中,也可以是:
所述高电位部经由被形成在所述第二绝缘膜上的导电连接部与所述导体部电气连接。
另外,在所述半导体装置中,也可以是:
所述导电连接部的一端与所述高电位部电气连接,另一端与所述导体部电气连接。
另外,在所述半导体装置中,也可以是:
所述高电位部被配置在:比与所述导电连接部连接后的导体部与所述过电压保护二极管相连接的部位更靠近中央部侧的部位中所述过电压保护二极管的上方。
另外,在所述半导体装置中,也可以是:
所述导电连接部的所述另一端经由贯穿所述第二绝缘膜的接触层与所述导体部电气连接。
另外,在所述半导体装置中,也可以是:
所述接触层被配置在用于将所述导体部与所述过电压保护二极管连接的连接区域上。
另外,在所述半导体装置中,也可以是:
所述导电连接部被配置在:从平面上看比与该导电连接部电气连接的所述导体部更靠近所述活性区域侧。
另外,在所述半导体装置中,也可以是:
所述高电位部的一端经由被形成在所述第二绝缘膜上的第一导电连接部与所述导体部电气连接,另一端经由被形成在所述第二绝缘膜上的第二导电连接部与所述导体部电气连接。
另外,在所述半导体装置中,也可以是:
进一步包括:上侧导体部,被形成在所述第二绝缘膜上并由导电性材料所构成,
所述上侧导体部被设置为:与所述高电位部电气连接,并且从平面上看与所述导体部重叠。
另外,在所述半导体装置中,也可以是:
所述P型半导体层以及所述N型半导体层由多晶硅构成。
另外,在所述半导体装置中,也可以是:
所述第一绝缘膜以及/或所述第二绝缘膜由硅氧化膜构成。
另外,在所述半导体装置中,也可以是:
所述半导体基板为第一导电型,
所述半导体装置中还进一步包括:
第二导电型扩散层,被选择性地形成在所述耐压区域的所述一方的主面上,并且包围所述活性区域;
第一导电型扩散区域,被形成在所述扩散层中;
发射极,被形成在所述扩散区域上;
栅电极,被形成在所述过电压保护二极管上;
第二导电型集电极区域,被形成在所述半导体基板的所述另一方的主面上;以及
集电极,被形成在所述集电极区域上。
另外,在所述半导体装置中,也可以是:
所述半导体基板为第一导电型,
所述半导体装置中还进一步包括:
第二导电型扩散层,被选择性地形成在所述耐压区域的所述一方的主面上,并且包围所述活性区域;
第一导电型扩散区域,被形成在所述扩散层中;
发射极,被形成在所述扩散区域上;
栅电极,被形成在所述过电压保护二极管上;
第一导电型漏极区域,被形成在所述半导体基板的所述另一方的主面上;以及
集电极,被形成在所述漏极区域上,并且与所述漏极区域形成肖特基势垒。
另外,在所述半导体装置中,也可以是:
所述半导体基板为第一导电型,
所述半导体装置中还进一步包括:
第二导电型扩散层,被选择性地形成在所述耐压区域的所述一方的主面上,并且包围所述活性区域;
第一导电型扩散区域,被形成在所述扩散层中;
源电极,被形成在所述扩散区域上;
栅电极,被形成在所述过电压保护二极管上;
第一导电型漏极区域,被形成在所述半导体基板的所述另一方的主面上;以及
漏电极,被形成在所述漏极区域上。
发明效果
由于本发明涉及的半导体装置包括:高电位部,其被构成为:经由覆盖过电压保护二极管的第二绝缘膜被设置在过电压保护二极管的上方,并且,在反向偏置施加状态下,具有比位于其正下方的P型半导体层的电位更高的电位。因此,在反向偏置施加状态下,过电压保护二极管的P型半导体层中的正电荷就会远离P型半导体层与第二绝缘膜之间的界面。即,P型半导体层中的正电荷就会向P型半导体层的内部区域移动。
其结果就是,界面区域中正电荷的浓度变得比中央区域中正电荷的浓度更低。即,正电荷的浓度最高处变为位于内部区域中。通过这样,过电压保护二极管就会在内部区域中齐纳击穿。因此,即便是在可动离子以及掺杂物跨越界面区域以及P型半导体层间移动的情况下,也能够抑制过电压保护二极管的耐压变动。
因此,根据本发明,就能够对过电压保护二极管的耐压变动进行抑制。
简单附图说明
图1是第一实施方式涉及的半导体装置1(IGBT)的平面图。
图2是沿图1的I-I线的截面图。
图3A是沿图1的II-II线的截面图。
图3B是沿图1的III-III线的截面图。
图4是将过电压保护二极管5的一部分放大后的斜视图。
图5是在反向偏置施加状态下P型半导体层5b的正电荷浓度数据图。
图6是第一实施方式的变形例涉及的半导体装置1A的截面图。
图7是第二实施方式涉及的半导体装置1B(纵型MOSFET)的截面图。
图8是以往的P型半导体层50b中正电荷浓度的数据图。
图9是在反向偏置施加状态下各区域的电位示例图。
图10是将图1中的区域C放大后的放大平面图。
【发明的具体实施方式】
以下,将参照附图对本发明涉及的各实施方式进行说明。各图中具有同等功能的构成要素使用同一符号进行了标示。
(第一实施方式)
以下,将参照图1~图5以及图10,对本发明的第一实施方式涉及的半导体装置1进行说明。图1是半导体装置1的平面图,但图中并未图示有绝缘膜15、表面保护膜16、发射极21、栅电极22、塞电极(Stopper electrode)24。另外,图3A中的截面图并不严密地对应图10中的一部分放大图。
第一实施方式涉及的半导体装置1具有IGBT构造,并且在其导电性的半导体基板2的上端面2a(一方的主面)与下端面2b(另一方的主面)之间流通有主电流。另外,虽然半导体基板2在本实施方式中为硅基板,但本发明并不仅限于此,也可以是其他类型的半导体基板(例如SiC基板、GaN基板等)。另外,半导体基板2的导电类型虽然在本实施方式中为N型,但不仅限于此。
如图1所示,半导体基板2的上端面2a上,设置有:流通主电流的活性区域A、以及包围该活性区域A的耐压区域B。耐压区域B包含半导体基板2的周缘部。这里的“周缘部”是指包含半导体基板2的侧面的半导体基板2的周缘部分。
如图1~图3A、图3B所示,半导体装置1包括:P型扩散层3、绝缘膜4、绝缘膜15(第二绝缘膜)、过电压保护二极管5、导体部6、7、8、9、N型缓冲区域11、P型集电极区域12、N型扩散区域13、N型塞电极区域14、表面保护膜16、发射极21、栅电极22、集电极23、以及塞电极24。半导体基板2的上端面2a上还设置有栅极焊盘(Gate pad)(未图示)。
扩散层3被选择性地的形成在耐压区域B的上端面2a上,并且将活性区域A包围。该扩散层3也称为P型基极区域。图1中由界面P1和P2包围的区域就是P型基极区域。界面P1是扩散层3与周边半导体区域10之间的pn结的界面,界面P2是活性区域A与耐压区域B之间的界面。周边半导体区域10是位于扩散层3的外侧的N型半导体区域。
半导体装置1中也可以进一步包括:为了高耐压化而被设置为包围扩散层3的P型扩散层(保护环)。该保护环被选择性地形成在耐压区域B的上端面2a上。另外,保护环的数量不仅限于一个,可以是两个或更多。
扩散层3以及保护环的掺杂物浓度,例如为1×1014cm-3~1×1019cm-3。扩散层3以及保护环的深度,例如为2μm~10μm。周边半导体区域10的掺杂物浓度,例如为1×1013cm-3~1×1015cm-3。
绝缘膜4被形成在半导体基板2的耐压区域B上。在本实施方式中,如图2所示,被形成在扩散层3、以及周边半导体区域10上。该绝缘膜4例如为硅氧化膜(SiO2膜),具体为为场氧化膜,其厚度例如为200nm~2000nm。
过电压保护二极管5由多个稳压二极管串联而成。在本实施方式中,过电压保护二极管5被设置在半导体装置1的集电极23与栅电极22之间。另外,也可以将本发明涉及的过电压保护二极管的构成,适用于被设置在栅电极22与发射极21之间的过电压保护二极管。
过电压保护二极管5如图2以及图4所示,其具有被交替地相邻配置在绝缘膜4上的N型半导体层5a和P型半导体层5b。即,过电压保护二极管5被形成在绝缘膜4上,并且其所具有的构成为N型半导体层5a和P型半导体层5b被交替地相邻配置。N型半导体层5a和P型半导体层5b被形成在耐压区域B的绝缘膜4上。例如,过电压保护二极管5是通过在绝缘膜4上形成P型半导体层后,再在P型半导体层的规定区域中导入N型掺杂物来形成的。
N型半导体层5a和P型半导体层5b由导电性的半导体(在本实施方式中为被导入掺杂物的多晶硅)构成。具体为:N型半导体层5a为被导入N型掺杂物(磷等)的多晶硅层。P型半导体层5b为被导入P型掺杂物(硼等)的多晶硅层。P型半导体层5b的P型掺杂物浓度例如为1×1016cm-3~1×1018cm-3。N型半导体层5a的N型掺杂物浓度例如为1×1019cm-3~1×1021cm-3。像这样,P型半导体层5b中的P型掺杂物的浓度比N型半导体层中的N型掺杂物的浓度更低。另外,多晶硅层的厚度例如为100nm~1000nm。
导体部6、7、8、9如图1所示,被形成为在绝缘膜4上沿耐压区域B包围活性区域A,并且分别与过电压保护二极管5的规定部位电气连接。即,导体部6、7、8、9基于各个重要部位的电压,从而与过电压保护二极管5的半导体层(N型半导体层5a和P型半导体层5b)电气连接。连接后的半导体层与导体部为相同的导电类型。另外,导体部也可以是连续跨过两个以上的半导体层后进行连接。
导体部6、7、8、9例如由被导入掺杂物的多晶硅或铝等导电性材料构成。在本实施方式中,如图3A以及图3B所述,导体部6、7经由绝缘膜4配置在扩散层3的上方,导体部8、9则经由绝缘膜4配置在周边半导体区域10的上方。导体部的数量不仅限于4个,可以为任意数量。
扩散区域13如图2所示,是形成在扩散层3中的N型半导体区域。该扩散区域13上形成有发射极21。另外,扩散区域13的掺杂物浓度,例如为1×1019cm-3~1×1021cm-3。
塞电极区域14如图2以及图3A所示,是一个被形成在半导体基板2侧端中的上端面2a上的N型半导体区域。该塞电极区域14的掺杂物浓度高于周边半导体区域10。塞电极24与过电压保护二极管5的另一端(在图2中为右端)电气连接。在塞电极区域14上形成有塞电极24。塞电极区域14的掺杂物浓度例如为1×1019cm-3~1×1021cm-3。
栅电极22经由绝缘膜4设置在扩散层3的上方。该栅电极22在本实施方式中,被形成在过电压保护二极管5上。具体来说,如图2所示,栅电极22与过电压保护二极管5的活性区域A侧的一端(图2中为左端)电气连接。
P型集电极区域12被形成在半导体基板2的下端面2b上。该集电极区域12的掺杂物浓度例如为1×1017cm-3~1×1019cm-3。如图2所示,集电极区域12上形成有集电极23。另外,与集电极区域12相邻设置有缓冲区域11。该缓冲区域11的掺杂物浓度例如为1×1016cm-3~1×1018cm-3。
绝缘膜15如图2所示,被设置为覆盖过电压保护二极管5以及导体部6、7、8、9。该绝缘膜15的厚度例如为200nm~2000nm。绝缘膜15例如为硅氧化膜,在本实施方式为BPSG(Boron Phosphorous Silicate Glass)膜。
表面保护膜16如图2所示,覆盖整个半导体装置1的上端面2a侧。该表面保护膜16例如为聚酰亚胺膜或硅氮化膜。
高电位部17经由绝缘膜15被设置在过电压保护二极管5的上方。即,高电位部17被形成在P型半导体层5b的正上方。在本实施方式中,高电位部17如图2所示,被形成在绝缘膜15上。另外,如图2所示,也可以在高电位部17的正下方包含有多个P型半导体层5b。也可以将与最外周的导体部9电气连接的高电位部17设置在过电压保护二极管5的上方。一般来说,高电位部17可以随导体部6、7、8、9中任意的至少一个以上的导体部来设置。
高电位部17有导电性的材料(例如铝等金属)构成。高电位部17例如是通过与发射极21和栅电极22相同的工序来形成的。
高电位部17经由导电连接部18(第一导电连接部)以及导电连接部19(第二导电连接部)与导体部6、7、或8电气连接。具体来说,高电位部17的一端(例如左端)经由导电连接部18与导体部6、7、或8电气连接,另一端(例如右端)经由导电连接部19与导体部6、7、或8电气连接。
另外,半导体装置1还可以进一步包括:由被形成在绝缘膜15上的导电性材料构成的上侧导体部。该上侧导体部例如被设置为从平面上看与导体部6重叠,并且经由导电连接部18、19与高电位部17电气连接。例如,当导体部6为图1所示的环形时,上侧导体部也按照导体部6被设置为环形。通过设置这样的上侧导体部,就能够进一步稳定表面电位,从而进一步提升半导体装置1的可靠性。
导电连接部18(19)如图3A所示,被形成在绝缘膜15上。该导电连接部18(19)的一端与高电位部17电气连接,另一端与导体部6、7或8电气连接。导电连接部18、19的另一端如图3A所示,经由贯穿绝缘膜15的接触层20与导体部6、7或8电气连接。接触层20可以与导电连接部18(19)一体形成。例如,导电连接部18、19以及接触层20可以在高电位部17的形成工序中被一同形成。
接触层20在本实施方式中被设置在连接区域Bc上。这里的连接区域Bc如图1所示,是位于过电压保护二极管5近旁的区域,为了导体部6、7、8、9与过电压保护二极管5连接,从而接触区域Bc之间的间隔被设定的很宽。
另外,接触层20也可以被设置在连接区域Bc外的区域上。也可以将导电连接部18、19中的任意一方省略掉。即,高电位部17也可以经由导电连接部18或导电连接部19与导体部6、7或8电气连接。
高电位部17如图1以及图10所示,被配置在:比与导电连接部18、19连接后的导体部6、7或8与过电压保护二极管5相连接的部位更靠近中央部侧(即低电位侧)的部位中过电压保护二极管5的上方。通过这样,如图9所示,高电位部17在反向偏置施加状态下,就会具有比位于其自身正下方的P型半导体层5b的电位更高的电位。这里的反向偏置施加状态,是指:在第一实施方式中,集电极23与高电位(例如直流电源的正极)连接,发射极21与接地连接,并且栅电极22处被施加不会使IGBT导通(ON)程度的低电压后的状态。
像这样,高电位部17如图9所示,被构成为:在反向偏置施加状态下,具有比位于其自身正下方的P型半导体层5b的电位更高的电位。
如上述般,在本实施方式涉及的半导体装置1中,由于设置有高电位部17,因此在反向偏置施加状态下,P型半导体层5b中的正电荷(空穴、可动离子等)就会远离P型半导体层5b与绝缘膜15之间的界面。即,P型半导体层中的正电荷就会向P型半导体层的内部区域移动。
其结果就是,如图5所示,界面区域F中正电荷的浓度变得比内部区域G中正电荷的浓度更低。即,正电荷的浓度最高处变为位于P型半导体层5b的内部区域G中。通过这样,过电压保护二极管5就会在内部区域G中齐纳击穿。
这里的“界面区域F”,是指:P型半导体层5b内的,包含P型半导体层5b与绝缘膜15之间的界面的区域。即,界面区域F为P型半导体层5b与绝缘膜5之间的界面区域。
由于过电压保护二极管5会在内部区域G中齐纳击穿,因此即便是在钠离子等可动离子以及硼等掺杂物跨越界面区域F以及P型半导体层间移动的情况下,也能够抑制过电压保护二极管5的耐压变动。所以,根据本实施方式,就能够对过电压保护二极管5的耐压变动进行抑制。即,能够稳定过电压保护二极管5的耐压。
(半导体装置1的变形例)
IGBT的构成不仅限于上述的半导体装置1。图6是第一实施方式的变形例涉及的半导体装置1A的截面图。图6中与图2为相同的构成要素则使用同一符号进行标示。
变形例涉及的半导体装置1A如图6所示,具有替代P型集电极区域12的N型漏极区域12A,并且,具有与该漏极区域12A形成肖特基势垒的集电极23。此情况下,集电极23具有由铂、钼等构成的势垒金属。
在半导体装置1A中,高电位部17被形成在绝缘膜15上。该高电位部17在反向偏置施加状态下通过使P型半导体层5b的正电荷向下方(集电极23侧)移动,从而能够抑制过电压保护二极管5的耐压变动。
(第二实施方式)
接下来,对本发明的第二实施方式涉及的半导体装置1B进行说明。该半导体装置1B为纵型MOSFET。半导体装置1B的平面图与图1相同。图7是半导体装置1B的截面图,其对应在第一实施方式中说明的图2。在图7中,与第一实施方式相同的构成要素使用了同一符号进行标示。下面,将以其与第一实施方式的不同点为中心进行说明。
半导体装置1B,包括:P型扩散层3、绝缘膜4、过电压保护二极管5、导体部6、7、8、9、N型漏极区域12B、N型扩散区域13、N型塞电极区域14、高电位部17、导电连接部18、19、接触层20、源电极21A、栅电极22、漏电极23A、以及塞电极24。漏极区域12B被形成在半导体基板2的下端面上,并且在该漏极区域12B上形成有漏电极23A。另外,源电极21A被形成在扩散区域13上。
过电压保护二极管5被设置在纵型MOSFET的漏电极23A与栅电极22之间,或被设置在源电极21A与栅电极22之间。
在半导体装置1B中,高电位部17被形成在绝缘膜15上。该电位部17在反向偏置施加状态下通过将P型半导体层5b的正电荷向下方(集电极23侧)移动,就能够抑制过电压保护二极管5的耐压变动。因此,根据第二实施方式,就能够提供能够抑制过电压保护二极管5的耐压变动的MOSFET。
基于上述记载,虽然本领域业者或许可以联想到本发明的追加效果或各种变形,但本发明的形态并不仅限于上述的各个实施方式。也可是将各种不同的实施方式间的构成要素进行适宜的组合。并且能够在专利请求的范围所规定的内容内,以及不脱离由其对等物指引出的本发明概念性的思想和主旨的范围内进行各种追添加、变更以及部分删除。
符号说明
1、1A、1B、半导体装置
2 半导体基板
2a 上端面
2b 下端面
3 扩散层
4、140 绝缘膜
5 过电压保护二极管
5a N型半导体层
5b、50b P型半导体层
6、7、8、9 导体部
10 周边半导体区域
11 缓冲区域
12 集电极区域
12A、12B 漏极区域
13 扩散区域
14 塞电极区域
15、150 绝缘膜
16 表面保护膜
17 高电位部
18、19 导电连接部
20 接触层
21 发射极
21A 源电极
22 栅电极
23 集电极
23A 漏电极
24 塞电极
A 活性区域
B 耐压区域
C 区域
F1、F10 界面区域
G、G10 内部区域
P1、P2 (扩散层3的)界面
Claims (15)
1.一种半导体装置,在半导体基板的一方的主面与另一方的主面之间流通主电流,其特征在于:
在所述半导体基板的所述一方的主面上,设置有:流通所述主电流的活性区域、以及将所述活性区域包围并且包含所述半导体基板的周缘部的耐压区域,
所述半导体装置,包括:
第一绝缘膜,被形成在所述耐压区域上;
过电压保护二极管,具有被交替地相邻配置在所述第一绝缘膜上的N型半导体层与P型半导体层;
多条导体部,被形成在所述第一绝缘膜上,并且与所述过电压保护二极管电气连接;
第二绝缘膜,覆盖所述过电压保护二极管以及所述导体部;以及
高电位部,经由所述第二绝缘膜被配置在所述过电压保护二极管的上方,
其中,所述P型半导体层的P型掺杂物浓度比所述N型半导体层的N型掺杂物浓度更低,
所述高电位部被构成为:在反向偏置施加状态下,具有比位于所述高电位部正下方的P型半导体层的电位更高的电位,
所述高电位部经由被形成在所述第二绝缘膜上的导电连接部与所述导体部电气连接,所述导电连接部的一端与所述高电位部电气连接,另一端与所述导体部电气连接。
2.根据权利要求1所述的半导体装置,其特征在于:
其中,在所述反向偏置施加状态下,所述P型半导体层的与所述第二绝缘膜之间的界面区域中的正电荷浓度,低于比所述P型半导体层的所述界面区域更靠近内部的区域中的正电荷浓度。
3.根据权利要求1所述的半导体装置,其特征在于:
其中,所述高电位被形成在所述第二绝缘膜上。
4.根据权利要求1所述的半导体装置,其特征在于:
其中,所述高电位部的正下方包含有多个所述P型半导体层。
5.根据权利要求1所述的半导体装置,其特征在于:
其中,所述高电位部被配置在:比与所述导电连接部连接后的导体部与所述过电压保护二极管相连接的部位更靠近中央部侧的部位中所述过电压保护二极管的上方。
6.根据权利要求1所述的半导体装置,其特征在于:
其中,所述导电连接部的所述另一端经由贯穿所述第二绝缘膜的接触层与所述导体部电气连接。
7.根据权利要求6所述的半导体装置,其特征在于:
其中,所述接触层被配置在用于将所述导体部与所述过电压保护二极管连接的连接区域上。
8.根据权利要求1所述的半导体装置,其特征在于:
其中,所述导电连接部被配置在:从平面上看比与该导电连接部电气连接的所述导体部更靠近所述活性区域侧。
9.根据权利要求1所述的半导体装置,其特征在于:
其中,所述导电连接部具有:将所述高电位部的一端与所述导体部电气连接的第一导电连接部、以及将所述高电位部的另一端与所述导体部电气连接的第二导电连接部。
10.根据权利要求1所述的半导体装置,其特征在于,进一步包括:
上侧导体部,被形成在所述第二绝缘膜上并由导电性材料所构成,
所述上侧导体部被设置为:与所述高电位部电气连接,并且从平面上看与所述导体部重叠。
11.根据权利要求1所述的半导体装置,其特征在于:
其中,所述P型半导体层以及所述N型半导体层由多晶硅构成。
12.根据权利要求1所述的半导体装置,其特征在于:
其中,所述第一绝缘膜以及/或所述第二绝缘膜由硅氧化膜构成。
13.根据权利要求1所述的半导体装置,其特征在于:
其中,所述半导体基板为第一导电型,
所述半导体装置中还进一步包括:
第二导电型扩散层,被选择性地形成在所述耐压区域的所述一方的主面上,并且包围所述活性区域;
第一导电型扩散区域,被形成在所述扩散层中;
发射极,被形成在所述扩散区域上;
栅电极,被形成在所述过电压保护二极管上;
第二导电型集电极区域,被形成在所述半导体基板的所述另一方的主面上;以及
集电极,被形成在所述集电极区域上。
14.根据权利要求1所述的半导体装置,其特征在于:
其中,所述半导体基板为第一导电型,
所述半导体装置中还进一步包括:
第二导电型扩散层,被选择性地形成在所述耐压区域的所述一方的主面上,并且包围所述活性区域;
第一导电型扩散区域,被形成在所述扩散层中;
发射极,被形成在所述扩散区域上;
栅电极,被形成在所述过电压保护二极管上;
第一导电型漏极区域,被形成在所述半导体基板的所述另一方的主面上;以及
集电极,被形成在所述漏极区域上,并且与所述漏极区域形成肖特基势垒。
15.根据权利要求1所述的半导体装置,其特征在于:
其中,所述半导体基板为第一导电型,
所述半导体装置中还进一步包括:
第二导电型扩散层,被选择性地形成在所述耐压区域的所述一方的主面上,并且包围所述活性区域;
第一导电型扩散区域,被形成在所述扩散层中;
源电极,被形成在所述扩散区域上;
栅电极,被形成在所述过电压保护二极管上;
第一导电型漏极区域,被形成在所述半导体基板的所述另一方的主面上;以及
漏电极,被形成在所述漏极区域上。
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CN1649169A (zh) * | 2004-01-29 | 2005-08-03 | 三菱电机株式会社 | 半导体器件 |
CN104221152A (zh) * | 2012-07-18 | 2014-12-17 | 富士电机株式会社 | 半导体装置以及半导体装置的制造方法 |
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WO2018061177A1 (ja) | 2018-04-05 |
JPWO2018061177A1 (ja) | 2018-09-27 |
CN108124494A (zh) | 2018-06-05 |
JP6301551B1 (ja) | 2018-03-28 |
NL2019315B1 (en) | 2018-04-10 |
US10361184B2 (en) | 2019-07-23 |
US20180331092A1 (en) | 2018-11-15 |
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