CN108122592B - 半导体装置和半导体集成系统 - Google Patents

半导体装置和半导体集成系统 Download PDF

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Publication number
CN108122592B
CN108122592B CN201711016611.5A CN201711016611A CN108122592B CN 108122592 B CN108122592 B CN 108122592B CN 201711016611 A CN201711016611 A CN 201711016611A CN 108122592 B CN108122592 B CN 108122592B
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memory chip
serial bus
semiconductor device
memory
chip
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CN108122592A (zh
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佐藤创
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Renesas Electronics Corp
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Renesas Electronics Corp
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Abstract

本公开涉及半导体装置和半导体集成系统。提供可以通过简单的方法访问和测试存储器芯片的半导体装置。在公共封装中安装多个芯片的半导体装置包括具有预定的功能的逻辑芯片和与逻辑芯片耦接并存储数据的存储器芯片。存储器芯片包括执行存储器芯片的操作测试的存储器芯片测试电路和用于在存储器芯片测试电路和设置在封装外部的串行总线之间发送和接收数据的串行总线接口电路。

Description

半导体装置和半导体集成系统
相关申请的交叉引用
于2016年11月30日提交的日本专利申请No.2016-232846的公开内容(包括说明书、附图和摘要)通过引用全部并入本文中。
技术领域
本公开涉及半导体装置和半导体集成系统，并且涉及包括存储器芯片的半导体装置。
背景技术
其中大容量存储器芯片和具有特定功能(诸如图像处理)的逻辑芯片被安装在同一封装中、被称为MCP(Multi Chip Package，多芯片封装)或MCM(Multi-Chip Module，多芯片模块)的半导体装置正在变得普遍。
在这方面，日本未审查专利申请公开No.2003-77296提出了其中将自测试电路(BIST：内建自测试电路)安装在MCP中的逻辑芯片上并且执行对封装在同一MCP中的存储器芯片的测试的实施例。
但是，该实施例是逻辑芯片访问存储器芯片的方法，并且该实施例没有公开直接访问存储器芯片以及测试和调试存储器芯片的方法。
发明内容
另一方面，需要从封装外部的引脚直接访问存储器芯片的机制。
本公开是为了解决以上问题，并且本公开的目的是提供可以通过简单的方法访问和测试存储器芯片的半导体装置和半导体集成系统。
从本说明书和附图的描述中，其它问题和新颖特征将变得清楚。
根据实施例，在公共封装中安装多个芯片的半导体装置包括具有预定的功能的逻辑芯片和与逻辑芯片耦接并存储数据的存储器芯片。存储器芯片包括执行存储器芯片的操作测试的存储器芯片测试电路和用于在存储器芯片测试电路和设置在封装外部的串行总线之间发送和接收数据的串行总线接口电路。
根据实施例，存储器芯片包括串行总线接口电路，使得可以通过简单的方法访问存储器芯片。
附图说明
图1是用于说明基于第一实施例的半导体装置1的构造的图。
图2是用于说明基于第一实施例的半导体装置1的截面结构的图。
图3是用于说明基于第一实施例的存储器芯片MD的构造的图。
图4是用于说明基于第一实施例的基部管芯的功能块的图。
图5是用于说明基于第一实施例的串行总线接口电路SIF的构造的图。
图6是用于说明基于第一实施例的系统板SD的构造的图。
图7是用于说明基于第一实施例的修改例的存储器芯片MD#的构造的图。
图8是用于说明基于第二实施例的半导体装置1#的构造的图。
图9是用于说明基于第三实施例的系统板SD#的构造的图。
具体实施方式
将参考附图详细描述实施例。在附图中给予相同或对应的部分相同的附图标记，并且将不再重复对该部分的描述。
(第一实施例)
图1是用于说明基于第一实施例的半导体装置1的构造的图。
如图1所示，半导体装置1是在公共封装中安装多个芯片的半导体装置。
具体而言，半导体装置1包括逻辑芯片PU和存储器芯片MD。
逻辑芯片PU是被结合以便实现预定的功能的诸如处理器单元的芯片。
存储器芯片MD是包括存储数据的存储器元件的芯片。
逻辑芯片PU与存储器芯片MD耦接，并向存储器芯片MD发送和从存储器芯片MD接收时钟、控制信号、地址和数据。例如，存储器芯片MD与来自逻辑芯片PU的时钟同步操作。根据来自逻辑芯片PU的控制信号的输入和地址来访问存储器芯片MD。例如，从存储器芯片MD读取数据到逻辑芯片PU，或者从逻辑芯片PU写入数据到存储器芯片。
在本示例中，存储器芯片MD与测试电路TC和串行总线接口电路SIF结合。
存储器芯片MD包括DRAM(动态随机存取存储器)元件作为示例。
半导体装置1的测试电路TC通过串行总线接口电路SIF包括外部端子SDAP和外部端子SCLP。
外部端子SDAP是用于执行串行数据通信的数据端子。外部端子SCLP是指定用于执行串行数据通信的定时的时钟端子。
外部端子SDAP和SCLP与设置在半导体装置1外部的串行总线耦接。
在本示例中，作为串行总线接口电路SIF，使用诸如I2C(Inter-IntegratedCircuit，内部集成电路)的标准串行总线接口电路作为示例。
测试电路TC是BIST电路，并且测试存储器芯片MD中的DRAM元件的操作等。
基于第一实施例的半导体装置1被安装有存储器芯片MD中的串行总线接口电路SIF，并且可以通过外部串行总线向测试电路TC发出测试指令。此外，半导体装置1可以通过串行总线从测试电路TC获取输出结果(测试结果)。
基于第一实施例的半导体装置1设置有诸如I2C的标准串行总线的外部端子SDAP和SCLP，用于访问存储器芯片MD的测试电路TC。外部端子SDAP和SCLP耦接到标准串行总线。
第一实施例的存储器芯片MD是堆叠型存储器芯片(半导体存储装置)，并且该半导体存储装置设置有测试电路TC。测试电路TC是根据诸如I2C的标准串行总线的信号在存储器芯片MD内部执行DRAM元件的测试的电路。测试电路TC被设置为能够通过外部端子SDAP和SCLP被直接控制。在正常操作中，存储器芯片MD由诸如处理器单元的逻辑芯片PU控制。具体而言，存储器芯片MD通过发送和接收时钟、控制信号、地址和数据与诸如处理器单元的逻辑芯片PU直接通信，并且存储器芯片MD不是从外部直接访问的。存储器芯片MD用作处理器单元等的分组缓冲器和高速缓存存储器。
因此，可以通过根据第一实施例的配置通过简单方法访问存储器芯片MD。虽然已经提出了通过使用测试引脚访问存储器芯片MD的方法，但是使用测试引脚的方法增加了系统设计者的负担并且还增加了成本。另一方面，当使用采用现有串行总线的方法时，系统设计者可以在使用现有总线的同时通过简单的方法执行测试，而无需引入用于新的测试的任何专用总线。
图2是用于说明基于第一实施例的半导体装置1的截面结构的图。
如图2所示，存储器芯片MD通过硅插入件SIP与逻辑芯片PU耦接。
硅插入件SIP通过超精细(ultra-fine)布线耦接在存储器芯片MD和逻辑芯片PU之间。
硅插入件SIP通过有机基板10与外部封装球13直接电耦接。外部封装球13用作外部端子。在本示例中，外部封装球13用作外部端子SDAP和SCLP。
存储器芯片MD由多个堆叠型存储器管芯形成。
图3是用于说明基于第一实施例的存储器芯片MD的构造的图。
如图3所示，存储器芯片MD包括设置在最下层的基部管芯102和设置在基部管芯102上方的多个存储器管芯100。
基部管芯102和多个存储器管芯100通过垂直结构贯通电极TSV彼此电耦接。
贯通电极TSV通过设置在基部管芯102下方的凸块BP与硅插入件SIP电耦接。
图4是用于说明基于第一实施例的基部管芯102的功能块的图。
如图4所示，基部管芯102安装有测试电路TC和串行总线接口电路SIF。
串行总线接口电路SIF与外部端子SDAP和外部端子SCLP耦接。
测试电路TC基于通过串行总线接口电路SIF从外部端子SDAP和外部端子SCLP输入的数据被控制。来自测试电路TC的测试结果通过串行总线接口电路SIF输出到外部端子SDAP。
图5是用于说明基于第一实施例的串行总线接口电路SIF的构造的图。
如图5所示，串行总线接口电路SIF包括用于时钟信号的时钟缓冲器SCLB、用于数据信号的数据缓冲器SDAB和串行链路单元SL。
串行链路单元SL与用于时钟信号的时钟缓冲器SCLB和用于数据信号的数据缓冲器SDAB耦接。
串行链路单元SL接收通过串行总线输入的串行时钟和串行数据，并向测试电路TC输出测试指令。此外，串行链路单元SL从测试电路TC接收输出结果(测试结果)，并将串行时钟和串行数据输出到串行总线。
外部端子SCLP与时钟缓冲器SCLB耦接。外部端子SDAP与数据缓冲器SDAB耦接。
时钟缓冲器SCLB包括放大器AP1、反相器IV1和晶体管TR1。
数据缓冲器SDAB包括放大器AP2、反相器IV2和晶体管TR2。
关于串行时钟(SCL_DATA和SCL_OUT)和串行数据(SDA_DATA和SDA_OUT)，通过时钟缓冲器SCLB和数据缓冲器SDAB将数据发送到串行链路单元SL以及从串行链路单元SL接收数据。
串行链路单元SL和串行总线之间通过时钟缓冲器SCLB和数据缓冲器SDAB的数据通信方法是众所周知的，因此将不再详细描述该方法。作为示例，可以使用I2C串行总线的通信方法。
图6是用于说明基于第一实施例的系统板SD的构造的图。
如图6所示，在系统板SD(母板)上，安装控制整个系统板SD的全体控制单元MCU、外围装置5、半导体装置1和串行总线SB。作为外围装置5，作为示例，可以安装各种传感器的半导体装置。但是，外围装置5不限于传感器。
全体控制单元MCU、外围装置5和半导体装置1通过串行总线SB耦接，并且串行总线SB通过电阻元件R0和R1由电源电压VCC上拉。串行总线SB包括串行数据总线SDB和串行时钟总线SCB。串行数据总线SDB被设置用于串行数据。串行时钟总线SCB被设置用于串行时钟。
虽然在附图中未示出，但是每个都作为装置的全体控制单元MCU、外围装置5和半导体装置1分别设置有串行总线接口，并且能够彼此通信。作为示例，可以使用I2C串行总线的通信方法。
全体控制单元MCU可以通过串行总线SB访问每个半导体装置1。当在系统板SD上对根据实施例的存储器芯片MD执行测试时，不需要为存储器芯片引入专用总线。可以通过使用现有的标准串行总线来测试存储器芯片MD。此外，通过使用标准串行总线来控制测试电路(BIST电路)，使得可以减少用于开发测试程序和调试软件的工时。
(修改例)
图7是用于说明基于第一实施例的修改例的存储器芯片MD#的构造的图。
如图7所示，存储器芯片MD#包括多个存储器管芯100#。
存储器芯片MD#与图3所述的存储器芯片MD的不同之处在于存储器芯片MD#没有基部管芯。
具体而言，存储器芯片MD#仅由多个存储器管芯100#形成。
以与上述相同的方式，多个存储器管芯100#通过垂直结构贯通电极TSV彼此电耦接。
贯通电极TSV通过设置于最低存储器管芯100#的凸块BP与硅插入件SIP电耦接。
最低存储器管芯100#设置有测试电路TC和串行总线接口电路SIF。
其它部件与第一实施例的部件相同，因此不再重复其详细描述。
通常，经常将不同的处理节点分别施加于基部管芯和存储器管芯。但是，在第一实施例的修改例中，可以仅通过存储器管芯的处理节点获得与第一实施例的效果相同的效果，使得可以进一步降低成本。
(第二实施例)
图8是用于说明第二实施例的半导体装置1#的构造的图。
如图8所示，半导体装置1#在公共封装中安装多个存储器芯片MDA和MDB以及公共逻辑芯片PU。
存储器芯片MDA和MDB中的每个都被构造为能够从逻辑芯片PU被访问。
其它部件与图1的部件相同，因此将不再重复其详细描述。
存储器芯片MDA包括测试电路TCA和串行总线接口电路SIFA。
存储器芯片MDB包括测试电路TCB和串行总线接口电路SIFB。
测试电路TCA和TCB基本上与测试电路TC相同。
串行总线接口电路SIFA和SIFB基本上与串行总线接口电路SIF相同。
设置外部端子SDAP和外部端子SCLP作为串行总线接口电路SIFA和SIFB的公共端子。
在本示例中，示出了将识别信息分配给存储器芯片MDA和MDB中的每个的情况。
具体而言，识别信息ID(0x0)被分配给存储器芯片MDA。作为示例，串行总线的装置ID(0x0)被设置为对应于存储器芯片MDA。此外，识别信息ID(0x1)被分配给存储器芯片MDB。作为示例，串行总线的装置ID(0x1)被设置为对应于存储器芯片MDB。
基于第二实施例的半导体装置1#将串行总线接口电路SIFA和SIFB分别安装在存储器芯片MDA和MDB上。串行总线接口电路SIFA和SIFB分别根据分配给存储器芯片MDA和MDB的识别信息接收通过外部串行总线输入的测试指令的输入。
测试电路TCA和TCB中的每个根据测试指令执行测试。测试电路TCA和TCB可以通过外部串行总线输出输出结果(测试结果)。
通过这种构造，可以通过串行总线从系统直接测试包括在半导体装置1#中的每个存储器芯片。
此外，在本示例中，可以通过使用公共外部端子SDAP和SCLP来访问多个存储器芯片。因此，即使当半导体装置中安装了多个存储器芯片时，也可以将作为半导体装置的外部端子所需的串行总线端子的数量减少到最小。
(第三实施例)
图9是用于说明基于第三实施例的系统板SD#的构造的图。
如图9所示，在系统板SD#(母板)上，安装控制整个系统板SD#的全体控制单元MCU、多个半导体装置1A至1C以及串行总线SB。
半导体装置1A在公共封装中安装多个存储器芯片MDA、MDB、MDC和MDD以及逻辑芯片PU。
存储器芯片MDA、MDB、MDC和MDD中的每个都被配置为能够从逻辑芯片PU被访问。其它部件与图1的部件相同，因此将不再重复其详细描述。
在本示例中，示出了将识别信息分配给存储器芯片MDA至MDD中的每个的情况。此外，示出了还将识别信息分配给多个半导体装置1A至1C中的每个的情况。
具体而言，串行总线的装置ID被划分为高位和低位，然后高位被分配给半导体装置，并且低位被分配给半导体装置的存储器芯片。
作为示例，串行总线的装置ID的高位ID1的集合被分配为分别对应于半导体装置1A至1C。具体而言，装置ID1(0x0)被设置为对应于半导体装置1A。装置ID1(0x1)被设置为对应于半导体装置1B。装置ID1(0x2)被设置为对应于半导体装置1C。
此外，串行总线的装置ID的低位ID0的集合被分配为分别对应于每个半导体装置1A至1C中的存储器芯片。具体而言，串行总线的装置ID0(0x0)被设置为对应于存储器芯片MDA。串行总线的装置ID0(0x1)被设置为对应于存储器芯片MDB。串行总线的装置ID0(0x2)被设置为对应于存储器芯片MDC。串行总线的装置ID0(0x3)被设置为对应于存储器芯片MDD。
虽然在本示例中没有设置外围装置，但是外围装置5可以进一步安装在系统板SD#上。外围装置5不限于传感器。
全体控制单元MCU和半导体装置1A至1C通过串行总线SB耦接，并且串行总线SB通过电阻元件R0和R1由电源电压VCC上拉。虽然在附图中未示出，但是每个都作为装置的全体控制单元MCU和半导体装置1A至1C被分别设置有串行总线接口，并且能够彼此通信。例如，可以使用I2C串行总线的通信方法。
全体控制单元MCU可以通过使用识别信息的高位通过串行总线SB访问每个半导体装置1。此外，全体控制单元MCU可以通过使用识别信息的低位通过串行总线SB访问半导体装置中的对应存储器芯片。
当在系统板SD上对根据实施例的存储器芯片MD执行测试时，不需要为存储器芯片引入专用总线。可以通过使用现有标准串行总线来测试存储器芯片MD。此外，通过使用标准串行总线控制测试电路(BIST电路)，使得可以减少用于开发测试程序和调试软件的工时。
虽然已经基于实施例具体描述了本公开，但是不用说，本发明不限于实施例，并且可以在不脱离本发明的范围的情况下进行各种修改。

Claims (16)

1.一种半导体装置，包括：
逻辑芯片，所述逻辑芯片具有预定的功能；以及
存储器芯片，所述存储器芯片与所述逻辑芯片耦接并存储数据，
其中，所述逻辑芯片和所述存储器芯片被容纳在封装中，以及
其中，所述存储器芯片包括：
存储器芯片测试电路，所述存储器芯片测试电路执行所述存储器芯片的操作测试，以及
串行总线接口电路，所述串行总线接口电路用于在所述存储器芯片测试电路和设置在所述封装外部的串行总线之间发送和接收数据。
2.如权利要求1所述的半导体装置，
其中，所述存储器芯片包括堆叠在彼此之上并且通过贯通电极电耦接到彼此的存储器管芯，以及
其中，所述存储器芯片测试电路和所述串行总线接口电路被设置于所述存储器管芯中的至少一个存储器管芯。
3.如权利要求1所述的半导体装置，
其中，所述存储器芯片包括
基部管芯，所述基部管芯设置于所述存储器芯片的最下层，以及
存储器管芯，所述存储器管芯堆叠在所述基部管芯上并且通过贯通电极电耦接到彼此，以及
其中，所述存储器芯片测试电路和所述串行总线接口电路设置于所述基部管芯。
4.如权利要求3所述的半导体装置，其中，所述基部管芯还包括用于外部耦接的凸块。
5.如权利要求1所述的半导体装置，其中，所述逻辑芯片和所述存储器芯片通过硅插入件耦接。
6.如权利要求1所述的半导体装置，
其中，所述串行总线接口电路包括
用于时钟信号的时钟缓冲器，以及
用于数据信号的数据缓冲器。
7.如权利要求6所述的半导体装置，
其中，所述串行总线接口电路还包括与时钟缓冲器和数据缓冲器耦接的串行链路单元，
其中，所述串行链路单元通过串行总线接收串行时钟和串行数据，并且向存储器芯片测试电路输出测试指令；并且
其中，所述串行链路单元从所述存储器芯片测试电路接收测试结果，并将基于所述测试结果的串行时钟和串行数据输出到所述串行总线。
8.如权利要求5所述的半导体装置，
其中，所述硅插入件被容纳在所述封装中。
9.如权利要求8所述的半导体装置，还包括：
基板，所述基板的一个表面上安装有所述硅插入件，以及
其中，外部封装球设置在所述基板的另一个表面上。
10.一种半导体集成系统，包括：
系统板；
全体控制单元，所述全体控制单元设置在所述系统板上并且控制整个系统板；
多个半导体装置，所述多个半导体装置设置在所述系统板上；以及
串行总线，所述串行总线将所述全体控制单元与所述半导体装置耦接，
其中，每个半导体装置都是在公共封装中安装多个芯片的半导体装置，并且包括
逻辑芯片，所述逻辑芯片具有预定的功能，以及
存储器芯片，所述存储器芯片与所述逻辑芯片耦接并存储数据，以及
其中，所述存储器芯片包括
存储器芯片测试电路，所述存储器芯片测试电路执行所述存储器芯片的操作测试，以及
串行总线接口电路，所述串行总线接口电路用于在所述存储器芯片测试电路和设置在所述封装外部的所述串行总线之间发送和接收数据。
11.如权利要求10所述的半导体集成系统，
其中，识别信息被分配给所述半导体装置中的每个半导体装置，以及
其中，所述全体控制单元根据通过所述串行总线分配的识别信息访问对应半导体装置的存储器芯片，并且指示该存储器芯片执行操作测试。
12.如权利要求11所述的半导体集成系统，
其中，每个半导体装置都设置有多个存储器芯片，
其中，所述识别信息包括高位和低位，以及
其中，所述全体控制单元基于通过所述串行总线分配的高位和低位中的至少任一个来访问半导体装置中的对应半导体装置，基于高位和低位中的另一个来访问所述对应半导体装置中的存储器芯片中的对应存储器芯片，并且指示该存储器芯片执行操作测试。
13.如权利要求10所述的半导体集成系统，
其中，所述存储器芯片包括通过贯通电极电耦接在一起的多个堆叠型存储器管芯，以及
其中，所述存储器芯片测试电路和所述串行总线接口电路设置于所述存储器管芯中的至少一个存储器管芯。
14.一种半导体装置，包括：
插入件；
逻辑芯片，所述逻辑芯片具有预定的功能并且设置在插入件上；和
第一存储器芯片，所述第一存储器芯片包括第一存储器管芯，所述第一存储器管芯存储数据、设置在所述插入件上并且通过所述插入件与所述逻辑芯片耦接，
其中，所述逻辑芯片、所述第一存储器芯片和所述插入件被容纳在封装中，以及
其中，所述第一存储器芯片还包括：
第一测试电路，所述第一测试电路对所述第一存储器芯片执行操作测试，和
第一串行总线接口电路，所述第一串行总线接口电路用于在所述第一测试电路和设置在所述封装外部的串行总线之间发送和接收数据，并且包括用于在所述第一测试电路和所述串行总线之间执行串行数据通信的第一数据端子以及指定用于执行串行数据通信的定时的第一时钟端子。
15.如权利要求14所述的半导体装置，还包括：
第二存储器芯片，所述第二存储器芯片包括第二存储器管芯，所述第二存储器管芯存储数据、设置在所述插入件上、通过所述插入件与所述逻辑芯片耦接并且被容纳在所述封装中，
其中，第二存储器芯片还包括：
第二测试电路，所述第二测试电路对第二存储器芯片执行操作测试，以及
第二串行总线接口电路，所述第二串行总线接口电路在所述第二测试电路和所述串行总线之间发送和接收数据，并且包括用于在所述第二测试电路和所述串行总线之间执行串行数据通信的第二数据端子以及指定用于执行串行数据通信的定时的第二时钟端子。
16.如权利要求15所述的半导体装置，还包括
外部数据端子，所述外部数据端子耦接到所述第一串行总线接口电路的所述第一数据端子和所述第二串行总线接口电路的所述第二数据端子，并且与所述串行总线交换；和
外部时钟端子，所述外部时钟端子耦接到所述第一串行总线接口电路的所述第一时钟端子和所述第二串行总线接口电路的所述第二时钟端子，并且与所述串行总线交换。
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