CN108109962A - The antistatic pinboard of integrated circuit - Google Patents
The antistatic pinboard of integrated circuit Download PDFInfo
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- CN108109962A CN108109962A CN201711352566.0A CN201711352566A CN108109962A CN 108109962 A CN108109962 A CN 108109962A CN 201711352566 A CN201711352566 A CN 201711352566A CN 108109962 A CN108109962 A CN 108109962A
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- silicon
- based substrate
- integrated circuit
- diode
- antistatic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The present invention relates to a kind of antistatic pinboard of integrated circuit, including：Silicon-based substrate 11, TSV holes 12, isolated groove 13, diode 14, plug 15, interconnection line 16, salient point 17 and separation layer 18；The TSV holes 12 are vertically through filling polycrystalline silicon material in the silicon-based substrate 11 and the TSV holes 12；The isolated groove 13 is vertically through filling earth silicon material in the silicon-based substrate 11 and the isolated groove 13；The diode 14 is arranged in the silicon-based substrate 11 and is located at 13 both sides of isolated groove respectively with the TSV holes 12；The separation layer 18 is respectively arranged at the opposite surface of the silicon-based substrate 11；The plug 15 is respectively arranged in the separation layer 18 and positioned at the polycrystalline silicon material, 14 surface of the diode.The antistatic pinboard of integrated circuit provided by the invention enhances the antistatic effect of laminate packaging chip.
Description
Technical field
The present invention relates to semiconductor device design and manufacturing field, more particularly to a kind of antistatic pinboard of integrated circuit.
Background technology
The characteristic size of integrated circuit is down to 7nm so far, and the number of transistors integrated on a single chip is
Through reaching 10,000,000,000 ranks, with the requirement of the number of transistors of 10,000,000,000 ranks, Resources on Chip and interconnection length problem become existing
The bottleneck of modern integrated circuit fields development, 3D integrated circuits are considered as the developing direction of future integrated circuits, its original circuit
On the basis of, it is stacked on Z axis, in the hope of integrating more functions on minimum area, this method overcomes original integrated
The limitation of degree using emerging technology silicon wafer through hole (Through SiliconVias, abbreviation TSV), is greatly improved integrated
The performance of circuit is reduced and postponed on line, reduces chip power-consumption.
Inside semicon industry, with the raising of integrated circuit integrated level and the reduction of device feature size, integrate
Potentiality damage caused by static discharge has become more and more apparent in circuit.According to relevant report, the event of integrated circuit fields
The failure for having nearly 35% in barrier is triggered by Electro-static Driven Comb (Electro-Static discharge, abbreviation ESD), therefore
Chip internal is all designed with esd protection structure to improve the reliability of device.However the antistatic effect of different chips is different,
The weak chip of antistatic effect influences whether the antistatic effect of whole system after encapsulation when three-dimensional stacked, therefore how to improve
The antistatic effect of 3D integrated circuits based on TSV techniques becomes semicon industry urgent problem to be solved.
The content of the invention
To solve technological deficiency and deficiency existing in the prior art, the present invention proposes a kind of antistatic suitable for integrated circuit
Pinboard.
An embodiment provides a kind of antistatic pinboard of integrated circuit, including：Silicon-based substrate 11, TSV
Hole 12, isolated groove 13, diode 14, plug 15, interconnection line 16, salient point 17 and passivation layer 18；
The TSV holes (12) are vertically through filling polysilicon material in the silicon-based substrate (11) and the TSV holes (12)
Material；
The isolated groove (13) is vertically through filling two in the silicon-based substrate (11) and the isolated groove (13)
Silica material；
The diode (14) be arranged in the silicon-based substrate (11) and be located at respectively with the TSV holes (12) it is described every
From groove (13) both sides；
The passivation layer (18) is respectively arranged at the opposite surface of the silicon-based substrate (11)；
The plug (15) is respectively arranged in the passivation layer (18) and positioned at the polycrystalline silicon material, the diode
(14) surface；
The interconnection line (16) is arranged in the passivation layer (18) and through the plug (15) and the polycrystalline silicon material
It is connected with the P areas of the diode (14)；
The salient point (17) is respectively arranged in the passivation layer (18) and through the plug (15) and the polysilicon material
The N areas of material and the diode (14) are connected.
In one embodiment of the invention, the crystal orientation of the silicon-based substrate 11 is (100), (110) or (111), is mixed
Miscellaneous concentration is 1014~1017cm-3, thickness is 450~550 μm.
In one embodiment of the invention, the impurity of the polycrystalline silicon material is phosphorus, doping concentration for 2 ×
1021cm-3。
In one embodiment of the invention, the impurity in the P areas of the diode 14 be boron, doping concentration preferably 5
×1018cm-3。
In one embodiment of the invention, the impurity in the N areas of the diode 14 be phosphorus, doping concentration preferably 5
×1018cm-3。
In another embodiment of the present invention, the plug 15 is tungsten.
In one embodiment of the invention, the interconnection line 16 is copper.
In one embodiment of the invention, the salient point 17 is copper.
In one embodiment of the invention, the passivation layer 18 is silica.
Compared with prior art, the present invention at least has the advantages that：
1st, the antistatic pinboard of integrated circuit provided by the invention, by being processed on TSV pinboards
ESD protection device --- diode enhances the antistatic effect of laminate packaging chip；
2nd, the isolated groove of up/down perforation is used around above-mentioned diode, there is smaller leakage current and is posted
Raw capacitance；
It 3rd, can be since process proposed by the invention can be realized in existing TSV technique platforms
In the case of any fund of addition and equipment investment, increase the antistatic effect of TSV pinboards.
Description of the drawings
Below in conjunction with attached drawing, the specific embodiment of the present invention is described in detail.
Fig. 1 is a kind of structure diagram of the antistatic pinboard of integrated circuit provided in an embodiment of the present invention；
Fig. 2 is a kind of preparation method flow chart of the antistatic pinboard of integrated circuit provided in an embodiment of the present invention；
Fig. 3 a- Fig. 3 h are that a kind of preparation method of antistatic pinboard of integrated circuit provided in an embodiment of the present invention is illustrated
Figure.
Specific embodiment
Further detailed description is done to the present invention with reference to specific embodiment, but embodiments of the present invention are not limited to
This.
Embodiment one
Fig. 1 is referred to, Fig. 1 is a kind of structural representation of the antistatic pinboard of integrated circuit provided in an embodiment of the present invention
Figure, the antistatic pinboard 10 of the integrated circuit include：Silicon-based substrate 11, TSV holes 12, isolated groove 13, diode 14 P areas,
N areas, plug 15, interconnection line 16, salient point 17 and the passivation layer 18 of diode 14；
The TSV holes 12 are vertically through filling polycrystalline silicon material in the silicon-based substrate 11 and the TSV holes 12；
The isolated groove 13 is vertically through filling silica in the silicon-based substrate 11 and the isolated groove 13
Material
The diode 14 is arranged in the silicon-based substrate 11 and is located at the isolated groove respectively with the TSV holes 12
13 both sides；
The passivation layer 18 is respectively arranged at the opposite surface of the silicon-based substrate 11；
The plug 15 is respectively arranged in the passivation layer 18 and positioned at the polycrystalline silicon material, 14 table of the diode
Face；
The interconnection line 16 be arranged in the passivation layer 18 and through the plug 15 and the polycrystalline silicon material with it is described
The P areas of diode 14 are connected；
The salient point 17 is respectively arranged in the passivation layer 18 and through the plug 15 and the polycrystalline silicon material and institute
The N areas for stating diode 14 are connected.
Preferably, the crystal orientation of the silicon-based substrate 11 is 100,110 or 111, doping concentration 1014~1017cm-3, it is thick
It spends for 450~550 μm.
Preferably, the impurity of the polycrystalline silicon material is phosphorus, and doping concentration is 2 × 1021cm-3。
Preferably, the impurity in the P areas of the diode 14 is boron, and doping concentration is 5 × 1018cm-3。
Preferably, the impurity in the N areas of the diode 14 is phosphorus, and doping concentration is 5 × 1018cm-3。
Preferably, the material of the plug 15 is tungsten.
Preferably, the material of the interconnection line 16 and the salient point 17 is copper.
Preferably, the material of the passivation layer 18 is silica.
The antistatic pinboard of integrated circuit provided in this embodiment, by processing ESD protection device on TSV pinboards
Part --- diode enhances the antistatic effect of laminate packaging chip；In addition, using up/down perforation around above-mentioned diode
Isolated groove has smaller leakage current and parasitic capacitance.
Embodiment two
Fig. 2 is refer to, Fig. 2 is a kind of preparation method stream of the antistatic pinboard of integrated circuit provided in an embodiment of the present invention
Cheng Tu, the present embodiment emphasis on the basis of above-described embodiment are described in detail its manufacture craft as follows.
Specifically, which can include：
(a) silicon-based substrate is chosen；
(b) TSV holes and isolated groove are made in the silicon-based substrate；
(c) SiO is utilized2Material fills the isolated groove；
(d) the TSV holes are filled using polycrystalline silicon material, and introduces impurity gas and original position is carried out to the polycrystalline silicon material
Doping；
(e) P areas are made on the silicon-based substrate top, wherein, the P areas are located at described isolate respectively with the TSV holes
Groove both sides；
(f) the silicon-based substrate base portion material is removed, so that the silicon is run through in the TSV holes with the isolated groove
Base substrate；
(g) N areas are made in the silicon-based substrate lower part, wherein, the N areas are located at P areas lower section, the P areas, described
N areas and its between silicon-based substrate formed diode；
(h) metal interconnecting wires are made in the silicon-based substrate so that the polycrystalline silicon material is connected with the diode
It connects, copper bump is made in the polycrystalline silicon material and N areas bottom.
Integral circuit keyset provided in this embodiment by processing diode on pinboard, enhances laminate packaging
The antistatic effect of chip, the weak chip of antistatic effect influences whether the anti-of whole system after encapsulation when solving three-dimensional stacked
The problem of electrostatic capacity；Meanwhile the diode component periphery formed is by SiO2Insulating layer surrounds, and can effectively reduce active area
Parasitic capacitance between substrate.
Embodiment three
Fig. 3 a- Fig. 3 h, Fig. 3 a- Fig. 3 h be refer to as a kind of antistatic pinboard of integrated circuit provided in an embodiment of the present invention
Preparation method schematic diagram, the present embodiment on the basis of above-described embodiment, using the crystal orientation of silicon-based substrate as (100), doping class
Type includes following step the preparation process of the antistatic pinboard of the present invention to be described in detail exemplified by p-type the preparation method
Suddenly：
1st step chooses the p-type silicon-based substrate 21 that crystal orientation is (100)；Its doping concentration is, for example, 1014~1017Cm-3 is thick
Degree for example, 450~550um.As shown in Figure 3a.
2nd step, at a temperature of 1050~1100 DEG C, using thermal oxidation technology, growth thickness is in the silicon-based substrate
The silicon dioxide layer of 800~1000nm；Using photoetching process, the first region to be etched and the is made in the silicon dioxide layer
Two regions to be etched；Using deep reaction ion etch process, in the described first region to be etched and the described second area to be etched
Domain etches the silicon-based substrate, is respectively formed the TSV holes 22 and the isolated groove 23；It is gone using CMP process
Planarization process is carried out except silicon dioxide layer and to silicon-based substrate surface, as shown in Figure 3b.
3rd step, using thermal oxidation technology, in the TSV holes and isolated groove so that the inner wall of blind hole forms oxide layer；Its
In, oxidate temperature is 1050~1100 DEG C, and the thickness of oxide layer is 200~300nm；Utilize wet-etching technology, selectivity
The oxide layer is etched so that the TSV holes and the isolated groove inner wall are smooth；Using photoetching process, in the silicon-based substrate
Surface forms isolated groove filling region；At a temperature of 690~710 DEG C, using chemical vapor deposition method, in the isolating trenches
Slot filling region deposits silica to be filled to the isolated groove, as shown in Figure 3c.
4th step, using photoetching process, TSV holes filling region is formed on the silicon-based substrate surface；In 600~620 DEG C of temperature
Under degree, using chemical vapor deposition method, in the TSV holes filling region depositing polysilicon material with to TSV holes progress
Filling, and impurity gas is introduced to carry out doping in situ to the polycrystalline silicon material；Wherein, polycrystalline silicon material doping concentration is preferred
For 2 × 1021cm-3, the preferred phosphorus of impurity, as shown in Figure 3d.
5th step, using CMP process, planarizing process is carried out to the silicon-based substrate upper surface；Utilize light
Carving technology, selective etch photoresist form the first ion region to be implanted in the silicon-based substrate upper surface；Described first
Ion region to be implanted mixes boron ion to form the p type island region domain 24 on the silicon-based substrate top；Wherein, the p type island region domain
24 doping concentration preferably 5 × 1018cm-3, the preferred boron of impurity, as shown in Figure 3 e.
6th step, using mechanical grinding technique, remove the silicon-based substrate low portion material；Utilize chemically mechanical polishing
Technique carries out planarizing process to the silicon-based substrate lower surface, makes the TSV holes 22 with the isolated groove 23 through described
Silicon-based substrate；Wherein, the silicon-based substrate thickness of remainder is preferably 300 μm~400 μm, as illustrated in figure 3f.
7th step utilizes photoetching process, selective etch photoresist, in the second ion of silicon-based substrate upper surface formation
Region to be implanted；Phosphonium ion is mixed in second ion region to be implanted to form the N-type in the silicon-based substrate lower part
Region 25, at a temperature of 950~1100 DEG C, to entire 15~120s of anneal of material, by mixed impurity activation；Wherein, N-type
Region dopant concentration preferably 5 × 1018cm-3, the preferred phosphorus of impurity, the p type island region domain, the N-type region domain and its between silicon
Base substrate forms diode, as shown in figure 3g.
8th step makes plug 26 and lower plug 27 respectively in the polycrystalline silicon material and the diode upper and lower surface；
26 surface of plug makes the metal interconnecting wires so that the polycrystalline silicon material is formed with the diode serially connects on described
It connects；The salient point 28 is made in the lower plug surface, as illustrated in figure 3h；Wherein, while using metal interconnecting wires it is surrounded by
Helical form and make it have the characteristic of inductance to be more particularly for the electrostatic protection of RF IC.
It should be noted that isolated groove is to separate diode and the connection of other structures in pinboard, therefore isolate
Groove can be made as enclosed construction (such as cyclic structure) and through substrate material, and diode is located inside the enclosed construction.
The above content is a further detailed description of the present invention in conjunction with specific preferred embodiments, it is impossible to assert
The specific implementation of the present invention is confined to these explanations.For those of ordinary skill in the art to which the present invention belongs, exist
On the premise of not departing from present inventive concept, several simple deduction or replace can also be made, should all be considered as belonging to the present invention's
Protection domain.
Claims (9)
1. a kind of antistatic pinboard of integrated circuit (10), which is characterized in that including：Silicon-based substrate (11), TSV holes (12), every
From groove (13), diode (14), plug (15), interconnection line (16), salient point (17) and passivation layer (18)；
The TSV holes (12) are vertically through filling polycrystalline silicon material in the silicon-based substrate (11) and the TSV holes (12)；
The isolated groove (13) is vertically through filling titanium dioxide in the silicon-based substrate (11) and the isolated groove (13)
Silicon materials；
The diode (14) is arranged in the silicon-based substrate (11) and is located at the isolating trenches respectively with the TSV holes (12)
Slot (13) both sides；
The passivation layer (18) is respectively arranged at the opposite surface of the silicon-based substrate (11)；
The plug (15) is respectively arranged in the passivation layer (18) and positioned at the polycrystalline silicon material, the diode (14)
Surface；
The interconnection line (16) is arranged in the passivation layer (18) and through the plug (15) and the polycrystalline silicon material and institute
The P areas for stating diode (14) are connected；
The salient point (17) be respectively arranged in the passivation layer (18) and through the plug (15) and the polycrystalline silicon material and
The N areas of the diode (14) are connected.
2. the antistatic pinboard of integrated circuit according to claim 1, which is characterized in that the crystalline substance of the silicon-based substrate (11)
To for (100), (110) or (111), doping concentration 1014~1017cm-3, thickness is 450~550 μm.
3. the antistatic pinboard of integrated circuit according to claim 1, which is characterized in that the doping of the polycrystalline silicon material
Impurity is phosphorus, and doping concentration is 2 × 1021cm-3。
4. the antistatic pinboard of integrated circuit according to claim 1, which is characterized in that the P areas of the diode (14)
Impurity for boron, doping concentration is 5 × 1018cm-3。
5. the antistatic pinboard of integrated circuit according to claim 1, which is characterized in that the N areas of the diode (14)
Impurity for phosphorus, doping concentration is 5 × 1018cm-3。
6. the antistatic pinboard of integrated circuit according to claim 1, which is characterized in that the material of the plug (15) is
Tungsten.
7. the antistatic pinboard of integrated circuit according to claim 1, which is characterized in that the material of the interconnection line (16)
For copper.
8. the antistatic pinboard of integrated circuit according to claim 1, which is characterized in that the material of the salient point (17) is
Copper.
9. the antistatic pinboard of integrated circuit according to claim 1, which is characterized in that the material of the passivation layer (18)
For silica.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711352566.0A CN108109962A (en) | 2017-12-15 | 2017-12-15 | The antistatic pinboard of integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711352566.0A CN108109962A (en) | 2017-12-15 | 2017-12-15 | The antistatic pinboard of integrated circuit |
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| Publication Number | Publication Date |
|---|---|
| CN108109962A true CN108109962A (en) | 2018-06-01 |
Family
ID=62217432
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201711352566.0A Withdrawn CN108109962A (en) | 2017-12-15 | 2017-12-15 | The antistatic pinboard of integrated circuit |
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| CN102598254A (en) * | 2009-10-23 | 2012-07-18 | 新思科技有限公司 | ESD/antenna diodes for through-silicon vias |
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| US20140203367A1 (en) * | 2013-01-21 | 2014-07-24 | United Microelectronics Corp. | Transistor Structure for Electrostatic Discharge Protection |
| US20150048497A1 (en) * | 2013-08-16 | 2015-02-19 | Qualcomm Incorporated | Interposer with electrostatic discharge protection |
| CN105190888A (en) * | 2013-05-06 | 2015-12-23 | 高通股份有限公司 | Electrostatic discharge diode |
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-
2017
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| CN1841651A (en) * | 2005-03-29 | 2006-10-04 | 三洋电机株式会社 | Semiconductor device manufacturing method |
| CN102362349A (en) * | 2009-03-26 | 2012-02-22 | 国际商业机器公司 | Esd network circuit with a through wafer via structure and a method of manufacture |
| CN101540320A (en) * | 2009-04-21 | 2009-09-23 | 上海宏力半导体制造有限公司 | Static discharge protection diode |
| CN102598254A (en) * | 2009-10-23 | 2012-07-18 | 新思科技有限公司 | ESD/antenna diodes for through-silicon vias |
| US20130119502A1 (en) * | 2011-11-16 | 2013-05-16 | Analog Devices, Inc. | Electrical overstress protection using through-silicon-via (tsv) |
| US20140203367A1 (en) * | 2013-01-21 | 2014-07-24 | United Microelectronics Corp. | Transistor Structure for Electrostatic Discharge Protection |
| CN105190888A (en) * | 2013-05-06 | 2015-12-23 | 高通股份有限公司 | Electrostatic discharge diode |
| US20150048497A1 (en) * | 2013-08-16 | 2015-02-19 | Qualcomm Incorporated | Interposer with electrostatic discharge protection |
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