CN108321145A - Integral circuit keyset and preparation method thereof - Google Patents
Integral circuit keyset and preparation method thereof Download PDFInfo
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- CN108321145A CN108321145A CN201711351066.5A CN201711351066A CN108321145A CN 108321145 A CN108321145 A CN 108321145A CN 201711351066 A CN201711351066 A CN 201711351066A CN 108321145 A CN108321145 A CN 108321145A
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- 238000002360 preparation method Methods 0.000 title claims abstract description 23
- 239000000758 substrate Substances 0.000 claims abstract description 62
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 60
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 60
- 239000010703 silicon Substances 0.000 claims abstract description 60
- 239000002210 silicon-based material Substances 0.000 claims abstract description 45
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 41
- 238000011049 filling Methods 0.000 claims abstract description 29
- 239000000463 material Substances 0.000 claims abstract description 15
- 239000012535 impurity Substances 0.000 claims abstract description 12
- 229910052751 metal Inorganic materials 0.000 claims abstract description 12
- 239000002184 metal Substances 0.000 claims abstract description 12
- 238000011065 in-situ storage Methods 0.000 claims abstract description 6
- 238000000034 method Methods 0.000 claims description 72
- 230000008569 process Effects 0.000 claims description 30
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 26
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 19
- 229910052721 tungsten Inorganic materials 0.000 claims description 19
- 239000010937 tungsten Substances 0.000 claims description 19
- 238000001259 photo etching Methods 0.000 claims description 16
- 238000005516 engineering process Methods 0.000 claims description 14
- 239000000377 silicon dioxide Substances 0.000 claims description 13
- 238000000151 deposition Methods 0.000 claims description 9
- 238000005229 chemical vapour deposition Methods 0.000 claims description 8
- 230000003647 oxidation Effects 0.000 claims description 8
- 238000007254 oxidation reaction Methods 0.000 claims description 8
- 235000012239 silicon dioxide Nutrition 0.000 claims description 8
- 230000008021 deposition Effects 0.000 claims description 6
- 238000002955 isolation Methods 0.000 claims description 6
- 238000006243 chemical reaction Methods 0.000 claims description 4
- 238000000227 grinding Methods 0.000 claims description 4
- 238000001039 wet etching Methods 0.000 claims description 4
- 229920005591 polysilicon Polymers 0.000 claims description 3
- 238000000926 separation method Methods 0.000 claims description 2
- 241000790917 Dioxys <bee> Species 0.000 claims 1
- 229910003978 SiClx Inorganic materials 0.000 claims 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 8
- 229910052802 copper Inorganic materials 0.000 abstract description 8
- 239000010949 copper Substances 0.000 abstract description 8
- 230000000694 effects Effects 0.000 abstract description 7
- 238000004806 packaging method and process Methods 0.000 abstract description 3
- 239000007789 gas Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 239000013049 sediment Substances 0.000 description 4
- 239000013078 crystal Substances 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 230000007812 deficiency Effects 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 125000004122 cyclic group Chemical group 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Geometry (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Element Separation (AREA)
Abstract
The present invention relates to a kind of Integral circuit keyset and preparation method thereof, which includes：Choose silicon-based substrate；The holes TSV, isolated groove and device trenches are made in silicon-based substrate, wherein isolated groove is between the holes TSV and device trenches；Isolated groove is filled using earth silicon material；Using the holes polycrystalline silicon material filling TSV, and introduces impurity gas and doping in situ is carried out to polycrystalline silicon material；Diode is made in device trenches；Metal interconnecting wires are made so that polycrystalline silicon material is connected with diode in the anode surface of polycrystalline silicon material upper surface and diode；Silicon-based substrate base portion material is removed, silicon-based substrate bottom is made to expose the holes TSV and isolated groove；Copper bump is made in polycrystalline silicon material and n-type region bottom.Integral circuit keyset provided by the invention enhances the antistatic effect of laminate packaging chip by processing ESD protection diode on TSV pinboards.
Description
Technical field
The present invention relates to semiconductor device design and manufacturing field, more particularly to a kind of Integral circuit keyset and its preparation
Method.
Background technology
The characteristic size of integrated circuit is down to 7nm so far, and the number of transistors integrated on a single chip is
Through reaching 10,000,000,000 ranks, with the requirement of the number of transistors of 10,000,000,000 ranks, Resources on Chip and interconnection length problem become existing
The bottleneck of modern integrated circuit fields development, 3D integrated circuits are considered as the developing direction of future integrated circuits, its original circuit
On the basis of, it is laminated on Z axis, in the hope of integrating more functions on minimum area, this method overcomes original integrated
Collection is greatly improved using emerging technology silicon wafer through hole (Through Silicon Vias, abbreviation TSV) in the limitation of degree
It at the performance of circuit, reduces and postpones on line, reduce chip power-consumption.
Inside semicon industry, with the raising of integrated circuit integrated level and the reduction of device feature size, integrate
Potentiality damage caused by static discharge has become to be more and more obvious in circuit.According to relevant report, the event of integrated circuit fields
The failure for having nearly 35% in barrier is caused by Electro-static Driven Comb (Electro-Static discharge, abbreviation ESD), therefore
Chip interior is all designed with esd protection structure to improve the reliability of device.However the antistatic effect of different chips is different,
The weak chip of antistatic effect influences whether the antistatic effect of whole system after encapsulation when three-dimensional stacked, therefore how to improve
The antistatic effect of 3D integrated circuits based on TSV techniques becomes semicon industry urgent problem to be solved.
Invention content
To solve technological deficiency and deficiency of the existing technology, a kind of Integral circuit keyset of present invention proposition and its system
Preparation Method.The preparation method includes：
(a) silicon-based substrate is chosen；
(b) holes TSV, isolated groove and device trenches are made in the silicon-based substrate, wherein the isolated groove is located at
Between the holes TSV and the device trenches；
(c) earth silicon material is utilized to fill the isolated groove；
(d) it utilizes polycrystalline silicon material to fill the holes TSV, and introduces impurity gas and original position is carried out to the polycrystalline silicon material
Doping；
(e) diode is made in the device trenches；
(f) metal interconnecting wires are made so that described in the anode surface of the polycrystalline silicon material upper surface and the diode
Polycrystalline silicon material is connected with the diode；
(g) remove the silicon-based substrate base portion material, make the silicon-based substrate bottom expose the holes TSV with it is described
Isolated groove；
(h) copper bump is made in the polycrystalline silicon material and the n-type region bottom.
In one embodiment of the invention, step (b) includes：
(b1) thermal oxidation technology is utilized, grows silicon dioxide layer in the silicon-based substrate；
(b2) photoetching process is utilized, the first region to be etched of making, the second region to be etched in the silicon dioxide layer
And third region to be etched；
(b3) deep reaction ion etch process is utilized, in the described first region to be etched, second region to be etched
And silicon-based substrate described in the third region etch to be etched, it is respectively formed the holes TSV, the isolated groove and the device
Groove.
In one embodiment of the invention, further include before step (c)：
(x1) thermal oxidation technology is utilized, oxygen is formed in the inner wall of the holes TSV, the isolated groove and the device trenches
Change layer；
(x2) utilize wet-etching technology, oxide layer described in selective etch so that the holes TSV, the isolated groove and
The inner wall of the device trenches is smooth.
In one embodiment of the invention, step (c) includes：
(c1) photoetching process is utilized, isolated groove filling region is formed on the silicon-based substrate surface；
(c2) chemical vapor deposition method is utilized, is deposited in the isolated groove by the isolated groove filling region
Silica.
In one embodiment of the invention, step (d) includes：
(d1) photoetching process is utilized, the holes TSV filling region is formed on the silicon-based substrate surface；
(d2) utilize chemical vapor deposition method, by the holes TSV filling region in the holes TSV depositing polysilicon
Material, and introduce impurity gas and doping in situ is carried out to the polycrystalline silicon material.
In one embodiment of the invention, step (e) includes：
(e1) photoetching process is utilized, device trench fill region is formed on the silicon-based substrate surface；
(e2) CVD techniques and ion doping technique are utilized, by the device trenches filling region in the device trenches
Bottom deposition thickness is 20 μm~40 μm, doping concentration is 5 × 1018cm-3The areas N+；
(e3) CVD techniques and ion doping technique are utilized, is formed sediment in the areas N+ by the device trenches filling region
Product thickness is 40 μm~80 μm, doping concentration is 2 × 1014cm-3The areas N-；
(e4) CVD techniques and ion doping technique are utilized, is formed sediment in the areas N- by the device trenches filling region
Product thickness is 20 μm~40 μm, doping concentration is 5 × 1018cm-3The areas P+, wherein the areas N+, the areas N- and the P+
Area forms the diode.
In another embodiment of the present invention, step (f) includes：
(f1) upper tungsten plug is made in the polycrystalline silicon material and the areas P+ surface；
(f2) metal interconnecting wires are made so that the polycrystalline silicon material and two pole on the upper tungsten plug surface
Pipe is connected.
In one embodiment of the invention, step (g) includes：
(g1) mechanical grinding technique is utilized, the silicon-based substrate low portion material is removed；
(g2) CMP process is utilized, planarizing process is carried out to the silicon-based substrate lower surface, makes the silicon
Expose the holes TSV, the isolated groove and the areas N+ in base substrate bottom.
In one embodiment of the invention, step (h) includes：
(h1) tungsten plug in the case where the polycrystalline silicon material and the areas N+ lower surface make；
(h2) copper bump is made on the lower tungsten plug surface.
In another embodiment of the present invention, a kind of Integral circuit keyset is provided, the Integral circuit keyset packet
Include silicon-based substrate, the holes TSV, isolation channel, diode, tungsten plug, metal interconnecting wires, copper bump and separation layer；Wherein, described integrated
Adapter plate for circuit is prepared by method described in any one of the above embodiments and is formed.
Compared with prior art, the present invention at least has the advantages that：
1, the preparation process of Integral circuit keyset provided by the invention, processing step is simple, and feasibility is high；
2, Integral circuit keyset provided by the invention, by processing ESD protection device --- two poles on TSV pinboards
Pipe, enhances the antistatic effect of laminate packaging chip；In addition, isolated groove up and down is used around above-mentioned diode,
With smaller leakage current and parasitic capacitance.
Description of the drawings
Below in conjunction with attached drawing, the specific implementation mode of the present invention is described in detail.
Fig. 1 is a kind of preparation method flow chart of Integral circuit keyset provided in an embodiment of the present invention；
Fig. 2 a- Fig. 2 i are a kind of preparation method schematic diagram of Integral circuit keyset provided in an embodiment of the present invention；
Fig. 3 is a kind of structural schematic diagram of Integral circuit keyset provided in an embodiment of the present invention.
Specific implementation mode
Further detailed description is done to the present invention with reference to specific embodiment, but embodiments of the present invention are not limited to
This.
Embodiment one
Fig. 1 is referred to, Fig. 1 is a kind of preparation method flow chart of Integral circuit keyset provided in an embodiment of the present invention,
The preparation method includes：
(a) silicon-based substrate is chosen；
(b) holes TSV, isolated groove and device trenches are made in the silicon-based substrate, wherein the isolated groove is located at
Between the holes TSV and the device trenches；
(c) earth silicon material is utilized to fill the isolated groove；
(d) it utilizes polycrystalline silicon material to fill the holes TSV, and introduces impurity gas and original position is carried out to the polycrystalline silicon material
Doping；
(e) diode is made in the device trenches；
(f) metal interconnecting wires are made so that described in the anode surface of the polycrystalline silicon material upper surface and the diode
Polycrystalline silicon material is connected with the diode；
(g) remove the silicon-based substrate base portion material, make the silicon-based substrate bottom expose the holes TSV with it is described
Isolated groove；
(h) copper bump is made in the polycrystalline silicon material and the n-type region bottom.
Preferably, the crystal orientation of the silicon-based substrate can be (100) either (110) or (111), not do any limit herein
System, in addition, the doping type of substrate can be N-type, can also be for p-type, doping concentration is, for example, 1014~1017cm-3, thickness
For example, 450~550 μm.
Further, on the basis of the above embodiments, step (b) includes：
(b1) at a temperature of 1050 DEG C~1100 DEG C, using thermal oxidation technology, growth thickness is in the silicon-based substrate
800nm~1000nm silicon dioxide layers；
(b2) photoetching process is utilized, the first region to be etched of making, the second region to be etched in the silicon dioxide layer
And third region to be etched；
(b3) deep reaction ion etch process is utilized, in the described first region to be etched, second region to be etched
And silicon-based substrate described in the third region etch to be etched, it is respectively formed the holes TSV, the isolated groove and the device
Groove.
Further, on the basis of the above embodiments, further include before step (c)：
(x1) at a temperature of 1050 DEG C~1100 DEG C, using thermal oxidation technology, the holes TSV, the isolated groove and
The inner wall of the device trenches forms the oxide layer that thickness is 200nm~300nm；
(x2) utilize wet-etching technology, oxide layer described in selective etch so that the holes TSV, the isolated groove and
The inner wall of the device trenches is smooth.The step is the holes TSV, the isolated groove and the device trenches side wall in order to prevent
Protrusion forms electric field concentrated area.
Further, on the basis of the above embodiments, step (c) includes：
(c1) photoetching process is utilized, isolated groove filling region is formed on the silicon-based substrate surface；
(c2) at a temperature of 690 DEG C~710 DEG C, using chemical vapor deposition method, pass through the isolated groove fill area
Domain deposits silica in the isolated groove.In this step, silica mainly plays isolating device, it is also possible to
Other isolated materials replace.
Further, on the basis of the above embodiments, step (d) includes：
(d1) photoetching process is utilized, the holes TSV filling region is formed on the silicon-based substrate surface；
(d2) at a temperature of 600~620 DEG C, using chemical vapor deposition method, in the holes TSV, filling region deposit is more
Crystal silicon material introduces impurity gas to carry out doping in situ to the polycrystalline silicon material to be filled to the holes TSV；Its
In, polycrystalline silicon material doping concentration is preferably 2 × 1021cm-3, the preferred phosphorus of impurity.The purpose of this step is in order in TSV
Impurity Distribution is formed in hole uniformly and the conductive material of high-dopant concentration is filled, and is conducive to reduce the resistance in the holes TSV.
Further, on the basis of the above embodiments, step (e) includes：
(e1) photoetching process is utilized, device trench fill region is formed on the silicon-based substrate surface；
(e2) CVD techniques and ion doping technique are utilized, by the device trenches filling region in the device trenches
Bottom deposition thickness is 20 μm~40 μm, doping concentration is 5 × 1018cm-3The areas N+；
(e3) CVD techniques and ion doping technique are utilized, is formed sediment in the areas N+ by the device trenches filling region
Product thickness is 40 μm~80 μm, doping concentration is 2 × 1014cm-3The areas N-；
(e4) CVD techniques and ion doping technique are utilized, is formed sediment in the areas N- by the device trenches filling region
Product thickness is 20 μm~40 μm, doping concentration is 5 × 1018cm-3The areas P+.
Wherein, the areas N+, the areas N- and the areas P+ form the diode.
Further, on the basis of the above embodiments, step (f) includes：
(f1) upper tungsten plug is made in the polycrystalline silicon material and the areas P+ surface；
(f2) metal interconnecting wires are made so that the polycrystalline silicon material and two pole on the upper tungsten plug surface
Pipe is connected.
Further, on the basis of the above embodiments, step (g) includes：
(g1) mechanical grinding technique is utilized, the silicon-based substrate low portion material is removed；The silicon-based substrate of remainder
Thickness be slightly larger than 10 μm of target size；
(g2) CMP process is utilized, planarizing process is carried out to the silicon-based substrate lower surface, makes the silicon
Expose the holes TSV, the isolated groove and the areas N+ in base substrate bottom.After the step process, the thickness of silicon-based substrate
Reach target thickness, preferably 80 μm~120 μm.
Further, on the basis of the above embodiments, step (h) includes：
(h1) tungsten plug in the case where the polycrystalline silicon material and the areas N+ lower surface make；
(h2) copper bump is made on the lower tungsten plug surface.
Integral circuit keyset provided in this embodiment is used as ESD protection device by processing diode on TSV pinboards
Part enhances the antistatic effect of laminate packaging chip；In addition, isolated groove up and down is used around above-mentioned diode,
With smaller leakage current and parasitic capacitance.
Embodiment two
It is a kind of preparation of Integral circuit keyset provided in an embodiment of the present invention to please refer to Fig. 2 a- Fig. 2 i, Fig. 2 a- Fig. 2 i
Method schematic diagram, the preparation method include the following steps：
1st step chooses silicon-based substrate 21；The crystal orientation of the silicon-based substrate 21 can be (100) either (110) or
(111), no limitations are hereby intended, in addition, the doping type of substrate can be N-type, can also be for p-type, doping concentration example
Such as it is 1014~1017Cm-3, thickness are, for example, 450~550 μm.As shown in Figure 2 a.
2nd step, at a temperature of 1050 DEG C~1100 DEG C, using thermal oxidation technology, grown in the silicon-based substrate 21 thick
Degree is 800nm~1000nm silicon dioxide layers；Using photoetching process, the first area to be etched is made in the silicon dioxide layer
Domain, the second region to be etched and third region to be etched；Using deep reaction ion etch process, in the described first area to be etched
Silicon-based substrate 21 described in domain, second region to be etched and third region etch to be etched, is respectively formed the holes TSV
22, the isolated groove 23 and the isolated groove 24, as shown in Figure 2 b.
3rd step, at a temperature of 1050 DEG C~1100 DEG C, using thermal oxidation technology, in the holes TSV 22, the isolating trenches
The inner wall of slot 23 and the isolated groove 24 forms oxide layer；Using wet-etching technology, oxide layer described in selective etch with
Keep the inner wall of the holes TSV 22, the isolated groove 23 and the isolated groove 24 smooth, as shown in Figure 2 c.The step be for
Prevent the protrusion of the holes TSV 22, the isolated groove 23 and the isolated groove 24 side wall from forming electric field concentrated area.
4th step, using photoetching process, form 23 filling region of isolated groove on 21 surface of the silicon-based substrate；At 690 DEG C
At a temperature of~710 DEG C, using chemical vapor deposition method, by 23 filling region of the isolated groove in the isolated groove 23
Interior deposit silica.In this step, silica mainly plays isolating device, it is also possible to other isolated material generations
It replaces, as shown in Figure 2 d.
5th step, using photoetching process, form 22 filling region of the holes TSV on 21 surface of the silicon-based substrate；600~620
At a temperature of DEG C, using chemical vapor deposition method, in the holes TSV, 22 filling region depositing polysilicon material is with to the TSV
Hole 22 is filled, and introduces impurity gas to carry out doping in situ to the polycrystalline silicon material；Wherein, polycrystalline silicon material adulterates
Concentration is preferably 2 × 1021cm-3, the preferred phosphorus of impurity.The purpose of this step is to form Impurity Distribution in the holes TSV 22
Uniformly and the conductive material of high-dopant concentration is filled, and is conducive to reduce the resistance in the holes TSV 22, as shown in Figure 2 e.
6th step, using photoetching process, form 24 filling region of isolated groove on 21 surface of the silicon-based substrate；Utilize CVD
Technique and ion doping technique in 24 bottom deposition thickness of the isolated groove are 20 by 24 filling region of the isolated groove
μm~40 μm, doping concentration be 5 × 1018cm-3The areas N+ 25；Using CVD techniques and ion doping technique, pass through the isolation
24 filling region of groove deposition thickness in the areas N+ is 40 μm~80 μm, doping concentration is 2 × 1014cm-3The areas N- 26；
Using CVD techniques and ion doping technique, by 24 filling region of the isolated groove, deposition thickness is 20 μ in the areas N-
M~40 μm, doping concentration are 5 × 1018cm-3The areas P+ 27.Wherein, the areas N+ 25, the areas N- 26 and 27 shape of the areas P+
At the diode, as shown in figure 2f.
7th step makes upper tungsten plug 28 in the polycrystalline silicon material and 27 surface of the areas P+；In the upper tungsten plug 28
Surface makes the metal interconnecting wires 29 so that the polycrystalline silicon material is connected with the diode, as shown in Figure 2 g；Wherein,
Simultaneously using metal interconnecting wires around spiral and make it have the characteristic of inductance to be more particularly for RF IC
Electrostatic protection.
8th step, using mechanical grinding technique, remove 21 low portion material of the silicon-based substrate；The silicon substrate of remainder
The thickness of substrate 21 is slightly larger than 10 μm of target size；Using CMP process, to 21 lower surface of the silicon-based substrate into
Row planarizing process makes 21 bottom of the silicon-based substrate expose the holes TSV 22, the isolated groove 23 and the areas N+ 25.
After the step process, the thickness of silicon-based substrate 21 reaches target thickness, preferably 80 μm~120 μm, as shown in fig. 2h.
9th step, the tungsten plug 30 in the case where the polycrystalline silicon material and 25 lower surface of the areas N+ make；In the lower tungsten plug
30 surfaces make the copper bump 31, as shown in fig. 2i.
It should be noted that isolated groove is to separate the connection of diode and other structures in pinboard, therefore it is isolated
Groove can be made as enclosed construction (such as cyclic structure) and run through substrate material, and diode is located inside the enclosed construction.
Embodiment three
Fig. 3 is please referred to, Fig. 3 is a kind of structural schematic diagram of Integral circuit keyset provided in an embodiment of the present invention.The collection
It prepares to be formed using the preparation method described in above-described embodiment at adapter plate for circuit.Specifically, the Integral circuit keyset packet
It includes：Silicon-based substrate 31, the holes TSV 32, isolation channel 33, diode 34, tungsten plug 35, metal interconnecting wires 36, copper bump 37 and isolation
Layer 38；Wherein, polycrystalline silicon material is filled in the holes TSV 32, and earth silicon material is filled in isolation channel 33.
The above content is a further detailed description of the present invention in conjunction with specific preferred embodiments, and it cannot be said that
The specific implementation of the present invention is confined to these explanations.For those of ordinary skill in the art to which the present invention belongs, exist
Under the premise of not departing from present inventive concept, a number of simple deductions or replacements can also be made, all shall be regarded as belonging to the present invention's
Protection domain.
Claims (10)
1. a kind of preparation method of Integral circuit keyset, which is characterized in that including：
(a) silicon-based substrate is chosen；
(b) holes TSV, isolated groove and device trenches are made in the silicon-based substrate, wherein the isolated groove is located at described
Between the holes TSV and the device trenches；
(c) earth silicon material is utilized to fill the isolated groove；
(d) it utilizes polycrystalline silicon material to fill the holes TSV, and introduces impurity gas and in situ mix is carried out to the polycrystalline silicon material
It is miscellaneous；
(e) diode is made in the device trenches；
(f) metal interconnecting wires are made so that the polycrystalline in the anode surface of the polycrystalline silicon material upper surface and the diode
Silicon materials are connected with the diode；
(g) the silicon-based substrate base portion material is removed, so that the silicon-based substrate bottom is exposed the holes TSV and is isolated with described
Groove；
(h) salient point is made in the polycrystalline silicon material and the n-type region bottom.
2. preparation method according to claim 1, which is characterized in that step (b) includes：
(b1) CVD techniques are utilized, grow silicon dioxide layer in the silicon-based substrate；
(b2) photoetching process is utilized, the first region to be etched, the second region to be etched and the are made in the silicon dioxide layer
Three regions to be etched；
(b3) deep reaction ion etch process is utilized, in the described first region, second region to be etched and institute to be etched
Silicon-based substrate described in third region etch to be etched is stated, the holes TSV, the isolated groove and the device ditch are respectively formed
Slot.
3. preparation method according to claim 1, which is characterized in that further include before step (c)：
(x1) thermal oxidation technology is utilized, oxidation is formed in the inner wall of the holes TSV, the isolated groove and the device trenches
Layer；
(x2) wet-etching technology is utilized, oxide layer described in selective etch is so that the holes TSV, the isolated groove and described
The inner wall of device trenches is smooth.
4. preparation method according to claim 1, which is characterized in that step (c) includes：
(c1) photoetching process is utilized, isolated groove filling region is formed on the silicon-based substrate surface；
(c2) chemical vapor deposition method is utilized, dioxy is deposited in the isolated groove by the isolated groove filling region
SiClx.
5. preparation method according to claim 1, which is characterized in that step (d) includes：
(d1) photoetching process is utilized, the holes TSV filling region is formed on the silicon-based substrate surface；
(d2) utilize chemical vapor deposition method, by the holes TSV filling region in the holes TSV depositing polysilicon material
Material, and introduce impurity gas and doping in situ is carried out to the polycrystalline silicon material.
6. preparation method according to claim 1, which is characterized in that step (e) includes：
(e1) photoetching process is utilized, device trench fill region is formed on the silicon-based substrate surface；
(e2) CVD techniques and ion doping technique are utilized, by the device trenches filling region in the device trenches bottom
Deposition thickness is 20 μm~40 μm, doping concentration is 5 × 1018cm-3The areas N+；
(e3) CVD techniques and ion doping technique are utilized, deposits thickness in the areas N+ by the device trenches filling region
Degree is 40 μm~80 μm, doping concentration is 2 × 1014cm-3The areas N-；
(e4) CVD techniques and ion doping technique are utilized, deposits thickness in the areas N- by the device trenches filling region
Degree is 20 μm~40 μm, doping concentration is 5 × 1018cm-3The areas P+, wherein the areas N+, the areas N- and the areas P+ shape
At the diode.
7. preparation method according to claim 6, which is characterized in that step (f) includes：
(f1) upper tungsten plug is made in the polycrystalline silicon material and the areas P+ surface；
(f2) metal interconnecting wires are made so that the polycrystalline silicon material and the diode phase on the upper tungsten plug surface
Connection.
8. preparation method according to claim 6, which is characterized in that step (g) includes：
(g1) mechanical grinding technique is utilized, the silicon-based substrate low portion material is removed；
(g2) CMP process is utilized, planarizing process is carried out to the silicon-based substrate lower surface, the silicon substrate is made to serve as a contrast
Expose the holes TSV, the isolated groove and the areas N+ in bottom bottom.
9. preparation method according to claim 6, which is characterized in that step (h) includes：
(h1) tungsten plug in the case where the polycrystalline silicon material and the areas N+ lower surface make；
(h2) salient point is made on the lower tungsten plug surface.
10. a kind of Integral circuit keyset, which is characterized in that including silicon-based substrate, the holes TSV, isolation channel, diode, tungsten plug,
Metal interconnecting wires, salient point and separation layer；Wherein, the Integral circuit keyset is by claim 1~9 any one of them method
It prepares and is formed.
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Application publication date: 20180724 |