CN108109961A - Antistatic pinboard of integrated circuit based on diode and preparation method thereof - Google Patents
Antistatic pinboard of integrated circuit based on diode and preparation method thereof Download PDFInfo
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- CN108109961A CN108109961A CN201711352556.7A CN201711352556A CN108109961A CN 108109961 A CN108109961 A CN 108109961A CN 201711352556 A CN201711352556 A CN 201711352556A CN 108109961 A CN108109961 A CN 108109961A
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- 238000002360 preparation method Methods 0.000 title claims abstract description 25
- 239000000758 substrate Substances 0.000 claims abstract description 54
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 46
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 46
- 239000010703 silicon Substances 0.000 claims abstract description 46
- 239000000463 material Substances 0.000 claims abstract description 27
- 229910052751 metal Inorganic materials 0.000 claims abstract description 12
- 239000002184 metal Substances 0.000 claims abstract description 12
- 238000000034 method Methods 0.000 claims description 91
- 230000008569 process Effects 0.000 claims description 60
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 48
- 229920005591 polysilicon Polymers 0.000 claims description 48
- 238000005229 chemical vapour deposition Methods 0.000 claims description 32
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 22
- 229910052802 copper Inorganic materials 0.000 claims description 22
- 239000010949 copper Substances 0.000 claims description 22
- 238000002161 passivation Methods 0.000 claims description 19
- 238000011049 filling Methods 0.000 claims description 16
- 238000001259 photo etching Methods 0.000 claims description 16
- 239000002210 silicon-based material Substances 0.000 claims description 14
- 238000011065 in-situ storage Methods 0.000 claims description 12
- 238000000151 deposition Methods 0.000 claims description 7
- 230000008021 deposition Effects 0.000 claims description 7
- 238000007747 plating Methods 0.000 claims description 7
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 7
- 229910052721 tungsten Inorganic materials 0.000 claims description 7
- 239000010937 tungsten Substances 0.000 claims description 7
- 238000005516 engineering process Methods 0.000 claims description 6
- 238000002955 isolation Methods 0.000 claims description 5
- 230000009467 reduction Effects 0.000 claims description 5
- 238000000227 grinding Methods 0.000 claims description 4
- 238000005240 physical vapour deposition Methods 0.000 claims description 4
- 238000001039 wet etching Methods 0.000 claims description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims 2
- 239000000377 silicon dioxide Substances 0.000 claims 1
- 230000000694 effects Effects 0.000 abstract description 9
- 238000004806 packaging method and process Methods 0.000 abstract description 3
- 239000012535 impurity Substances 0.000 description 9
- 241000790917 Dioxys <bee> Species 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000003071 parasitic effect Effects 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 238000010276 construction Methods 0.000 description 2
- 230000007812 deficiency Effects 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 125000004122 cyclic group Chemical group 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000013049 sediment Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The present invention relates to a kind of antistatic pinboards of the integrated circuit based on diode and preparation method thereof, which includes：(a) silicon-based substrate is chosen；(b) diode, TVS holes and isolated groove in the silicon-based substrate；(c) in the TSV holes, so that the TSV holes are connected with the diode, (d) removes the silicon-based substrate base portion material with diode upper surface making metal interconnecting wires, to expose the TSV holes, the isolated groove and the diode in the silicon-based substrate bottom；(e) salient point is made in the TSV holes and the diode lower surface.The antistatic pinboard of integrated circuit provided by the invention based on diode is used as ESD protection device by processing diode on TSV pinboards, enhances the antistatic effect of laminate packaging chip.
Description
Technical field
The present invention relates to semiconductor device design and manufacturing field, more particularly to a kind of integrated circuit based on diode resists
Electrostatic pinboard and preparation method thereof.
Background technology
The characteristic size of integrated circuit is down to 7nm so far, and the number of transistors integrated on a single chip is
Through reaching 10,000,000,000 ranks, with the requirement of the number of transistors of 10,000,000,000 ranks, Resources on Chip and interconnection length problem become existing
The bottleneck of modern integrated circuit fields development, 3D integrated circuits are considered as the developing direction of future integrated circuits, its original circuit
On the basis of, it is stacked on Z axis, in the hope of integrating more functions on minimum area, this method overcomes original integrated
Using emerging technology silicon wafer through hole (Through Silicon Vias, abbreviation TSV), collection is greatly improved in the limitation of degree
It into the performance of circuit, reduces and postpones on line, reduce chip power-consumption.
Inside semicon industry, with the raising of integrated circuit integrated level and the reduction of device feature size, integrate
Potentiality damage caused by static discharge has become more and more apparent in circuit.According to relevant report, the event of integrated circuit fields
The failure for having nearly 35% in barrier is triggered by Electro-static Driven Comb (Electro-Static discharge, abbreviation ESD), therefore
Chip internal is all designed with esd protection structure to improve the reliability of device.However the antistatic effect of different chips is different,
The weak chip of antistatic effect influences whether the antistatic effect of whole system after encapsulation when three-dimensional stacked, therefore how to improve
The antistatic effect of 3D integrated circuits based on TSV techniques becomes semicon industry urgent problem to be solved.
The content of the invention
To solve technological deficiency and deficiency existing in the prior art, present invention proposition is a kind of can to improve the anti-of integrated circuit
Pinboard of electrostatic capacity and preparation method thereof.
A kind of system of the antistatic pinboard of the integrated circuit based on diode is provided in one embodiment of the invention
Preparation Method.The preparation method includes：
(a) silicon-based substrate is chosen；
(b) diode, TVS holes and isolated groove in the silicon-based substrate；
(c) metal interconnecting wires are made in the TSV holes and the diode upper surface so that the TSV holes and two pole
Pipe is connected
(d) the silicon-based substrate base portion material is removed, to expose the TSV holes, institute in the silicon-based substrate bottom
State isolated groove and the diode；
(e) salient point is made in the TSV holes and the diode lower surface.
In one embodiment of the invention, the doping concentration of the silicon-based substrate is 3 × 1014~5 × 1017cm-3。
In one embodiment of the invention, step (b) includes：
(b11) using photoetching process, the first region to be etched is made in the silicon-based substrate upper surface；
(b12) using dry etch process, in silicon-based substrate described in the described first region etch to be etched, device ditch is formed
Slot；
(b13) using chemical vapor deposition method, the first polysilicon layer is deposited in the device trenches, and introduces first
Impurity gas carries out first polysilicon layer doping in situ, forms N+ polysilicon layers；
(b14) using chemical vapor deposition method, the second polysilicon layer is deposited in the device trenches, and introduces second
Impurity gas carries out second polysilicon layer doping in situ, forms N- polysilicon layers；
(b15) using chemical vapor deposition method, the 3rd polysilicon layer is deposited in the device trenches, and introduces the 3rd
Impurity gas carries out the 3rd polysilicon layer doping in situ, forms P+ polysilicon layers；
Wherein, the P+ polysilicon layers, the N- polysilicon layers and the N+ polysilicon layers form diode structure.
In one embodiment of the invention, step (b) further includes：
(b21) using photoetching process, the second region to be etched and the 3rd region to be etched are made in the silicon-based substrate；
(b22) using deep reaction ion etch process, in the described second region to be etched and the 3rd area to be etched
Domain etches the silicon-based substrate, is respectively formed the TSV holes and the isolated groove；
(b23) using plasma-reinforced chemical vapor deposition process, dioxy is deposited in the TSV holes and isolated groove inner wall
Silicon nitride material is as insulating layer；
(b24) using wet-etching technology, oxide layer described in selective etch is so that the TSV holes and the isolated groove
Inner wall it is smooth.
In one embodiment of the invention, step (b) further includes：
(b31) using photoetching process, the first filling region is formed on the isolated groove surface；
(b32) at a temperature of 690~710 DEG C, using chemical vapor deposition method, existed by first filling region
Earth silicon material is filled in the isolated groove；
(b33) using photoetching process, the second filling region is formed in the TSV hole surfaces；
(b34) using physical vapor deposition process, copper material is filled in the TSV holes by second filling region
Material.
In one embodiment of the invention, step (c) includes：
(c1) using plasma-reinforced chemical vapor deposition process, including the TSV holes, the isolated groove and described
The entire material upper surface in P+ regions deposits earth silicon material as the first passivation layer；
(c2) using dry etch process, the first passivation layer described in selective etch, in the TSV holes and the P+ regions
Surface forms the first plug hole；
(c3) using chemical vapor deposition method, deposition tungsten material is as the first plug in first plug hole；
(c4) using electrochemical plating process for copper, grow copper product as metal interconnecting wires in first plug surface so that
The TSV holes are connected with the diode.
In one embodiment of the invention, step (d) includes：
(d1) using mechanical grinding technique, reduction processing is carried out to the silicon-based substrate；
(d2) using CMP process, planarizing process is carried out to the silicon-based substrate bottom, with described in exposing
TSV holes, the isolated groove and the diode.
In one embodiment of the invention, step (e) includes：
(e1) using plasma-reinforced chemical vapor deposition process, including the TSV holes, the isolated groove and described
The entire material lower surface in N+ regions deposits earth silicon material as the second passivation layer；
(e2) using dry etch process, the second passivation layer described in selective etch, in the TSV holes and the N+ regions
Surface forms the second plug hole；
(e3) using chemical vapor deposition method, deposition tungsten material is as the second plug in second plug hole；
(e4) using electrochemical plating process for copper, copper product is grown as salient point stating the second plug surface.
In another embodiment of the present invention, a kind of antistatic pinboard of the integrated circuit based on diode is provided,
The pinboard includes：Substrate, TSV holes, isolation channel, diode, plug, metal interconnecting wires, salient point and passivation layer；Wherein, it is described
Pinboard is prepared by method described in any one of the above embodiments and formed.
Compared with prior art, the present invention at least has the advantages that：
1st, the preparation process of the antistatic pinboard of integrated circuit provided by the invention, processing step is simple, and feasibility is high；
2nd, the antistatic pinboard of integrated circuit provided by the invention is used as ESD by processing diode on TSV pinboards
Protective device enhances the antistatic effect of laminate packaging chip；In addition, the isolation of up/down perforation is used around above-mentioned diode
Groove has smaller leakage current and parasitic capacitance.
Description of the drawings
Below in conjunction with attached drawing, the specific embodiment of the present invention is described in detail.
Fig. 1 is a kind of preparation method of the antistatic pinboard of integrated circuit based on diode provided in an embodiment of the present invention
Flow chart；
Fig. 2 a- Fig. 2 g are a kind of system of the antistatic pinboard of integrated circuit based on diode provided in an embodiment of the present invention
Preparation Method schematic diagram；
Fig. 3 is a kind of structural representation of the antistatic pinboard of integrated circuit based on diode provided in an embodiment of the present invention
Figure.
Specific embodiment
Further detailed description is done to the present invention with reference to specific embodiment, but embodiments of the present invention are not limited to
This.
Embodiment one
Fig. 1 is referred to, Fig. 1 is a kind of antistatic pinboard of integrated circuit based on diode provided in an embodiment of the present invention
Preparation method flow chart, which includes：
(a) silicon-based substrate is chosen；
(b) diode, TVS holes and isolated groove in the silicon-based substrate；
(c) metal interconnecting wires are made in the TSV holes and the diode upper surface so that the TSV holes and two pole
Pipe is connected
(d) the silicon-based substrate base portion material is removed, to expose the TSV holes, institute in the silicon-based substrate bottom
State isolated groove and the diode；
(e) salient point is made in the TSV holes and the diode lower surface.
Wherein, the doping concentration of the silicon-based substrate is 3 × 1014~5 × 1017cm-3。
Step (b) can include：
(b11) using photoetching process, the first region to be etched is made in the silicon-based substrate upper surface；
(b12) using dry etch process, in silicon-based substrate described in the described first region etch to be etched, device ditch is formed
Slot；
(b13) using chemical vapor deposition method, the first polysilicon layer is deposited in the device trenches, and introduces first
Impurity gas carries out first polysilicon layer doping in situ, forms N+ polysilicon layers；
(b14) using chemical vapor deposition method, the second polysilicon layer is deposited in the device trenches, and introduces second
Impurity gas carries out second polysilicon layer doping in situ, forms N- polysilicon layers；
(b15) using chemical vapor deposition method, the 3rd polysilicon layer is deposited in the device trenches, and introduces the 3rd
Impurity gas carries out the 3rd polysilicon layer doping in situ, forms P+ polysilicon layers；
Wherein, the P+ polysilicon layers, the N- polysilicon layers and the N+ polysilicon layers form diode structure.
Step (b) can also include：
(b21) using photoetching process, the second region to be etched and the 3rd region to be etched are made in the silicon-based substrate；
(b22) using deep reaction ion etch process, in the described second region to be etched and the 3rd area to be etched
Domain etches the silicon-based substrate, is respectively formed the TSV holes and the isolated groove；
(b23) using plasma-reinforced chemical vapor deposition process, dioxy is deposited in the TSV holes and isolated groove inner wall
Silicon nitride material is as insulating layer；
(b24) using wet-etching technology, oxide layer described in selective etch is so that the TSV holes and the isolated groove
Inner wall it is smooth.
Step (b) can also include：
(b31) using photoetching process, the first filling region is formed on the isolated groove surface；
(b32) at a temperature of 690~710 DEG C, using chemical vapor deposition method, existed by first filling region
Earth silicon material is filled in the isolated groove；
(b33) using photoetching process, the second filling region is formed in the TSV hole surfaces；
(b34) using physical vapor deposition process, copper material is filled in the TSV holes by second filling region
Material.
Step (c) can include：
(c1) using plasma-reinforced chemical vapor deposition process, including the TSV holes, the isolated groove and described
The entire material upper surface in P+ regions deposits earth silicon material as the first passivation layer；
(c2) using dry etch process, the first passivation layer described in selective etch, in the TSV holes and the P+ regions
Surface forms the first plug hole；
(c3) using chemical vapor deposition method, deposition tungsten material is as the first plug in first plug hole；
(c4) using electrochemical plating process for copper, grow copper product as metal interconnecting wires in first plug surface so that
The TSV holes are connected with the diode.
Step (d) can include：
(d1) using mechanical grinding technique, reduction processing is carried out to the silicon-based substrate；
(d2) using CMP process, planarizing process is carried out to the silicon-based substrate bottom, with described in exposing
TSV holes, the isolated groove and the diode.
Step (e) can include：
(e1) using plasma-reinforced chemical vapor deposition process, including the TSV holes, the isolated groove and described
The entire material lower surface in N+ regions deposits earth silicon material as the second passivation layer；
(e2) using dry etch process, the second passivation layer described in selective etch, in the TSV holes and the N+ regions
Surface forms the second plug hole；
(e3) using chemical vapor deposition method, deposition tungsten material is as the second plug in second plug hole；
(e4) using electrochemical plating process for copper, copper product is grown as salient point stating the second plug surface.
The preparation method of the antistatic pinboard of integrated circuit provided in this embodiment based on diode, by turning in TSV
Diode is processed on fishplate bar as ESD protection device, enhances the antistatic effect of laminate packaging IC chip；In addition,
The preparation method is relatively easy, and feasibility is high.
Embodiment two
The present embodiment is that the realization method of the present invention is illustrated on the basis of embodiment one.
Specifically, refer to Fig. 2 a~Fig. 2 g, Fig. 2 a~Fig. 2 g is based on diode for one kind provided in an embodiment of the present invention
The antistatic pinboard of integrated circuit preparation method schematic diagram, which includes the following steps：
S1, substrate 201 is chosen, as shown in Figure 2 a.
Wherein, the thickness of substrate 201 be 450~550 μm, doping type can be N-type or p-type, doping concentration
For 3 × 1014~5 × 1017cm-3, in addition, 201 crystal orientation of substrate can be (100) either (110) or (111), do not do herein
Any restrictions.
S2, first specified region makes diode 202 in the silicon-based substrate 201；As shown in Figure 2 b.Specifically, S2
It may include steps of：
S21, using photoetching process, make the first region to be etched in 201 upper surface of silicon-based substrate；
S22, using dry etch process, in silicon-based substrate 201 described in the described first region etch to be etched, form device
Groove；
S23, using chemical vapor deposition method, the first polysilicon layer is deposited in the device trenches, and introduces first
Impurity gas carries out first polysilicon layer doping in situ, forms N+ polysilicon layers 2021；
S24, using chemical vapor deposition method, the second polysilicon layer is deposited in the device trenches, and introduces second
Impurity gas carries out second polysilicon layer doping in situ, forms N- polysilicon layers 2022；
S25, using chemical vapor deposition method, the 3rd polysilicon layer is deposited in the device trenches, and introduces the 3rd
Impurity gas carries out the 3rd polysilicon layer doping in situ, forms P+ polysilicon layers 2023；
Wherein, the P+ polysilicon layers 2023, the N- polysilicon layers 2022 and the N+ polysilicon layers 2021 form two
Pole pipe 202.
S3, in the silicon-based substrate 201 second specify region and the 3rd specify region make respectively TVS holes 203 and every
From groove 204, as shown in Figure 2 c.Specifically, S3 may include steps of：
S31, using photoetching process, the first region to be etched and the second region to be etched are made in the silicon-based substrate；
S32, using deep reaction ion etch process, in the described first region to be etched and the described second region to be etched
The silicon-based substrate 201 is etched, is respectively formed the TSV holes 203 and the isolated groove 204；
S33, using plasma-reinforced chemical vapor deposition process, form sediment in the TSV holes 203 and 204 inner wall of isolated groove
Product earth silicon material is as insulating layer；
S34, using wet-etching technology, oxide layer described in selective etch is so that the TSV holes 203 and the isolating trenches
The inner wall of slot 204 is smooth；By the step, it can prevent 203 side wall protrusion of TSV holes from forming electric field concentrated area.
S4, the TVS holes 203 and the isolated groove 204 are filled out respectively using earth silicon material and copper product
It fills；As shown in Figure 2 d.Specifically, S4 may include steps of：
S41, using photoetching process, form the first filling region on the isolated groove surface；
S42, at a temperature of 690~710 DEG C, using chemical vapor deposition method, existed by first filling region
Earth silicon material is filled in the isolated groove；
S43, using photoetching process, form the second filling region in the TSV hole surfaces；
S44, using physical vapor deposition process, copper product is filled in the TSV holes by second filling region.
S5, metal interconnecting wires 205 are made so that the TSV holes in the TSV holes 203 and 202 upper surface of diode
203 are connected with the diode 202, as shown in Figure 2 e.Specifically, S5 may include steps of：
S51, earth silicon material is deposited as the first passivation layer in the TSV holes 203 and 202 upper surface of diode
206, the first passivation layer 206 described in selective etch forms first in the TSV holes 202 and 202 upper surface of diode and inserts
Consent；Deposition tungsten material is as the first plug 207 in first plug hole；
S52, using electrochemical plating process for copper, copper product is grown on 207 surface of the first plug as metal interconnecting wires
So that the TSV holes are connected with the diode 202；Wherein, while surround spiral using metal interconnecting wires and make
Its characteristic with inductance is to be more particularly for the electrostatic protection of RF IC.
S6, removal 201 base portion material of substrate, to expose the TSV holes 203, institute in 201 bottom of substrate
State isolated groove 204 and the diode 202；As shown in figure 2f.Specifically, S6, can include：
S61, using mechanical grinding technique, reduction processing is carried out to 201 lower surface of substrate；
S62, using CMP process, planarizing process is carried out to 201 lower surface of substrate, in the lining
Expose the TSV holes 203, the isolated groove 204 and the diode 202 in 201 bottom of bottom.After the step process, lining
The thickness at bottom 201 is 300~400 μm.
S7, salient point 208 is made in the TSV holes 203 and 202 lower surface of diode, as shown in Figure 2 g.Specifically,
S7 can include：
S71, earth silicon material is deposited as the second passivation layer in the TSV holes 203 and 202 lower surface of diode
209, the second passivation layer 209 described in selective etch forms second in the TSV holes 203 and 202 lower surface of diode and inserts
Consent；Copper product is deposited in second plug hole as the second plug 210；
S72, copper product conduct is deposited on the second plug 210 of the TSV holes 203 and 202 lower surface of diode
Salient point 208.
It should be noted that isolated groove is to separate diode and the connection of other structures in pinboard, therefore isolate
Groove can be made as enclosed construction (such as cyclic structure) and through substrate material, and diode is located inside the enclosed construction.
The preparation method of the antistatic pinboard of integrated circuit provided in this embodiment based on diode, by turning in TSV
Diode is made on fishplate bar as ESD protection device, enhances the antistatic effect of integrated circuit；In addition, above-mentioned diode
Surrounding uses the isolated groove of up/down perforation, has smaller leakage current and parasitic capacitance.
Embodiment three
The present embodiment is based on the preparation method described in above-described embodiment, and emphasis is to the integrated circuit based on diode
The structure of antistatic pinboard is described.
Fig. 3 is refer to, Fig. 3 is a kind of antistatic pinboard of integrated circuit based on diode provided in an embodiment of the present invention
Structure diagram.The antistatic pinboard of integrated circuit based on diode is using the preparation method system described in above-described embodiment
It is standby to be formed.Specifically, which includes：Substrate 301, TSV holes 302, isolation channel 303, diode 304, plug 305, gold
Belong to interconnection line 306, salient point 307 and passivation layer 308；Wherein, copper product is filled in TSV holes 302, dioxy is filled in isolation channel 303
Silicon nitride material.
The antistatic pinboard of integrated circuit provided in this embodiment based on diode, by making two poles in pinboard
Pipe enhances the antistatic effect of integrated circuit as ESD protection device；In addition, by being set up and down around diode
The isolated groove of perforation can reduce the leakage current and parasitic capacitance of pinboard.
The above content is a further detailed description of the present invention in conjunction with specific preferred embodiments, it is impossible to assert
The specific implementation of the present invention is confined to these explanations.For those of ordinary skill in the art to which the present invention belongs, exist
On the premise of not departing from present inventive concept, several simple deduction or replace can also be made, should all be considered as belonging to the present invention's
Protection domain.
Claims (9)
1. a kind of preparation method of the antistatic pinboard of integrated circuit based on diode, which is characterized in that including：
(a) silicon-based substrate is chosen；
(b) diode, TVS holes and isolated groove in the silicon-based substrate；
(c) metal interconnecting wires are made with the diode upper surface in the TSV holes so that the TSV holes and the diode phase
Connection
(d) remove the silicon-based substrate base portion material, with expose in the silicon-based substrate bottom TSV holes, it is described every
From groove and the diode；
(e) salient point is made in the TSV holes and the diode lower surface.
2. preparation method according to claim 1, which is characterized in that the doping concentration of the silicon-based substrate is 3 × 1014~
5×1017cm-3。
3. preparation method according to claim 1, which is characterized in that step (b) includes：
(b11) using photoetching process, the first region to be etched is made in the silicon-based substrate upper surface；
(b12) using dry etch process, in silicon-based substrate described in the described first region etch to be etched, device trenches are formed；
(b13) using chemical vapor deposition method, the first polysilicon layer is deposited in the device trenches, and introduces the first doping
Gas carries out first polysilicon layer doping in situ, forms N+ polysilicon layers；
(b14) using chemical vapor deposition method, the second polysilicon layer is deposited in the device trenches, and introduces the second doping
Gas carries out second polysilicon layer doping in situ, forms N- polysilicon layers；
(b15) using chemical vapor deposition method, the 3rd polysilicon layer is deposited in the device trenches, and introduces the 3rd doping
Gas carries out the 3rd polysilicon layer doping in situ, forms P+ polysilicon layers；
Wherein, the P+ polysilicon layers, the N- polysilicon layers and the N+ polysilicon layers form diode structure.
4. preparation method according to claim 3, which is characterized in that step (b) further includes：
(b21) using photoetching process, the second region to be etched and the 3rd region to be etched are made in the silicon-based substrate；
(b22) using deep reaction ion etch process, carved in the described second region to be etched and the described 3rd region to be etched
The silicon-based substrate is lost, is respectively formed the TSV holes and the isolated groove；
(b23) using plasma-reinforced chemical vapor deposition process, silica is deposited in the TSV holes and isolated groove inner wall
Material is as insulating layer；
(b24) using wet-etching technology, oxide layer described in selective etch so that the TSV holes and the isolated groove it is interior
Wall is smooth.
5. preparation method according to claim 4, which is characterized in that step (b) further includes：
(b31) using photoetching process, the first filling region is formed on the isolated groove surface；
(b32) at a temperature of 690~710 DEG C, using chemical vapor deposition method, by first filling region described
Earth silicon material is filled in isolated groove；
(b33) using photoetching process, the second filling region is formed in the TSV hole surfaces；
(b34) using physical vapor deposition process, copper product is filled in the TSV holes by second filling region.
6. preparation method according to claim 5, which is characterized in that step (c) includes：
(c1) using plasma-reinforced chemical vapor deposition process, including the TSV holes, the isolated groove and the P+ areas
The entire material upper surface in domain deposits earth silicon material as the first passivation layer；
(c2) using dry etch process, the first passivation layer described in selective etch, in the TSV holes and the P+ region surfaces
Form the first plug hole；
(c3) using chemical vapor deposition method, deposition tungsten material is as the first plug in first plug hole；
(c4) using electrochemical plating process for copper, copper product is grown as metal interconnecting wires so that described in first plug surface
TSV holes are connected with the diode.
7. preparation method according to claim 6, which is characterized in that step (f) includes：
(d1) using mechanical grinding technique, reduction processing is carried out to the silicon-based substrate；
(d2) using CMP process, planarizing process is carried out to the silicon-based substrate bottom, to expose the TSV
Hole, the isolated groove and the diode.
8. preparation method according to claim 7, which is characterized in that step (g) includes：
(e1) using plasma-reinforced chemical vapor deposition process, including the TSV holes, the isolated groove and the N+ areas
The entire material lower surface in domain deposits earth silicon material as the second passivation layer；
(e2) using dry etch process, the second passivation layer described in selective etch, in the TSV holes and the N+ region surfaces
Form the second plug hole；
(e3) using chemical vapor deposition method, deposition tungsten material is as the second plug in second plug hole；
(e4) using electrochemical plating process for copper, copper product is grown as salient point stating the second plug surface.
9. the antistatic pinboard of a kind of integrated circuit based on diode, which is characterized in that including silicon-based substrate, TSV holes, isolation
Slot, diode, plug, metal interconnecting wires, salient point and passivation layer；Wherein, the pinboard is by any one of claim 1~9 institute
The method stated prepares to be formed.
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Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1841651A (en) * | 2005-03-29 | 2006-10-04 | 三洋电机株式会社 | Semiconductor device manufacturing method |
| CN101540320A (en) * | 2009-04-21 | 2009-09-23 | 上海宏力半导体制造有限公司 | Static discharge protection diode |
| CN102362349A (en) * | 2009-03-26 | 2012-02-22 | 国际商业机器公司 | Esd network circuit with a through wafer via structure and a method of manufacture |
| CN102598254A (en) * | 2009-10-23 | 2012-07-18 | 新思科技有限公司 | ESD/antenna diodes for through-silicon vias |
| US20130119502A1 (en) * | 2011-11-16 | 2013-05-16 | Analog Devices, Inc. | Electrical overstress protection using through-silicon-via (tsv) |
| US20140203367A1 (en) * | 2013-01-21 | 2014-07-24 | United Microelectronics Corp. | Transistor Structure for Electrostatic Discharge Protection |
| US20150048497A1 (en) * | 2013-08-16 | 2015-02-19 | Qualcomm Incorporated | Interposer with electrostatic discharge protection |
| CN105190888A (en) * | 2013-05-06 | 2015-12-23 | 高通股份有限公司 | Electrostatic discharge diode |
| CN105789163A (en) * | 2016-03-23 | 2016-07-20 | 宜确半导体（苏州）有限公司 | Radio frequency front-end chip integration module and radio frequency front-end chip integration method |
-
2017
- 2017-12-15 CN CN201711352556.7A patent/CN108109961A/en not_active Withdrawn
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1841651A (en) * | 2005-03-29 | 2006-10-04 | 三洋电机株式会社 | Semiconductor device manufacturing method |
| CN102362349A (en) * | 2009-03-26 | 2012-02-22 | 国际商业机器公司 | Esd network circuit with a through wafer via structure and a method of manufacture |
| CN101540320A (en) * | 2009-04-21 | 2009-09-23 | 上海宏力半导体制造有限公司 | Static discharge protection diode |
| CN102598254A (en) * | 2009-10-23 | 2012-07-18 | 新思科技有限公司 | ESD/antenna diodes for through-silicon vias |
| US20130119502A1 (en) * | 2011-11-16 | 2013-05-16 | Analog Devices, Inc. | Electrical overstress protection using through-silicon-via (tsv) |
| US20140203367A1 (en) * | 2013-01-21 | 2014-07-24 | United Microelectronics Corp. | Transistor Structure for Electrostatic Discharge Protection |
| CN105190888A (en) * | 2013-05-06 | 2015-12-23 | 高通股份有限公司 | Electrostatic discharge diode |
| US20150048497A1 (en) * | 2013-08-16 | 2015-02-19 | Qualcomm Incorporated | Interposer with electrostatic discharge protection |
| CN105789163A (en) * | 2016-03-23 | 2016-07-20 | 宜确半导体（苏州）有限公司 | Radio frequency front-end chip integration module and radio frequency front-end chip integration method |
Non-Patent Citations (1)
| Title |
|---|
| 菲利普•加罗: "《3D集成手册 3D集成电路技术与应用》", 31 May 2017 * |
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