CN108092661B - Phase discriminator and phase-locked loop circuit - Google Patents
Phase discriminator and phase-locked loop circuit Download PDFInfo
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- CN108092661B CN108092661B CN201810034873.2A CN201810034873A CN108092661B CN 108092661 B CN108092661 B CN 108092661B CN 201810034873 A CN201810034873 A CN 201810034873A CN 108092661 B CN108092661 B CN 108092661B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
- H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
- H03L7/113—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using frequency discriminator
Abstract
The invention belongs to the technical field of phase locking, and provides a phase discriminator and a phase-locked loop circuit. A phase detector, comprising: the phase difference output circuit is connected with a frequency division clock signal and an input clock signal respectively through a first input end and a second input end of the phase difference output circuit, and is used for comparing the phases of the frequency division clock signal and the input clock signal and outputting a phase difference signal; the delay output circuit is used for carrying out delay output processing on the frequency division clock signal and outputting a delay signal; and the input end of the pre-charging and discharging signal is connected with the input clock signal and is connected with the output end of the delay output circuit, and the input end of the pre-charging and discharging signal is connected with the input clock signal and is used for outputting the pre-charging and discharging signal. The circuit calibration precision is high, the locking time is shortened, and the requirement of a modern communication system on the rapid switching of the phase-locked loop frequency is met.
Description
Technical Field
The invention belongs to the technical field of phase locking, and particularly relates to a phase discriminator and a phase-locked loop circuit.
Background
In order to improve the utilization efficiency of frequency spectrum, the modern wireless communication system mostly adopts the frequency division multiplexing technology, and channels used by a wireless transceiver during wireless communication can be switched in real time according to the real-time occupation condition of the channels, the channel quality and the like. The real-time switching of the channel is realized by changing the output frequency of the phase-locked loop. The phase-locked loop provides a frequency programmable local carrier signal for the up-conversion circuit and the down-conversion circuit in the transceiver, which is a key core module in the wireless transceiver, and the performance of the phase-locked loop can greatly influence the communication quality of the communication system.
As shown in fig. 1, the basic blocks of a conventional Phase-locked Loop include a Voltage Controlled Oscillator (VCO), a Phase Detector (PD), and a Loop Filter (LF). A phase-locked loop is a circuit that synchronizes the output signal generated by a voltage-controlled oscillator with an input reference signal in phase and frequency. If the phase difference between the output signal of the voltage controlled oscillator and the input reference signal changes, a negative feedback control mechanism exists in the phase-locked loop to adjust the output of the oscillator, so that the phase difference between the two is reduced, and finally the phase-locked state is achieved. The phase discriminator is an important component of the phase-locked loop and can judge the phase difference between an input reference signal and an output signal when the frequency or the phase of the input signal jumps, so that the output signal is enabled to quickly follow the change of the input signal. After the phase discriminator performs phase discrimination on a clock signal, the phase-locked loop system only adjusts the output of the oscillator according to the phase difference, the phase-locked loop system can reach a locked state after a plurality of times of frequency calibration from starting to complete locking, and the calibration precision is low and the working efficiency is very low.
Therefore, the traditional technical scheme has the problems of low calibration precision and low working efficiency.
Disclosure of Invention
The invention aims to provide a phase discriminator and a phase-locked loop circuit, and aims to solve the problems of low calibration precision and low working efficiency in the traditional technical scheme.
A phase detector, comprising:
the phase difference output circuit is connected with the frequency division clock signal and the input clock signal at the input end respectively, and is used for comparing the phases of the frequency division clock signal and the input clock signal and outputting a phase difference signal;
the delay output circuit is used for carrying out delay output processing on the frequency division clock signal and outputting a delay signal;
and the pre-charging and discharging signal output circuit is respectively connected with the input clock signal and the output end of the delay output circuit, and is used for outputting a pre-charging and discharging signal.
Further, there is provided a phase-locked loop circuit including:
the phase discriminator described above;
the charge pump outputs current according to the phase difference signal and the delay signal, and carries out charging and discharging and pre-charging and discharging on the loop filter;
the loop filter is connected with the charge pump and the phase discriminator and outputs a phase control signal;
the voltage control oscillator is connected with the loop filter and controls and outputs a target phase signal according to the phase control signal;
and the frequency divider is connected between the voltage control oscillator and the phase discriminator and feeds the target phase signal back to the phase discriminator.
According to the phase discriminator and the phase-locked loop circuit, the frequency division clock signal is compared with the input clock signal through the phase difference output circuit, the frequency division clock signal and the phase difference signal of the input clock signal are output, the frequency division clock signal is subjected to delay output processing through the delay output circuit and is output as the delay signal, the pre-charge and discharge signal is output through the pre-charge and discharge signal output circuit, and the charge pump controls charge and discharge of the loop filter according to the phase difference signal, the delay signal and the pre-charge and discharge signal, so that the voltage control oscillator is controlled to adjust the phase of the input clock signal and output a target phase signal, rapid synchronization of the frequency division clock signal and the input clock signal is realized, the circuit calibration precision is high, the locking time is shortened, and the requirement of a modern communication system on rapid switching of the frequency of.
Drawings
FIG. 1 is a diagram illustrating a conventional PLL;
FIG. 2 is a schematic diagram of a phase-locked loop circuit according to a preferred embodiment of the present invention;
fig. 3 is an exemplary circuit schematic of a phase detector in the phase locked loop circuit shown in fig. 2;
FIG. 4 is an exemplary circuit schematic of a charge pump in the phase locked loop circuit of FIG. 2;
FIG. 5 is an exemplary circuit schematic of a loop filter in the phase locked loop circuit shown in FIG. 2;
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Fig. 2 is a schematic structural diagram of a phase-locked loop circuit according to a preferred embodiment of the present invention, and for convenience of description, only the relevant portions of the phase-locked loop circuit are shown, which is detailed as follows:
an embodiment of the present invention provides a phase-locked loop circuit, where the phase-locked loop includes: the phase detector 10, the charge pump 20, the loop filter 30, the voltage controlled oscillator 40 and the frequency divider 50 process the received input clock signal FREF to synchronize the signal with the phase of the frequency divided clock signal FDIV output by the phase locked loop.
The phase detector 10 is configured to input a phase difference signal and a phase adjustment control signal of the clock signal FREF and the frequency-divided clock signal FDIV, so as to control charging and discharging of the charge pump 20 to the loop filter 30.
As shown in fig. 3, the phase detector 10 includes a phase difference output circuit 101, a delay output circuit 102, and a pre-charge-discharge signal output circuit 103.
The first input end and the second input end of the phase difference output circuit 101 are respectively connected with the input frequency-division clock signal FDIV and the input clock signal FREF, and compare and output phase difference signals of the frequency-division clock signal FDIV and the input clock signal FREF, the phase difference signals include a first phase difference signal UP and a second phase difference signal UPB which are output in a differential mode, the phase difference output circuit 101 correspondingly has a first output end and a second output end, and the first output end of the phase difference output circuit 101 and the second output end of the phase difference output circuit 101 are respectively used for outputting the first phase difference signal UP and the second phase difference signal UPB. The phase difference output circuit 101 includes a first D flip-flop DFF1, a second D flip-flop DFF2, a first AND gate AND1, AND a first differential converter S2D 1; the first D flip-flop DFF1 is connected to the input clock signal FREF for receiving the input clock signal FREF, and the first differential converter S2D1 is connected to the output terminal of the first D flip-flop DFF1 for converting the signal output by the first D flip-flop DFF1 into a differential signal and outputting the differential signal; the second D flip-flop DFF2 is connected to the divided clock signal FDIV for receiving the divided clock signal FDIV, a first input terminal of the first AND circuit AND1 is connected to an output terminal of the first D flip-flop DFF1, a second input terminal of the first AND circuit AND1 is connected to an output terminal of the second D flip-flop DFF2, AND an output terminal of the first AND circuit AND1 is connected to a reset terminal of the first flip-flop AND a reset terminal of the second flip-flop, respectively, for resetting the first D flip-flop DFF1 AND the second D flip-flop DFF 2. When the outputs of the first and second D flip-flops DFF1 and DFF2 are both "1", the first and second D flip-flops DFF1 and DFF2 are reset at the same time, the output terminal of the first D flip-flop DFF1 outputs a phase difference signal of the frequency-divided clock signal FDIV and the input clock signal FREF, and the differential converter converts the phase difference signal into differential first and second phase difference signals UP and UPB.
A delay output circuit 102, configured to perform a delay output process on the frequency-divided clock signal FDIV and output a delay signal, where the delay signal includes a first delay signal HOLDP and a second delay signal holdlm which are differentially output, the delay output circuit 102 has a first output terminal and a second output terminal, and the first output terminal of the delay output circuit 102 and the second output terminal of the delay output circuit 102 are respectively configured to output the first delay signal HOLDP and the second delay signal holdlm. The delay output circuit 102 includes a first delay DU1, a second delay DU2, a third D flip-flop DFF3, and a second differential converter S2D 2; an input end of the first delay DU1 is connected to the frequency-divided clock signal FDIV to receive the frequency-divided clock signal FDIV, an output end of the first delay DU1 is connected to an input end of the second delay DU2 and the third D flip-flop DFF3, an output end of the second delay DU2 is connected to a reset end of the third D flip-flop DFF3 for resetting the third D flip-flop DFF3, and the second differential converter S2D2 is connected to an output end of the third D flip-flop DFF3 for converting the output signal of the third D flip-flop DFF3 into a differential signal and outputting the differential signal. After the frequency-divided clock signal FDIV is delayed by the first delayer DU1, the frequency-divided clock signal FDIV passes through the third D flip-flop DFF3, and resets the third D flip-flop DFF3 with the frequency-divided clock signal FDIV twice delayed by the first delayer DU1 and the second delayer DU2 at the same time, so as to obtain a narrow delay signal, and the second differential converter S2D2 converts the delay signal from a single end to the differential first delay signal HOLDP and the differential second delay signal dlhom.
And a pre-charge and discharge signal output circuit 103 connected to the second output terminal of the delay output circuit 102, wherein the pre-charge and discharge signal output circuit 103 is configured to output a pre-charge and discharge control signal. The precharge AND discharge signal output circuit 103 includes a first inverter INV1, a second inverter INV2, a fourth D flip-flop DFF4, a fifth D flip-flop, a second AND gate AND2, a third inverter INV3, AND a fourth inverter INV 4; an input clock signal FREF is input to an input end of the first inverter INV1, the second inverter INV2 is connected in series between an output end of the first inverter INV1 AND the fourth D flip-flop DFF4, an output end of the fourth D flip-flop DFF4 is connected to a second input end of the second AND circuit AND2, the fifth D flip-flop DFF5 is connected to a second output end of the delay output circuit 102 AND is connected to the second delay signal HODLM, an output end of the fifth D flip-flop DFF5 is output through the third inverter INV3 AND the fourth inverter INV4 which are connected in series, AND an output end of the second AND circuit AND2 is connected to a reset end of the fifth D flip-flop DFF 5. The precharge and discharge control signal PRECHG is a precharge signal for the loop filter 30, is "1" when the rising edge of the second delayed signal HOLDM signal arrives, and is reset to "0" when the rising edge of the input clock signal FREF arrives.
As shown in fig. 4, the charge pump 20 outputs a current according to the phase difference signal and the delay signal, and charges and pre-charges the loop filter 30, and the charge pump 20 includes: a first current source I1, a second current source I2, a first switch K1, a second switch K2, a third switch K3 and a MOS tube Q1;
the cathode of the first current source I1 is connected with the cathode of the second current source I2, the first switch K1 is connected between the sources of the positive MOS transistors Q1 of the first current source I1, the gate of the MOS transistor Q1 is connected with the drain of the MOS transistor Q1, the second switch K2 and the third switch K3 are sequentially connected in series between the anode of the second current source I2 and the drain of the MOS transistor Q1, and the common connection end of the second switch K2 and the third switch K3 is connected with the loop filter 30 as the output end of the charge pump 20; the phase difference signal controls the first switch K1 and the second switch K2 to be closed and opened, and the pre-charge signal PRECHG controls the third switch K3 to be closed and opened. Specifically, the first phase difference signal UP and the second phase difference signal UPB are respectively used for controlling the first switch K1 and the second switch K2, when the control signal is "1", the first switch, the second switch and the third switch K3 are closed, and when the control signal is "0", the first switch K1, the second switch K2 and the third switch K3 are opened, so as to control the power output of the charge pump 20.
As shown in fig. 5, the loop filter 30 is connected to the charge pump 20 and the phase detector 10, and outputs a phase control signal; the loop filter 30 includes a fourth switch K4, a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a first resistor R1, and a second resistor R2; a fourth switch K4, a first resistor R1 and a second resistor R1 are connected in series between the output end of the charge pump 20 and the voltage-controlled oscillator 40, a first capacitor C1 is connected between the output end of the charge pump 20 and the ground, a second capacitor C2 is connected between the common connection end of the fourth switch K4 and the first resistor R1 and the ground, a third capacitor C3 is connected between the common connection end of the first resistor R1 and the second resistor R2 and the ground, and a fourth capacitor C4 is connected between the voltage-controlled oscillator 40 and the ground; wherein the delay signal controls the closing and opening of the fourth switch K4. Specifically, the first delay signal HOLDP and the second delay signal holdlm differentially control the fourth switch to charge and discharge the first capacitor C1 of the loop filter at the same time, and the phase control signal VCTRL is output through an RC filter circuit composed of the second capacitor C2, the third capacitor C3, the fourth capacitor C4, the first resistor R1 and the second resistor R2, so as to control the output of the voltage controlled oscillator 40.
The voltage controlled oscillator 40 is connected to the loop filter 30, and controls and outputs a target phase signal according to the phase control signal VCTRL; the frequency divider 50 is connected between the voltage controlled oscillator 40 and the phase detector 10 and feeds back a target phase signal to the phase detector 10.
According to the phase-locked loop circuit, the phase difference output circuit is used for comparing the frequency division clock signal with the input clock signal and outputting the phase difference signal of the frequency division clock signal and the input clock signal, the delay output circuit is used for carrying out delay output processing on the frequency division clock signal and outputting the delay signal, the pre-charging and discharging signal is output through the pre-charging and discharging signal output circuit, and the charge pump is controlled to charge and discharge the loop filter according to the phase difference signal, the delay signal and the pre-charging and discharging signal, so that the voltage control oscillator is controlled to adjust the phase of the input clock signal and output a target phase signal, the frequency division clock signal and the input clock signal are quickly synchronized, the circuit calibration precision is high, the locking time is shortened, and the requirement of a modern communication system for quickly switching.
The present invention is not limited to the above preferred embodiments, and any modifications, equivalent substitutions and improvements made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (9)
1. A phase detector, comprising:
the phase difference output circuit is connected with a frequency division clock signal and an input clock signal respectively through a first input end and a second input end of the phase difference output circuit, and is used for comparing the phases of the frequency division clock signal and the input clock signal and outputting a phase difference signal;
the delay output circuit is used for carrying out delay output processing on the frequency division clock signal and outputting a delay signal;
the input end of the pre-charging signal is connected with the input clock signal and is connected with the output end of the delay output circuit, and the input end of the pre-charging signal is connected with the input clock signal and is used for outputting the pre-charging signal;
the pre-charging and discharging signal output circuit comprises a first inverter, a second inverter, a fourth D trigger, a fifth D trigger, a second AND gate circuit, a third inverter and a fourth inverter;
the input end of the first inverter is connected with the input clock signal, the second inverter is connected in series between the output end of the first inverter and the fourth D flip-flop, the output end of the fourth D flip-flop is connected to the second input end of the second and circuit, the fifth D flip-flop is connected with the output end of the delay output circuit, the output end of the fifth D flip-flop is output through the third inverter and the fourth inverter which are connected in series, and the output end of the second and circuit is connected with the reset end of the fifth D flip-flop;
the pre-charge and discharge control signal is used for pre-charging the loop filter, and is "1" when the rising edge of the second delay signal comes, and is reset to "0" when the rising edge of the input clock signal comes.
2. A phase detector as claimed in claim 1, wherein said phase difference output circuit has a first output terminal and a second output terminal, said phase difference signal comprises a first phase difference signal and a second phase difference signal output differentially, said first output terminal of said phase difference output circuit and said second output terminal of said phase difference output circuit are for outputting said first phase difference signal and said second phase difference signal, respectively.
3. A phase detector as claimed in claim 1, wherein said delayed output circuit has a first output terminal and a second output terminal, said delayed signals comprising a differentially output first delayed signal and a second delayed signal, said first output terminal of said delayed output circuit and said second output terminal of said delayed output circuit for outputting said first delayed signal and said second delayed signal, respectively.
4. A phase detector as claimed in claim 3, wherein a trigger terminal of said pre-charge-discharge signal output circuit is connected to a second output terminal of said delay output circuit.
5. A phase detector as claimed in claim 1, wherein said phase difference output circuit comprises a first D flip-flop, a second D flip-flop, a first and gate circuit, and a first differential converter;
the first D flip-flop is connected to the input clock signal and configured to receive the input clock signal, and the first differential converter is connected to an output end of the first D flip-flop and configured to convert a signal output by the first D flip-flop into a differential signal and output the differential signal;
the second D trigger is connected with the frequency division clock signal and used for receiving the frequency division clock signal, the first input end of the first AND gate circuit is connected with the output end of the first D trigger, the second input end of the first AND gate circuit is connected with the output end of the second D trigger, and the output end of the first AND gate circuit is respectively connected with the reset end of the first D trigger and the reset end of the second D trigger and used for resetting the first D trigger and the second D trigger.
6. A phase detector as claimed in claim 1, wherein said delay output circuit comprises a first delay, a second delay, a third D flip-flop and a second differential converter;
the input end of the first delayer is connected with the frequency division clock signal to receive the frequency division clock signal, the output end of the first delayer is respectively connected with the input end of the second delayer and the third D trigger, the output end of the second delayer is connected with the reset end of the third D trigger to reset the third D trigger, and the second differential converter is connected with the output end of the third D trigger to convert the output signal of the third D trigger into a differential signal and output the differential signal.
7. A phase-locked loop circuit, comprising:
a phase detector according to any one of claims 1 to 4;
the charge pump outputs current according to the phase difference signal and the delay signal, and carries out charging and discharging and pre-charging and discharging on the loop filter;
the loop filter is connected with the charge pump and the phase discriminator and outputs a phase control signal;
the voltage control oscillator is connected with the loop filter and controls and outputs a target phase signal according to the phase control signal;
and the frequency divider is connected between the voltage control oscillator and the phase discriminator and feeds the target phase signal back to the phase discriminator.
8. The phase-locked loop circuit of claim 7, wherein the charge pump comprises: the circuit comprises a first current source, a second current source, a first switch, a second switch, a third switch and an MOS (metal oxide semiconductor) tube;
the negative electrode of the first current source is connected with the negative electrode of the second current source, the first switch is connected between the positive electrode of the first current source and the source electrode of the MOS tube, the grid electrode of the MOS tube is connected with the drain electrode of the MOS tube, the second switch and the third switch are sequentially connected in series and between the positive electrode of the second current source and the drain electrode of the MOS tube, and the common connecting end of the second switch and the third switch is used as the output end of the charge pump and is connected with the loop filter;
wherein the phase difference signal controls the first switch and the second switch to be closed and opened, and the pre-charge and discharge signal controls the third switch to be closed and opened.
9. The phase-locked loop circuit of claim 7, wherein the loop filter comprises a fourth switch, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a first resistor, and a second resistor;
the fourth switch, the first resistor and the second resistor are connected in series between the output end of the charge pump and the voltage-controlled oscillator, the first capacitor is connected between the output end of the charge pump and the ground, the second capacitor is connected between the common connection end of the fourth switch and the first resistor and the ground, the third capacitor is connected between the common connection end of the first resistor and the second resistor and the ground, and the fourth capacitor is connected between the voltage-controlled oscillator and the ground;
wherein the delay signal is used for closing and opening of the fourth switch.
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| CN112350204A (en) * | 2019-11-20 | 2021-02-09 | 邹虚 | Movable transformer substation |
| CN111835344B (en) * | 2020-07-29 | 2022-11-29 | 展讯通信（上海）有限公司 | Phase-locked loop circuit and terminal |
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| CN105634481B (en) * | 2015-12-25 | 2018-08-07 | 中国科学技术大学先进技术研究院 | A kind of low spurious linearizer structure applied to fractional-n phase-locked loop |
| EP3190704B1 (en) * | 2016-01-06 | 2018-08-01 | Nxp B.V. | Digital phase locked loops |
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2018
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