JP6121135B2 - Synchronization circuit and clock data recovery circuit including the same - Google Patents

Description

  The present invention relates to a synchronization circuit that generates a recovered clock signal synchronized with a reference clock signal and a clock data recovery circuit (hereinafter referred to as a CDR circuit) including the synchronization circuit.

  Currently, as a high-speed serial data communication method, an embedded clock method in which a clock signal is superimposed on a data signal and transmitted is employed.

  A receiving device of a communication system adopting an embedded clock system includes a CDR circuit that acquires a recovered clock signal that is phase-synchronized with a data transition point from the received data signal by using the periodicity of data transition in the received data signal. It is mounted (see, for example, FIG. 5 of Patent Document 1). This CDR circuit includes a PLL (phase locked loop) circuit including a phase / frequency detector, a charge pump, a loop filter, a voltage controlled oscillator, and a frequency divider (see, for example, FIG. 5 of Patent Document 1).

 However, due to various factors, there is a case in which a false lock in which the frequency of the recovered clock signal is locked to a frequency higher than a desired frequency may occur. In this case, accurate data reception cannot be guaranteed. There has occurred.

  Therefore, the CDR circuit includes a pseudo lock detection circuit that detects whether or not a pseudo lock is generated in the PLL circuit as the synchronization circuit (for example, reference numeral 40 in FIG. 5 of Patent Document 1). This pseudo lock detection circuit determines whether or not a pseudo lock has occurred based on a pattern of a data series obtained by sampling a training pattern for detecting a pseudo lock included in a received data signal at the timing of the above-described reproduction clock signal. To detect. When the pseudo lock is detected by the pseudo lock detection circuit, the voltage supplied to the voltage controlled oscillator in the PLL circuit is forcibly lowered to lock the frequency higher than the desired frequency. This reduces the frequency of the recovered clock signal.

  By the way, when the phase / frequency detector in the PLL circuit malfunctions due to external noise or the like, for example, only a signal corresponding to the phase advance (or delay) is continuously supplied to the charge pump, the charge pump The output is fixed at zero level. Therefore, when a new data signal is received thereafter, the PLL circuit starts the initial synchronization from the state where the output of the charge pump is zero level. At this time, the synchronization having the feedback loop such as the PLL circuit is performed. There is a possibility that the control circuit may be pseudo-locked at a frequency different from the desired frequency.

JP 2011-30058 A

  It is an object of the present invention to provide a synchronization circuit capable of generating a recovered clock signal synchronized with a reference clock signal without causing a pseudo lock, and a clock data recovery circuit including the synchronization circuit.

A synchronization circuit according to the present invention is a synchronization circuit that generates a recovered clock signal synchronized with a reference clock signal, and has a voltage value corresponding to a phase difference between the reference clock signal and the recovered clock signal A charge pump that generates a phase control voltage and sends it to the first line; a phase control circuit that controls the phase of the recovered clock signal in accordance with the phase control voltage; and the phase control voltage is lower than a lower limit reference voltage. wherein for the first line starts precharge, the includes a pseudo lock avoidance circuit phase control voltage continues to precharge operation for said first line by more than the upper limit reference voltage, the said false-lock avoidance circuit when the Performs a magnitude comparison between the phase control voltage and the lower limit reference voltage, and lowers the lower limit when the phase control voltage is smaller than the lower limit reference voltage. A first comparator that generates a second signal, and a second comparator that compares the phase control voltage with the upper reference voltage and generates an upper limit over signal when the phase control voltage is greater than the upper reference voltage. And applying a power supply voltage to the first line in response to the lower limit under signal while applying the power supply voltage to the first line in response to the upper limit over signal. And a precharge transistor for stopping the precharge by stopping .

The clock data recovery circuit according to the present invention includes a clock generation means for generating a reference clock signal synchronized with a data transition point appearing every predetermined period in an input data signal, and a recovered clock signal synchronized with the reference clock signal. A clock data recovery circuit including a synchronizing means for generating a phase control voltage having a voltage value corresponding to a phase difference between the reference clock signal and the recovered clock signal. above when it falls below a charge pump for delivering it to the first line on a phase control circuit for controlling the phase of the reproduced clock signal in response to the phase control voltage, the phase control voltage is a lower limit reference voltage a Precharge for one line is started and the precharge for the first line is continued until the phase control voltage exceeds the upper reference voltage. Includes a pseudo lock avoidance circuit to continue di- operation, the said false-lock avoidance circuit performs comparison between the phase control voltage and the lower limit reference voltage, the phase control voltage is smaller than the lower limit reference voltage A first comparator that generates a lower limit under signal at a certain time is compared with the phase control voltage and the upper reference voltage, and an upper limit over signal is generated when the phase control voltage is greater than the upper reference voltage The second comparator and the first line are precharged by applying a power supply voltage to the first line in response to the lower limit under signal, while the power to the first line in response to the upper limit over signal And a precharge transistor that stops precharging by stopping application of voltage .

  In the present invention, the following pseudo lock avoidance processing is performed when generating a clock signal synchronized with a reference clock signal by a synchronization circuit having a charge pump. That is, when the phase control voltage sent on the first line by the charge pump falls below the lower limit reference voltage, precharge for the first line is started, and until the phase control voltage exceeds the upper limit reference voltage, The precharge operation is continued.

  As a result, even if the charge pump operation is substantially stopped due to the influence of external noise, the first line is forcibly precharged at this time, so that the voltage of the phase control voltage is set to a high voltage value. It can be maintained.

  Therefore, according to the present invention, it is possible to avoid the false lock that occurs when the synchronization circuit starts the initial synchronization from the state where the phase control voltage is at a low voltage near the ground voltage.

1 is a block diagram showing a configuration of a clock data recovery circuit 100 including a DLL circuit 3 as a synchronization circuit according to the present invention. 3 is a time chart showing an internal operation of the clock data recovery circuit 100. 3 is a circuit diagram illustrating an example of an internal configuration of a clock generation unit 2. FIG. 2 is a circuit diagram showing an internal configuration of variable delay NAND gates 21, 22 and 62. FIG. 3 is a circuit diagram showing an internal configuration of a multiphase clock generator 30. FIG. Is a circuit diagram showing the internal configuration of the variable delay circuit ₃₀₁ 1 to 301 _n each. 3 is a circuit diagram illustrating an example of an internal configuration of an enable signal generation unit 6. FIG. It is an example of the time chart which shows the transmission timing of the enable signal EN, and the timing of the enable clock signal CK _(X) used in order to produce | generate the enable signal EN. 3 is a circuit diagram showing an example of an internal configuration of a pseudo lock avoidance circuit 34. FIG. 3 is a time chart showing an internal operation of a pseudo lock avoidance circuit 34. 6 is a time chart showing an example of a pseudo lock avoidance operation by a pseudo lock avoidance circuit. FIG. 6 is a circuit diagram showing another example of the internal configuration of the pseudo lock avoidance circuit 34. 13 is a time chart showing an example of a pseudo lock avoidance operation by the pseudo lock avoidance circuit 34 shown in FIG. 12.

  FIG. 1 is a block diagram showing a clock data recovery circuit 100 including a DLL circuit 3 as a synchronization circuit according to the present invention.

  The clock data recovery circuit 100 shown in FIG. 1 is formed in a semiconductor IC mounted on a receiving device (not shown). Such a receiving device receives and demodulates a transmission signal transmitted from a transmitting device (not shown), and generates a binarized version thereof as a received data signal DIN. At this time, as shown in FIG. 2, the received data signal DIN includes a dummy bit DB for one bit for each reference transition period P in a data series DS each composed of a plurality of data bits each having a unit data period UI. Has been inserted. At this time, as shown in FIG. 2, when the first data bit of the data series DS is at logic level 0, a dummy bit DB at logic level 1 is inserted immediately before that. On the other hand, when the first data bit is at logic level 1, a dummy bit DB at logic level 0 is inserted immediately before that. As a result, in the received data signal DIN, the reference transition portion TC that transitions from the logic level 1 to the logic level 0 or from the logic level 0 to the logic level 1 appears at the rear edge portion of the dummy bit DB for each reference transition period P. Will do.

  The transition detection unit 1 detects a rising edge portion in which the value of the data bit transitions from the logic level 0 to the logic level 1 from the received data signal DIN, and a falling edge transitions from the logic level 1 to the logic level 0. 2 is generated, a short pulse transition detection signal CLKX 2 as shown in FIG. 2 is generated and supplied to the clock generation unit 2. That is, the transition detection unit 1 supplies the clock generation unit 2 with a transition detection signal CLKX2 that represents a data transition point of the reception data signal DIN with a short pulse.

  FIG. 3 is a circuit diagram showing the internal configuration of the clock generator 2.

  As shown in FIG. 3, the clock generation unit 2 includes an RS flip-flop (hereinafter referred to as RSFF) including variable delay NAND gates 21 and 22, a NAND gate 23, and inverters 24 and 25.

The variable delay NAND gate 21 obtains a negative logical product of the transition detection signal CLKX2 supplied from the transition detection unit 1 and the enable signal EN as shown in FIG. A set signal ST1 indicating the logical product result is supplied to the input terminal I1 of the NAND gate 23. In short, the variable delay NAND gate 21 captures the transition detection signal CLKX2 only while the enable signal EN is at the logic level 1, and the NAND gate 23 sets a signal obtained by inverting the logic level of the captured transition detection signal CLKX2 as the set signal ST1. To supply. The variable delay NAND gate 21 delays the set signal ST1 to the NAND gate 23 by delaying by 0.5 · UI (UI: unit data cycle) from the time when the transition detection signal CLKX2 transits from the logic level 0 to the logic level 1. Supply. At this time, the delay time of the variable delay NAND gate 21 is adjusted to maintain at all times 0.5 · UI in accordance with the delay adjustment signal to be described later _(CT P, CT _N). As described above, the variable delay NAND gate 21 operates as variable delay fetching means for fetching the transition detection signal CLKX2 after delaying it by the unit data period UI according to the enable signal EN. The inverter 24 supplies a signal obtained by inverting the logic level of the reproduction clock signal CK ₂ (described later) to the input terminal I2 of the variable delay NAND gate 22 as the reset signal RT1. The output terminal of the NAND gate 23 is connected to the input terminal I 1 of the variable delay NAND gate 22, and the input terminal I 2 of the NAND gate 23 and the input terminal of the inverter 25 are connected to the output terminal of the variable delay NAND gate 22. The variable delay NAND gate 22 delays the reproduction clock signal CK ₂ from the logic level 0 to the logic level 1 state by 0.5 · UI and supplies the output result to each of the NAND gate 23 and the inverter 25. At this time, the delay time of the variable delay NAND gate 22 is adjusted to maintain at all times 0.5 · UI in accordance with the delay adjustment signal _(CT P, CT _N). The inverter 25 outputs a signal obtained by inverting the logic level of the signal sent from the variable delay NAND gate 22 as the reference clock signal CLK.

  FIG. 4 is a circuit diagram showing an example of the internal configuration of the variable delay NAND gates 21 and 23.

  As shown in FIG. 4, each of the variable delay NAND gates 21 and 23 includes n-channel MOS (metal-oxide semiconductor) transistors 201 and 202, p-channel MOS transistors 203 and 204, and variable resistors 205 to 207. And having.

The gate terminal of the transistor 201 is connected to the input terminal I 1, and its source terminal is connected to the drain terminal of the transistor 202. The drain terminal of the transistor 201 is connected to the drain terminals of the transistors 203 and 204 via the output line L0. The gate terminal of the transistor 202 is connected to the input terminal I 2, and the source terminal thereof is connected to one end of the variable resistor 205. A ground voltage GND is applied to the other end of the variable resistor 205. The variable resistor 205 changes its resistance value according to a delay adjustment signal CT _N (described later). The gate terminal of the transistor 203 is connected to the input terminal I 1, and its source terminal is connected to one end of the variable resistor 206. A power supply voltage VDD is applied to the other end of the variable resistor 206. The gate terminal of the transistor 204 is connected to the input terminal I 2, and the source terminal is connected to one end of the variable resistor 207. A power supply voltage VDD is applied to the other end of the variable resistor 207. These variable resistors 206 and 207, in accordance with the delay adjustment signal CT _P (described below), to change its resistance value. Therefore, when a voltage corresponding to logic level 0 is applied to the input terminal I1 or I2, the transistor 203 or 204 is turned on, and current is output through the variable resistor 206 and the transistor 203 or the variable resistor 207 and the transistor 204. Flow into line L0. As a result, the output line L0 is charged, and the voltage on the output line L0 increases with time. At this time, when the voltage applied to the input terminal I1 or I2 transitions from the logic level 1 to the logic level 0 by 0.5 · UI, the voltage on the output line L0 becomes equal to or higher than the threshold voltage. A signal transitioning from level 0 to logic level 1 is sent through output terminal Y.

Here, the resistance value of the variable resistor 206 and 207 is increased in accordance with the delay adjustment signal CT _P, reduces the amount of current charging the output line L0, the voltage rise rate on the output line L0 with time is reduced . Therefore, the time until the voltage exceeds the threshold voltage becomes long, and therefore, the delay time of the signal transmitted through the output terminal Y increases. On the other hand, if the resistance value of the variable resistor 206 and 207 is reduced in accordance with the delay adjustment signal CT _P, increases the amount of current charging the output line L0, the voltage rise rate on the output line L0 with time increases. Therefore, the time until the voltage exceeds the threshold voltage is shortened, and therefore the delay time of the signal transmitted through the output terminal Y is reduced. When a voltage corresponding to logic level 1 is applied to both input terminals I1 and I2, the transistors 201 and 202 are turned on, and current is drawn from the output line L0 to the transistors 201 and 202 and the variable resistor 205. As a result, the output line L0 is discharged, and the voltage on the output line L0 decreases with time. At this time, the voltage on the output line L0 becomes less than the threshold voltage when 0.5 · UI elapses after the voltage corresponding to the logic level 1 is started to be applied to both the input terminals I1 and I2. A signal transitioning to level 0 is sent through the output terminal Y. Here, increasing the resistance value of the variable resistor 205 in accordance with the delay adjustment signal CT _N, since the amount of current to discharge the output line L0 is reduced, the voltage decrease rate on the output line L0 with time decreases. Therefore, the time until the voltage falls below the threshold voltage is lengthened, and therefore, adjustment is performed to increase the delay time of the signal transmitted via the output terminal Y. On the other hand, if the resistance value of the delay adjustment signal CT _N depending on the variable resistor 205 is decreased, since the amount of current discharging the output line L0 is increased, the voltage drop rate on the output line L0 with time is increased. Therefore, the time until the voltage falls below the threshold voltage is shortened, and therefore, adjustment is performed to reduce the delay time of the signal transmitted through the output terminal Y.

With the configuration described above, the clock generator 2 takes in the transition detection signal CLKX2 only when the enable signal EN is in the logic level 1 state. Then, the clock generation unit 2, as shown in FIG. 2, a transition from a logic level 0 to the state of the logic level 1 at the rising edge timing of the transition detection signal CLKX2, then the logic level at the rising edge timing of the recovered clock signal CK ₂ A reference clock signal CLK having a pulse waveform that transitions to a 0 state is generated. The clock generator 2 is provided with the variable delay NAND gates 21 and 22 as described above, as shown in FIG. 2, from the rising edge timing of the transition detection signal CLKX2 or reproduction clock signal CK _2, only 1.0 · UI The reference clock signal CLK is output at the delayed timing. At this time, the delay time of the clock generator 2, the variable delay NAND gates 21 and 22 are adjusted to maintain always 1.0 · UI in accordance with the delay adjustment signal _(CT P, CT _N).

  The clock generator 2 supplies the reference clock signal CLK to a delay lock loop (hereinafter referred to as DLL) circuit 3.

  Here, as shown in FIG. 2, the enable signal EN is a signal including a train of pulses that transitions from a logic level 0 to a logic level 1 in a reference transition period P.

  Therefore, the clock generation means including the transition detection unit 1 and the clock generation unit 2 generates the reference clock signal CLK synchronized with the data transition point appearing every predetermined reference transition period P in the input data signal DIN. Is supplied to the DLL circuit 3.

  The DLL circuit 3 as a synchronization circuit includes a multiphase clock generation unit 30, a phase comparator 31, a charge pump 32, a phase control circuit 33, and a pseudo lock avoidance circuit.

The phase comparator 31 compares the phases of the reference clock signal CLK and the recovered clock signal CK _n (described later). In this case, while the phase comparator 31, when the reference clock signal CLK is a reproduction clock signal CK _n is delayed phase to provide charge-up signal UP to the charge pump 32, reproducing the reference clock signal CLK When the clock signal CK _n is in the lead phase, the charge down signal DN is supplied to the charge pump 32.

  The charge pump 32 generates a phase control voltage CTR whose voltage gradually increases while the charge-up signal UP is supplied, and gradually decreases while the charge-down signal DN is supplied. This is sent to the line LP. The phase control voltage CTR output from the charge pump 32 is supplied to the phase control circuit 33 and the pseudo lock avoidance circuit 34 via the line LP, respectively.

Phase control circuit 33, while the phase control voltage CTR is increasing for generating a delay adjustment signal CT _P and CT _N to decrease gradually the amount of delay. Meanwhile, while the phase control voltage CTR is decreasing, the phase control circuit 33 generates the delay amount to gradually increase the delay adjustment signal CT _P and CT _N. Phase control circuit 33 supplies such a delay adjustment signal CT _P and CT _N clock generator 2, the enable signal generating unit 6 and the multi-phase clock generator 30. That is, the phase control means comprising a phase comparator 31, charge pump 32 and the phase control circuit 33, position between the reproduced clock signal CK _n and the reference clock signal CLK 1 of the recovered clock signal _CK 1 _{~CK n} in accordance with the delay adjustment signal CT _P and CT _N corresponding to the phase difference, and controls the clock generation unit 2, the enable signal generator 6 and the multi-phase clock generator 30 each delay amount (phase).

  FIG. 5 is a circuit diagram showing the internal configuration of the multiphase clock generator 30.

As shown in FIG. 5, the multiphase clock generator 30 includes variable delay circuits 301 _{1 to} 301 _n connected in series.

FIG. 6 is a circuit diagram showing an internal configuration of each of the variable delay circuits 301 _{1 to} 301 _n .

In FIG. 6, the gate terminals of each of a p-channel MOS (metal-oxide semiconductor) type transistor 311 and an n-channel MOS type transistor 312 are connected to an input terminal I, and each drain terminal is connected via a line L1. The input terminal of the inverter 313 is connected. A power supply voltage VDD is applied to the source terminal of the transistor 311 via the variable resistor 314. Variable resistor 314 changes the resistance value in accordance with the delay adjustment signal CT _P. The ground voltage GND is applied to the source terminal of the transistor 312 via the variable resistor 315. Variable resistor 315 changes the resistance value in accordance with the delay adjustment signal CT _N. Therefore, when a voltage corresponding to the logic level 0 is applied to the input terminal I, the transistor 311 among the transistors 311 and 312 is turned on, and a current flows into the line L1 through the variable resistor 314 and the transistor 311. As a result, the line L1 is charged, and the voltage on the line L1 rises with time. Here, when 0.5 · UI elapses after the voltage corresponding to the logic level 1 is started to be applied to the input terminal I, the voltage on the line L 1 exceeds the threshold voltage of the inverter 313. Therefore, the inverter 313 sends a signal that transitions from the logic level 1 to the logic level 0 via the output terminal Y. In this case, the resistance value of the variable resistor 314 increases in accordance with the delay adjustment signal CT _P, since the amount of current for charging the line L1 is lowered, the voltage rise rate on the line L1 with time is reduced. Therefore, the time until the voltage exceeds the threshold voltage of the inverter 313 becomes longer, and the timing at which the inverter 313 sends the voltage corresponding to the logic level 0 to the output terminal Y is delayed. On the other hand, when a voltage corresponding to the logic level 1 is applied to the input terminal I, the transistor 312 among the transistors 311 and 312 is turned on, and current is drawn from the line L1 through the transistor 312 and the variable resistor 315. As a result, the line L1 is discharged, and the voltage on the line L1 decreases with time. Here, the voltage on the line L <b> 1 falls below the threshold voltage of the inverter 313 when 0.5 · UI elapses after the voltage corresponding to the logic level 0 is started to be applied to the input terminal I. Therefore, the inverter 313 sends a signal that transitions from the logic level 0 to the logic level 1 through the output terminal Y. In this case, the resistance value of the variable resistor 315 increases in accordance with the delay adjustment signal CT _N, since the amount of current which discharges the line L1 is lowered, the voltage decrease rate on line L1 with time is reduced. Therefore, the time until the voltage falls below the threshold voltage of the inverter 313 becomes longer, and the timing at which the inverter 313 sends the voltage corresponding to the logic level 1 to the output terminal Y is delayed.

With the configuration described above, the variable delay circuit 301 _1, the output is supplied to the input terminal I, a delayed the reference clock signal CLK only 0.5 · UI as shown in FIG. 2 as a reproduction clock signal CK ₁ It sends out the terminal Y, and supplies it to the input terminal I of the next stage of the variable delay circuit 301 _2. Variable delay circuits 301 ₂ sends out from the output terminal Y a delayed recovered clock signal CK ₁ only 0.5 · UI as shown in FIG. 2 as a reproduction clock signal CK _2, which the next stage of the variable delay supplied to the input terminal I of the circuit 301 _3. The variable delay circuit 301 _3, sends out from the output terminal Y a delayed recovered clock signal CK ₂ by 0.5 · UI as shown in FIG. 2 as a reproduction clock signal CK _3, which the next stage of the variable delay supplied to the input terminal I of the circuit 301 _4. Similarly, each of the variable delay circuits 301 _{4 to} 301 _n−1 is obtained by delaying the reproduction clock signal CK supplied from the preceding variable delay circuit 301 by 0.5 · UI as shown in FIG. The reproduction clock signals CK _{4 to} CK _n−1 are sent from the respective output terminals Y and supplied to the input terminal I of the variable delay circuit 301 at the next stage. Further, the last stage variable delay circuit 301 _n reproduces the reproduction clock signal CK _n−1 supplied from the preceding stage variable delay circuit 301 _n−1 by delaying it by 0.5 · UI as shown in FIG. transmitted from the output terminal Y as the clock signal CK _n.

Thus, the variable delay circuit ₃₀₁ 1 to 301 _n adjusts the above-described phase control circuit 33 according to the supplied delayed adjusted signal CT _P and CT _N from each of the delay time (0.5 · UI). As a result, the multi-phase clock generation unit 30 including the variable delay circuits 301 _{1 to} 301 _n performs a reproduction that has undergone a phase correction process that should converge the phase difference between the reference clock signal CLK and the reproduction clock signal CK _n to zero. Clock signals CK _{1 to} CK _n are output.

That is, the DLL circuit 3 including the multiphase clock generation unit 30, the phase comparator 31, the charge pump 32, and the phase control circuit 33 performs phase correction to converge the phase error with the reference clock signal CLK to zero. As shown in FIG. 2, the reproduction clock signals CK _{1 to} CK _n are generated by sequentially delaying the phase by 0.5 · UI. In this case, DLL circuit 3 supplies a CK _n of the reproduced clock signal _CK 1 _{~CK n} to the phase comparator 31 supplies a CK ₂ to the clock generation unit 2. Further, the DLL circuit 3 supplies CK ₁ and CK ₂ among the reproduction clock signals CK _{1 to} CK _n to the enable clock selection unit 4 and supplies the reproduction clock signals CK _{1 to} CK _n to the clock selector 5.

The enable clock selection unit 4 first detects the phase difference between the reproduced clock signals CK ₁ and CK ₂ and detects a unit data period UI as shown in FIG. 2 based on the phase difference. For example, since corresponding to the phase difference between the reproduced clock signal CK ₁ and CK ₂ is the delay time of the variable delay circuit 301 ₂ 0.5 UI, enable clock selection unit 4 is twice the phase difference detected as described above By doing so, the unit data cycle UI is obtained. Next, the enable clock selection unit 4 selects a clock phase coefficient ZZ that satisfies the following formula based on the unit data period UI.

2.7 · UI-W _CLK > ZZ · UI> 2.3 · UI
W _CLK : Pulse width of CLKX2

The clock phase coefficient ZZ is a coefficient for relatively expressing the rising edge timing of each of the reproduction clock signals CK _{1 to} CK _{n with} the rising edge timing of the reference clock signal CLK as a base point. For example, in FIG. 2, since the reproduction clock signal CK _n is the reference clock signal CLK and the same phase, the clock phase coefficient ZZ is 0. Further, since the phase of the recovered clock signal CK _n−1 is advanced by 0.5 · UI with respect to the reference clock signal CLK, the clock phase coefficient ZZ is 0.5. That is, the clock phase coefficient ZZ corresponding to each of the reproduction clock signals CK _{1 to} CK _n is assigned in advance. Therefore, the enable clock selection unit 4 selects a clock phase coefficient ZZ that is assigned to each of the recovered clock signals CK _{1 to} CK _n and satisfies the above formula, and 1 corresponding to the selected clock phase coefficient ZZ. Is selected as the rising edge of the enable signal, that is, the enable clock signal CK _(X) for generating the front edge. Then, the enable clock selection unit 4 supplies the clock selector 5 with a clock selection signal S _CK for selecting the enable clock signal CK _(X) .

The clock selector 5 selects the enable clock signal CK _(X) indicated by the clock selection signal S _CK from the reproduced clock signals CK _{1 to} CK _n , and this enable clock signal CK _(X) is an enable signal generator. 6 is supplied. Further, the clock selector 5 selects a reproduction clock signal CK _(X-2) whose phase is delayed by 1 · UI from the reproduction clock signals CK _{1 to} CK _n selected as described above. This is selected and supplied to the enable signal generator 6.

  FIG. 7 is a circuit diagram showing an internal configuration of the enable signal generator 6.

  As shown in FIG. 7, the enable signal generation unit 6 includes an RSFF including a variable delay inverter 61, a variable delay NAND gate 62, a NAND gate 63, and inverters 64 and 65.

The variable delay inverter 61 supplies an inverted set signal obtained by inverting the logic level of the enable clock signal CK _(X) supplied from the clock selector 5 to the input terminal I1 of the NAND gate 63. The variable delay inverter 61 supplies the inverted set signal to the NAND gate 63 with a delay of 0.5 · UI from the time when the enable clock signal CK _(X) transits from the logic level 0 to the logic level 1 state. . At this time, the delay time of the variable delay inverter 61 is adjusted to maintain at all times 0.5 · UI in accordance with the delay adjustment signal _(CT P, CT _N). The inverter 64 supplies an inverted reset signal obtained by inverting the logic level of the recovered clock signal CK _(X-2) supplied from the clock selector 5 to the variable delay NAND gate 62. The output terminal of the NAND gate 63 is connected to the input terminal I 1 of the variable delay NAND gate 62, and the input terminal I 2 of the NAND gate 63 and the input terminal of the inverter 65 are connected to the output terminal of the variable delay NAND gate 62. The variable delay NAND gate 62 delays the output clock signal CK _(X-2) by 0.5 · UI from the time when the reproduction clock signal CK _(X-2) transits from the logic level 0 to the logic level 1, and outputs the output result to each of the NAND gate 63 and the inverter 65. To supply. At this time, the delay time of the variable delay NAND gate 61 is adjusted to maintain at all times 0.5 · UI in accordance with the delay adjustment signal _(CT P, CT _N). The inverter 65 outputs a signal obtained by inverting the logic level of the signal sent from the variable delay NAND gate 62 as the enable signal EN. The internal structure of the variable delay NAND gate 62 is the same as that shown in FIG. 4, and the internal structure of the variable delay inverter 61 is obtained by omitting the inverter 313 from the structure shown in FIG.

With this configuration, as shown in FIG. 2, the enable signal generator 6 transitions from the logic level 0 to the logic level 1 in response to the enable clock signal CK _(X) , and changes to the recovered clock signal CK _(X-2) . In response, an enable signal EN having a pulse waveform that transitions from a logic level 1 to a logic level 0 state is generated. That is, the enable signal generating unit 6, a reproduction clock signal _CK in response to 1 ~Ck _n 1 of the enable clock signal _CK of the _(X), the enable signal EN indicating the section including the reference transition TC as shown in FIG. 2 The front edge portion is generated, and the rear edge portion of the enable signal EN is generated according to the reproduction clock signal CK _(X-2) . The enable signal generation unit 6 includes the variable delay inverter 61 and the variable delay NAND gate 62 described above, thereby enabling the front edge timing of the enable clock signal CK _(X) or CK _(X-2) as shown in FIG. , The enable signal EN is output with a delay of 1.0 · UI. In this case, such delay time is adjusted to maintain always 1.0 · UI in accordance with the delay adjustment signal _(CT P, CT _N). That is, the variable delay inverter 61 and the variable delay NAND gate 62 operate as variable delay transmission means for transmitting the enable clock signal CK _(X) at a timing delayed by the unit data period UI. The enable signal generator 6 supplies the enable signal EN generated as described above to the clock generator 2.

  Hereinafter, the operation of generating the recovered clock signal (CK) by the clock data recovery circuit 100 shown in FIG. 1 will be described.

  First, the transition detection unit 1 detects a front edge part and a rear edge part in which a data bit value transitions from the received data signal DIN, and transitions from a logic level 0 to a logic level 1 state at the time of detection of each edge part. A transition detection signal CLKX2 having a short pulse waveform as shown in FIG. 2 is generated.

  Next, in response to a logic level 1 enable signal EN that is to receive only a pulse corresponding to the reference transition section TC from the transition detection signal CLKX2, the clock generation section 2 applies a reference transition section TC as shown in FIG. A synchronized reference clock signal CLK is generated.

Then, the DLL circuit 3 generates and outputs multi-phase reproduction clock signals CK _{1 to} CK _n having a phase delayed by 0.5 · UI in synchronization with the reference clock signal CLK.

At this time, in generating the above-described enable signal EN, the enable generating means including the enable clock selecting unit 4, the clock selector 5, and the enable signal generating unit 6 is first based on the recovered clock signals (CK ₁ , CK ₂ ). The unit data period UI shown in FIG. 2 is obtained. Then, the enable generation means generates an enable signal EN whose front edge portion appears within a range TW from time t1 to t2 as shown in FIG. 8 based on the unit data cycle UI. The time point t1 is a pulse immediately before the pulse CP corresponding to the reference transition portion TC in the transition detection signal CLKX2 in which the front edge portion of the enable signal EN is added with a jitter margin of 0.3 · UI. it is a point of CP _F and temporally non-overlapping limit. That is, when the front edge of the enable signal EN appears a point in time before t1, it will capture the pulse CP _F immediately before the pulse CP to be captured originally, which leads to reduced accuracy of the reference clock signal CLK. The time point t2 is a time point that is ahead of the front edge portion of the pulse CP by a setup time considering a jitter margin of 0.3 · UI. That is, if the front edge portion of the enable signal EN appears at a time later than the time t2, the pulse CP cannot be reliably captured, and the accuracy of the reference clock signal CLK is reduced.

Therefore, in the enable generation means (4 to 6), in order to generate the above-described enable signal EN, first, the enable clock selection unit 4 and the clock selector 5 enable one of the reproduction clock signals CK _{1 to} CK _n. It is selected as an enable clock signal CK _(X) for signal generation. Then, the enable signal generation unit 6 generates a front edge portion of the enable signal EN according to the enable clock signal CK _(X), and a rear edge portion of the enable signal EN according to the reproduction clock signal CK _(X-2). Generate. That is, for the selected enable clock signal CK _(X) , the front edge portion of the enable signal EN appears after the processing delay time by the enable signal generator 6 has elapsed. At this time, the processing delay time by the enable signal generation unit 6 is 1.0 · UI due to the variable delay inverter 61 and the variable delay NAND gate 62 provided in the enable signal generation unit 6. Therefore, as shown in FIG. 8, the enable clock selection unit 4 and the clock selector 5 bring the range TW from the time point t1 to t2 at which the front edge portion of the enable signal EN should be included to the previous time by 1.0 · UI. The enable clock signal CK _(X) whose front edge portion is included in the shifted range (ZZ · UI ₎ is selected. At this time, the timing of the front edge portion of each of the reproduction clock signals CK _{1 to} CK _n is represented by the clock phase coefficient ZZ based on the front edge timing of the reference clock signal CLK as described above. Further, the reference clock signal CLK is only 1.0 · UI from the front edge portion of the pulse CP in the transition detection signal CLKX2 by the variable delay NAND gates 21 and 22 formed in the clock generation unit 2 as shown in FIG. Output with a delay. Therefore, the enable clock selection unit 4 and the clock selector 5 generate the enable signal EN whose front edge portion is included in the range TW shown in FIG. 8 from among the reproduction clock signals CK _{1 to} CK _n . As shown in FIG. 4, the enable clock signal CK _(X) including the front edge portion within the range (ZZ · UI) satisfying the above formula is selected.

  Therefore, according to the enable generation means (4 to 6), at the timing (within the range TW) in which only the pulse CP corresponding to the reference transition portion TC is reliably captured from the transition detection signal CLKX2 by following the unit data cycle UI. A front edge portion of an enable signal indicating a section corresponding to the reference transition portion (TC) is generated.

Therefore, even if the unit data cycle UI is shortened due to the high-speed communication operation, a highly accurate reference clock signal CLK synchronized with only the reference transition unit TC in the received data signal DIN is obtained, and based on this reference clock signal CLK It becomes possible to reproduce multi-phase reproduction clock signals (CK _{1 to} CK _n ) having different phases.

  Next, a pseudo lock avoidance operation by the pseudo lock avoidance circuit 34 included in the DLL circuit 3 will be described.

  FIG. 9 is a circuit diagram showing an example of the internal configuration of the pseudo lock avoidance circuit 34.

  As shown in FIG. 9, the pseudo lock avoidance circuit 34 includes a voltage dividing circuit 341, comparators 342 and 343, a p-channel MOS transistor 344, NAND gates 345 and 346, and an inverter 347.

The voltage dividing circuit 341 has a plurality of resistors connected in series between the power supply voltage VDD and the ground voltage GND, and as shown in FIG. 10, an upper reference voltage value VH _REF lower than the power supply voltage VDD and further higher than this VH _REF. A low lower reference voltage value VL _REF is generated.

The comparator 342 compares the above upper limit reference voltage value VH _REF with the phase control voltage CTR sent from the charge pump 32. The comparator 342, as shown in FIG. 10, when the phase control voltage CTR is less than the upper limit reference voltage value _{VH REF} indicates the logic level 1, a logic level 0 when the phase control voltage CTR becomes larger than the upper limit reference voltage value _{VH REF} supplied to the input terminal I1 of the NAND gate 345 limit over signal _{X OV} showing the.

The comparator 343 compares the lower limit reference voltage value VL _REF described above with the phase control voltage CTR sent from the charge pump 32. The comparator 343, as shown in FIG. 10, when the phase control voltage CTR is lower reference voltage value VL _REF above indicates the logical level 1, a logic level 0 when the phase control voltage CTR becomes smaller than the lower limit reference voltage value VL _REF supplied to the input terminal I2 of the NAND gate 346 to lower under signal X _UD indicating the.

The output terminal of the NAND gate 345 is connected to the input terminal I1 of the NAND gate 346. The output terminal of the NAND gate 346 is connected to the input terminal I2 of the NAND gate 345 and the input terminal of the inverter 347. The inverter 347 uses a signal obtained by inverting the logic level of the signal sent from the NAND gate 346 as the precharge control signal X _ALK and supplies it to the gate terminal of the precharge transistor 344.

That is, the RSFF including the NAND gates 345 and 346 and the inverter 347 is reset according to the lower limit under signal X _UD indicating the logic level 0. That is, this RSFF enters a reset state when the phase control voltage CTR transitions from a state where the phase control voltage CTR is greater than or equal to the lower limit reference voltage value VL _REF to a state below this VL _REF , and a logic level 0 precharge control signal indicating precharge execution X _ALK is supplied to the gate terminal of transistor 344. On the other hand, the RSFF is set according to the upper limit over signal X _OV indicating the logic level 0. In other words, this RSFF is set when the phase control voltage CTR transitions from a state where the phase control voltage CTR is lower than or equal to the upper reference voltage value VH _REF to a state where the phase control voltage CTR is greater than this VH _REF , and logic level 1 precharge control indicating precharge stop Signal X _ALK is supplied to the gate terminal of transistor 344.

A power supply voltage VDD is supplied to the source terminal of the transistor 344, and its drain terminal is connected to a line LP that is a supply line of the phase control voltage CTR. The transistor 344 is turned on only when the logic level 0 precharge control signal X _ALK indicating precharge execution is supplied, and precharges the line LP with the power supply voltage VDD.

  FIG. 11 is implemented by the pseudo lock avoidance circuit 34 when the enable signal EN is delayed due to the influence of external noise and the pulse CP corresponding to the reference transition unit TC cannot be captured from the transition detection signal CLKX2. It is a time chart which shows an example of the pseudo lock avoidance operation.

As shown in FIG. 11, when the pulse CP corresponding to the reference transition unit TC cannot be captured, the clock generation unit 2 sends out the reference clock signal CLK that does not include the clock pulse. At this time, although a new reproduction clock signal CK synchronized with the pulse CP is not generated, the reproduction clock signal CK _n synchronized with the pulse CP in the transition detection signal CLKX2 fetched last time is supplied to the phase comparator 31. Supplied. Therefore, the phase comparator 31, because only the clock pulses by the playback clock signal CK _n is supplied, as shown in FIG. 11, only the charge pump 32 DN of the charge-up signal UP and the charge-down signal DN Supply begins. In response to the charge-down signal DN, the charge pump 32 decreases the voltage value of the phase control voltage CTR as shown in FIG. Here, when the voltage value of the phase control voltage CTR falls below VL _REF , the comparator 343 of the pseudo lock avoidance circuit 34 generates a lower limit under signal X _UD that shifts to a logic level 0 state as shown in FIG. In response to the lower under signal _{X UD,} RSFF pseudo lock avoidance circuit 34 (345-347) becomes the reset state, and supplies a precharge control signal _{X ALK} at logic level 0 to the transistor 344 for precharging. Therefore, during this time, the transistor 344 precharges the line LP with the power supply voltage VDD. As a result, the voltage value of the phase control voltage CTR gradually increases as shown in FIG. Here, when the voltage value of the phase control voltage CTR exceeds VH _REF , the comparator 342 of the pseudo lock avoidance circuit 34 generates an upper limit over signal X _OV that transitions to a logic level 0 state as shown in FIG. In response to the limit over signal _{X OV,} RSFF pseudo lock avoidance circuit 34 (345-347) becomes a set state, supplies the precharge control signal _{X ALK} at logic level 1 to the transistor 344 for precharging. Therefore, in response to the logic level 1 precharge control signal X _ALK , the transistor 344 stops the precharge operation for the line LP.

Thus, the precharge operation for such line LP and the voltage value of the phase control voltage CTR is relatively predetermined upper reference voltage value VH _REF vicinity as shown in FIG. 11, is maintained in a high voltage state. That is, even when the phase comparator 31 continues to send only the charge-down signal DN to the charge pump 32 due to the influence of external noise, that is, when the charge pump operation is stopped, the line LP is preloaded at this time. Since it is charged, the voltage value of the phase control voltage CTR can be maintained at a high voltage value in the vicinity of VH _REF .

Thus, thereafter, when the now uptake is made of pulse CP corresponding to the reference transition TC from among transition detection signal CLKX2 the phase control voltage CTR is an upper limit reference voltage value VH _REF high voltage values of the neighboring From this state, the DLL circuit 3 starts the initial synchronization.

  Therefore, according to the pseudo lock avoidance circuit 34, it is possible to avoid the pseudo lock that occurs when the DLL circuit 3 starts the initial synchronization from the state where the phase control voltage CTR is at a low voltage near the ground voltage GND. It becomes.

  Even when no external noise is generated, the operation of the charge pump 32 becomes unstable immediately after the power is turned on, so that a false lock may occur depending on the supplied power supply voltage value or the environmental temperature.

  FIG. 12 is a circuit diagram showing another example of the internal configuration of the pseudo lock avoidance circuit 34 that can prevent the pseudo lock that may occur immediately after the power is turned on.

  The configuration shown in FIG. 12 is the same as the configuration shown in FIG. 9 except that a p-channel MOS transistor 348, an n-channel MOS transistor 349, and a power-on reset circuit 350 are added.

  That is, in the configuration shown in FIG. 12, the drain terminal of the transistor 344 is connected to the source terminal of the transistor 348, and the drain terminal of the transistor 348 is connected to the line LP. The drain terminal of the transistor 349 is connected to the line LP, and the ground voltage GND is applied to its source terminal. The power-on reset circuit 350 generates a one-pulse power-on reset signal POR that becomes high only for a period TQ as shown in FIG. 13 in response to power-on, and supplies this to the gate terminals of the transistors 348 and 349. .

  FIG. 13 is a time chart showing an example of the pseudo lock avoidance operation performed immediately after the power is turned on in the pseudo lock avoidance circuit 34.

First, when the clock data recovery circuit 100 starts to be turned on, the voltage value of the power supply voltage VDD gradually increases with time, and reaches a desired peak voltage value at time t1. Following the transition of the voltage value of the power supply voltage VDD, the power-on reset signal POR, the upper limit reference voltage value VH _REF and the lower limit reference voltage value VL _REF also gradually increase as shown in FIG. The peak voltage value is reached and maintained. Here, the voltage value of the power-on reset signal POR changes to the level of the ground voltage GND (0 volt) when the period TQ elapses from the time point t1. Note that while the power-on reset signal POR is in a high voltage state, the transistor 348 is off and the transistor 349 is on. Thus, a state in which the ground voltage GND to the line LP is applied, that is becomes a discharge state, and therefore, the voltage value of an output value of a charge pump 32 phase control voltage CTR is the state of the ground voltage GND (0 V) maintain. During this time, since the transistor 348 is in the OFF state, the through current flowing in the current paths of the transistors 344, 348, and 349 is blocked.

Thereafter, when the voltage value of the power-on reset signal POR transitions to 0 volts, the transistor 349 is turned off and the transistor 348 is turned on, so that the precharge for the line LP is started. As a result, the voltage value of the phase control voltage CTR gradually increases as shown in FIG. Then, when the voltage value of the phase control voltage CTR exceeds the upper limit reference voltage value VH _REF , the comparator 342 sends out an upper limit over signal X _OV indicating a logic level 0. In response to this, RSFF (345 to 347) is set and supplies a precharge control signal X _ALK of logic level 1 to the precharge transistor 344. In response to the logic level 1 precharge control signal X _ALK , the transistor 344 stops the precharge operation for the line LP. Therefore, after that, when the DLL circuit 3 executes the initial synchronization, the initial synchronization is started from the state in which the phase control voltage CTR has the power supply voltage VDD, so that the pseudo lock does not occur.

  Thus, in the configuration shown in FIG. 12, the line LP is discharged once over the period TQ immediately after power-on so that the phase control voltage CTR sent from the charge pump 32 onto the line LP does not become unstable when the power is turned on. The line LP is precharged after the state (the transistor 349 is turned on).

  Therefore, according to such a configuration, the output voltage value (CTR) of the charge pump 32 that becomes unstable immediately after the power is turned on can be maintained at a high voltage value near the power supply voltage VDD. In the initial synchronization of the DLL circuit 3 that is performed first, pseudo lock is avoided.

  In the clock data recovery circuit 100 shown in FIG. 1, the DLL circuit (3) is used as the synchronization circuit, but the same applies when a PLL circuit (phase locked loop) circuit is used instead of the DLL circuit. The pseudo lock avoidance circuit 34 shown in FIG. 9 or FIG. 13 can avoid the pseudo lock described above.

In short, the clock data recovery circuit (100) according to the present invention uses the clock generation means to generate the reference clock signal (CLK) synchronized with the data transition point (TC) appearing every predetermined period (P) in the input data signal (DIN). Generated by (1, 2). Then, the synchronization circuit (3) according to the present invention generates a recovered clock signal (CK) synchronized with the reference clock signal. At this time, the synchronization circuit generates a phase control voltage (CTR) having a voltage value corresponding to the phase difference between the reference clock signal and the recovered clock signal and sends it to the first line (LP). to include a charge pump (32), a phase control circuit for controlling the phase of the recovered clock signal in response to such a phase control voltage (33), following such false-lock avoidance circuit (34). The pseudo lock avoidance circuit starts precharging the first line (LP) when the phase control voltage (CTR) falls below the lower limit reference voltage (VL _REF ), and this phase control voltage becomes the upper limit reference voltage (VH _REF ). The voltage value of the phase control voltage is maintained at a high voltage state by continuing the precharge operation for the first line until the value exceeds.

As a result, even if the charge pump operation is substantially stopped due to the influence of external noise, the first line is forcibly precharged at this time, so that the voltage of the phase control voltage is set to a high voltage value. It can be maintained. Therefore, after that, when the initial synchronization is started by the synchronization circuit, the synchronization circuit (3) is initialized from the state where the phase control voltage (CTR) is at a high voltage value near the upper limit reference voltage (VH _REF ). Synchronization will begin. Therefore, according to the pseudo lock avoidance circuit (34), it is possible to avoid the pseudo lock that occurs when the synchronization circuit starts the initial synchronization from the state where the phase control voltage is at a low voltage near the ground voltage. It becomes.

DESCRIPTION OF SYMBOLS 1 Transition detection part 2 Clock generation part 3 DLL circuit 31 Phase comparator 32 Charge pump 33 Phase control circuit 34 Pseudo lock avoidance circuit 342, 343 Comparator 344 Transistor

Claims (4)

A synchronization circuit for generating a recovered clock signal synchronized with a reference clock signal,
A charge pump that generates a phase control voltage having a voltage value corresponding to a phase difference between the reference clock signal and the recovered clock signal and sends the voltage to the first line;
A phase control circuit for controlling the phase of the recovered clock signal in accordance with the phase control voltage;
A pseudo lock avoidance circuit that starts precharging the first line when the phase control voltage falls below a lower limit reference voltage, and continues the precharge operation for the first line until the phase control voltage exceeds the upper limit reference voltage. And including
The pseudo lock avoidance circuit compares the phase control voltage with the lower limit reference voltage, and generates a lower limit under signal when the phase control voltage is smaller than the lower limit reference voltage;
A second comparator that performs a magnitude comparison between the phase control voltage and the upper limit reference voltage, and generates an upper limit over signal when the phase control voltage is greater than the upper limit reference voltage;
The first line is precharged by applying a power supply voltage to the first line in response to the lower limit under signal, while the application of the power supply voltage to the first line is stopped in response to the upper limit over signal. And a precharge transistor that stops precharging . A power-on reset circuit that generates a one-pulse power-on reset signal when the power is turned on;
The synchronization circuit according to claim 1, further comprising a discharge transistor that discharges the first line for a predetermined period in response to the power-on reset signal . Clock data recovery comprising: clock generation means for generating a reference clock signal synchronized with a data transition point appearing every predetermined period in an input data signal; and synchronization means for generating a recovered clock signal synchronized with the reference clock signal A circuit,
The synchronization means includes
A charge pump that generates a phase control voltage having a voltage value corresponding to a phase difference between the reference clock signal and the recovered clock signal and sends the voltage to the first line;
A phase control circuit for controlling the phase of the recovered clock signal in accordance with the phase control voltage;
A pseudo lock avoidance circuit that starts precharging the first line when the phase control voltage falls below a lower limit reference voltage, and continues the precharge operation for the first line until the phase control voltage exceeds the upper limit reference voltage. And including
The pseudo lock avoidance circuit compares the phase control voltage with the lower limit reference voltage, and generates a lower limit under signal when the phase control voltage is smaller than the lower limit reference voltage;
A second comparator that performs a magnitude comparison between the phase control voltage and the upper limit reference voltage, and generates an upper limit over signal when the phase control voltage is greater than the upper limit reference voltage;
The first line is precharged by applying a power supply voltage to the first line in response to the lower limit under signal, while the application of the power supply voltage to the first line is stopped in response to the upper limit over signal. A clock data recovery circuit comprising: a precharge transistor that stops precharging by performing a precharge transistor . A power-on reset circuit that generates a one-pulse power-on reset signal in response to power-on; and a discharge transistor that discharges the first line in response to the power-on reset signal over a predetermined period. The clock data recovery circuit according to claim 3 .

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