CN108091570B - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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CN108091570B
CN108091570B CN201611061525.1A CN201611061525A CN108091570B CN 108091570 B CN108091570 B CN 108091570B CN 201611061525 A CN201611061525 A CN 201611061525A CN 108091570 B CN108091570 B CN 108091570B
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contact hole
dielectric layer
sccm
gas flow
gate structure
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CN108091570A (zh
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韩秋华
唐龙娟
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Beijing Corp
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Abstract

本发明公开了半导体装置及其制造方法，涉及半导体技术领域。该方法包括：提供衬底结构，包括位于衬底上的一个或多个半导体鳍片；位于鳍片上的栅极结构；位于鳍片中在栅极结构至少一侧的有源区；以及至少覆盖有源区的层间电介质层；在层间电介质层和栅极结构之上形成硬掩模层；利用图案化的掩模通过刻蚀形成在有源区上方的穿过硬掩膜层并延伸到层间电介质层的一部分中的第一接触孔；在第一接触孔的侧壁上形成侧壁电介质层，以部分填充第一接触孔。由于采用非自对准工艺生成上半部分接触孔并在孔壁上形成侧壁电介质层，以侧壁电介质层作为掩模刻蚀生成下半部分接触孔，能够有效避免接触件与栅极之间发生的漏电，并且使得栅极之间的电容较小。

Description

半导体装置及其制造方法
技术领域
本发明涉及半导体技术领域，特别涉及半导体装置及其制造方法。
背景技术
鳍式场效应晶体管(Fin Field-Effect Transistor，简称为FinFET)是一种新的互补式金氧半导体(CMOS)晶体管，具有较好的短沟道效应控制能力、较高的驱动电流和较低的耗电量，具有功耗低，面积小的优点，其有希望延续摩尔定律，已经开始14纳米节点推进。目前，在鳍式场效应晶体管形成有源区的接触件的工艺中，通常采用自对准技术刻蚀出到达有源区的接触孔，并在接触孔中填充导电材料，形成接触件。如图1所示，在采用自对准技术刻蚀接触孔时，会在栅极绝缘层01、03的侧壁上形成坡口，坡口使得栅极绝缘层01、03较薄，并且采用自对准技术刻蚀能够使接触孔的下部尺寸较大，在填充导电材料形成接触件05后，容易发生栅极02、04与接触件05之间的漏电现象，影响产品的质量。
发明内容
本发明的发明人发现上述现有技术中存在问题，并因此针对所述问题中的至少一个问题提出了新的技术方案。
本发明一个实施例的目的之一是：提供一种半导体装置的制造方法。本发明一个实施例的目的之一是：提供一种半导体装置，从而减少接触件与栅极之间漏电现象的发生。
根据本发明的第一方法，提供了一种半导体装置的制造方法，包括以下步骤：提供衬底结构，所述衬底结构包括：衬底；位于所述衬底上的一个或多个半导体鳍片；位于所述鳍片上的栅极结构；位于所述鳍片中在所述栅极结构至少一侧的有源区；以及至少覆盖所述有源区的层间电介质层；在所述层间电介质层和所述栅极结构之上形成硬掩模层；利用图案化的掩模通过刻蚀形成在所述有源区上方的穿过所述硬掩膜层并延伸到所述层间电介质层的一部分中的第一接触孔；在所述第一接触孔的侧壁上形成侧壁电介质层，以部分填充所述第一接触孔；以所述侧壁电介质层作为掩模，刻蚀所述第一接触孔的底部的层间电介质层，以形成延伸至所述有源区的第二接触孔。
在一些实施例中，以导电材料填充所述第一接触孔和所述第二接触孔以形成到所述有源区的接触件。
在一些实施例中，对所述衬底结构进行刻蚀以形成第一接触孔的步骤以下列条件执行：将C4F8、C4F6连同氧气和载流气体通入反应腔室，在10毫托至100毫托的压强下，在100w至2000w的功率下执行；其中，所述C4F8的气体流量范围为10sccm至50sccm；所述C4F6的气体流量范围为10sccm至50sccm；所述氧气的气体流量范围为5sccm至30sccm；所述载流气体的气体流量范围为50sccm至1000sccm。
在一些实施例中，所述第一接触孔的深度为3－30nm，所述第一接触孔的宽度为30－40nm。
在一些实施例中，通过沉积工艺在所述第一接触孔的侧壁上形成低K氮化硅层作为所述侧壁电介质层，所述低K氮化硅层的厚度为2－10nm，K值为3－5。
在一些实施例中，在形成低k氮化硅层之后，以及形成第二接触孔之前，所述方法还包括：对所述低k氮化硅层进行表面刻蚀处理。
在一些实施例中，所述表面刻蚀处理以下列条件执行：将CH3F连同氧气通入反应腔室，在2毫托至30毫托的压强下，在100w至1000w的功率下执行；其中，所述CH3F的气体流量范围为20sccm至200sccm；所述氧气的气体流量范围为50sccm至200sccm。
在一些实施例中，所述自对准地刻蚀以形成第二接触孔的步骤以下列条件执行：将C4F8、C4F6连同氧气和载流气体通入反应腔室，在10毫托至100毫托的压强下，在100w至2000w的功率下执行；其中，所述C4F8的气体流量范围为10sccm至50sccm；所述C4F6的气体流量范围为10sccm至50sccm；所述氧气的气体流量范围为5sccm至30sccm；所述载流气体的气体流量范围为50sccm至1000sccm。
在一些实施例中，所述栅极结构包括：包绕所述鳍片的至少一部分的栅极电介质；在所述栅极电介质上的金属栅极；以及在所述金属栅极两侧的间隔物。
在一些实施例中，所述第一接触孔的底部和顶部的截面尺寸相等；所述第二接触孔的底部和顶部的截面尺寸相等。
在一些实施例中，去除所述图案化的掩模。
在一些实施例中，所述有源区包括源极和/或漏极。
根据本发明的第二方面，提供一种半导体装置，包括：半导体衬底；位于所述半导体衬底上的一个或多个鳍片；位于所述鳍片上的栅极结构；位于所述鳍片上在所述栅极结构两侧的源极和漏极；覆盖在所述源极和所述漏极上的层间电介质层；以及在所述层间电介质层和所述栅极结构上的硬掩模层；在所述源极或所述漏极上方穿过所述硬掩膜层并延伸到所述层间电介质层中的第一接触孔；在所述第一接触孔的侧壁上的低k氮化硅层；在所述第一接触孔的下方且延伸至所述源极或所述漏极的第二接触孔；以及在所述第一接触孔和所述第二接触孔中接触所述源极或所述漏极的金属连接件。
在一些实施例中，所述栅极结构为高k金属栅极结构。
在一些实施例中，所述第一接触孔的深度为3－30nm，所述第一接触孔的宽度为30－40nm。
在一些实施例中，所述低k氮化硅层的厚度为2－10nm，k值为3－5。
在一些实施例中，所述第一接触孔的底部和顶部的截面尺寸相等；所述第二接触孔的底部和顶部的截面尺寸相等。
本发明中，采用非自对准工艺生成上半部分接触孔，并在孔壁上形成侧壁电介质层，以侧壁电介质层作为掩模刻蚀生成下半部分接触孔，使得接触孔的孔径较小，接触件距离栅极较远，能够有效避免接触件与栅极之间漏电现象的发生，并且，由于在接触孔上添加了侧壁电介质层，使得栅极之间的电容较小，能够提高半导体装置的性能。
通过以下参照附图对本发明的示例性实施例的详细描述，本发明的其它特征及其优点将会变得清楚。
附图说明
构成说明书的一部分的附图描述了本发明的实施例，并且连同说明书一起用于解释本发明的原理。
参照附图，根据下面的详细描述，可以更加清楚地理解本发明，其中：
图1是现有技术中采用自对准技术形成接触件后的半导体装置结构的横截面示意图。
图2是示出根据本发明一些实施例的半导体装置的制造方法的流程图。
图3是示意性地示出根据本发明一些实施例的半导体装置的制造过程中的一个阶段的结构的横截面示意图。
图4是示意性地示出根据本发明一些实施例的半导体装置的制造过程中的一个阶段的结构的横截面示意图。
图5是示意性地示出根据本发明一些实施例的半导体装置的制造过程中的一个阶段的结构的横截面示意图。
图6是示意性地示出根据本发明一些实施例的半导体装置的制造过程中的一个阶段的结构的横截面示意图。
图7是示意性地示出根据本发明一些实施例的半导体装置的制造过程中的一个阶段的结构的横截面示意图。
具体实施方式
现在将参照附图来详细描述本发明的各种示例性实施例。应注意到：除非另外具体说明，否则在这些实施例中阐述的部件和步骤的相对布置、数字表达式和数值不限制本发明的范围。
同时，应当明白，为了便于描述，附图中所示出的各个部分的尺寸并不是按照实际的比例关系绘制的。
以下对至少一个示例性实施例的描述实际上仅仅是说明性的，决不作为对本发明及其应用或使用的任何限制。
对于相关领域普通技术人员已知的技术、方法和设备可能不作详细讨论，但在适当情况下，所述技术、方法和设备应当被视为授权说明书的一部分。
在这里示出和讨论的所有示例中，任何具体值应被解释为仅仅是示例性的，而不是作为限制。因此，示例性实施例的其它示例可以具有不同的值。
应注意到：相似的标号和字母在下面的附图中表示类似项，因此，一旦某一项在一个附图中被定义，则在随后的附图中不需要对其进行进一步讨论。下文中的“第一”、“第二”等，仅仅为描述上相区别，并没有其它特殊的含义。
图2是示出根据本发明一些实施例的半导体装置的制造方法的流程图。图3至图7分别是示意性地示出根据本发明一些实施例的半导体装置的制造过程中的若干阶段的结构的横截面示意图。下面结合图2以及图3至图7描述本发明实施例的半导体装置的制造过程。
在步骤S11，提供衬底结构，衬底结构包括：衬底；位于衬底上的一个或多个半导体鳍片。如图3、4所示，衬底结构包括：衬底(例如硅衬底)20、位于该衬底20上的2个鳍片22、23，鳍片的材料可以为硅。
位于鳍片上的栅极可以有多种结构，例如，栅极结构包括：包绕鳍片的至少一部分的栅极电介质、在栅极电介质上的金属栅极和在金属栅极两侧的间隔物。栅极可以采用多种工艺方法进行制造，例如，采用HKMG(high-k绝缘层-金属蹦极)制造工艺等。
在一些实施例中，位于鳍片23上的栅极结构包括：栅极30、功函数调节层31、高K电介质层32、栅极电介质3和间隔物34。位于鳍片22上的栅极结构包括：栅极40、功函数调节层41、高K电介质层42、栅极绝缘物43和间隔物44。
在栅极结构至少一侧具有有源区。半导体装置可为NMOS型或PMOS型。有源区可以包括源极51和漏极52、源极53和漏极54。在源极51和漏极52、源极53和漏极54上覆盖有源区的层间电介质层26。层间电介质层26可以为氧化硅。在一个实施例中，衬底结构还可以包括第一绝缘物24和第二绝缘物27，在层间电介质层26和栅极结构之上形成氮化硅层21。
在步骤S12，在层间电介质层26和栅极结构之上形成硬掩模层。
在步骤S13，利用图案化的掩模通过刻蚀形成在有源区上方的穿过硬掩膜层并延伸到层间电介质层的一部分中的第一接触孔。如图4所示，在经过刻蚀后，在源极51和漏极52，以及源极53和漏极54的上方形成了延伸到层间电介质层26的一部分中的第一接触孔11。第一接触孔的尺寸可以根据不同的需求进行设置，例如，第一接触孔的深度为3－30nm，第一接触孔的宽度为30－40nm。
在一些实施例中，对衬底结构进行刻蚀以形成第一接触孔的执行条件可以根据不同的工艺要求进行设置。例如，将C4F8、C4F6连同氧气和载流气体通入反应腔室，在10毫托至100毫托的压强下，在100w至2000w的功率下执行，例如10000W；其中，C4F8的气体流量范围为10sccm至50sccm，例如20sccm；C4F6的气体流量范围为10sccm至50sccm，例如30sccm；氧气的气体流量范围为5sccm至30sccm，例如15sccm；载流气体的气体流量范围为50sccm至1000sccm，例如500sccm。
在步骤S14，在第一接触孔11的侧壁上形成侧壁电介质层，以部分填充第一接触孔。如图5所示，在第一接触孔11的侧壁上形成了电介质层12。可以通过多种工艺形成电介质层12，例如，通过沉积工艺在第一接触孔11的侧壁上形成低K氮化硅层作为侧壁电介质层，低K氮化硅层的厚度为2－10nm，例如8nm，K值为3－5，例如4。
在步骤S15中，以侧壁电介质层12作为掩模，自对准地刻蚀第一接触孔的底部的层间电介质层，以形成延伸至有源区的第二接触孔。
在一些实施例中，第一接触孔的底部和顶部的截面尺寸相等，第二接触孔的底部和顶部的截面尺寸相等。如图6所示，经过对第一接触孔的底部进行刻蚀后，形成延伸至源极51和漏极52以及源极53和漏极54的第二接触孔13。如图7所示，以导电材料填充第一接触孔和第二接触孔以形成到有源区的接触件14。
至此，提供了根据本发明一些实施例的半导体装置的制造方法。采用非自对准工艺生成上半部分接触孔，并在孔壁上形成侧壁电介质层，以侧壁电介质层作为掩模刻蚀生成下半部分接触孔，使得接触孔的孔径较小，接触件距离栅极较远，能够有效避免接触件与栅极之间的漏电现象发生。
在一些实施例中，在形成电介质层12，即低k氮化硅层之后，并在形成第二接触孔13之前，对低k氮化硅层进行表面刻蚀处理，已保证第一接触孔11的尺寸以及侧壁的光洁度。进行表面刻蚀可以采用多种工艺方法，例如，表面刻蚀处理以下列条件执行：将CH3F连同氧气通入反应腔室，在2毫托至30毫托的压强下，在100w至1000w的功率下执行，例如500w；其中，CH3F的气体流量范围为20sccm至200sccm，例如100sccm；氧气的气体流量范围为50sccm至200sccm，例如100sccm。
自对准地刻蚀以形成第二接触孔13的步骤以下列条件执行：将C4F8、C4F6连同氧气和载流气体通入反应腔室，在10毫托至100毫托的压强下，在100w至2000w的功率下执行，例如500w；其中，C4F8的气体流量范围为10sccm至50sccm，例如30sccm；C4F6的气体流量范围为10sccm至50sccm，例如30sccm；氧气的气体流量范围为5sccm至30sccm，例如20sccm；载流气体的气体流量范围为50sccm至1000sccm，例如200sccm。
本发明还提供了一种半导体装置，例如如图7所示，该半导体装置可以包括：半导体衬底20；位于半导体衬底上的一个或多个鳍片22、23；位于鳍片上的栅极结构；位于鳍片22、23上在栅极结构两侧的源极51、53和漏极52、54。覆盖在源极51、53和漏极52、54上的层间电介质层26，以及在层间电介质层26和栅极结构上的硬掩模层；在源极51、53或漏极52、54上方穿过硬掩膜层并延伸到层间电介质层26中的第一接触孔；在第一接触孔的侧壁上的低k氮化硅层12；在第一接触孔的下方且延伸至源极51、53或漏极52、54的第二接触孔；以及在第一接触孔和第二接触孔中接触源极51、53或漏极52、54的金属连接件14。
在一些实施例中，栅极结构为高k金属栅极结构，第一接触孔的深度为3－30nm，第一接触孔的宽度为30－40nm。低k氮化硅层12的厚度为2－10nm，k值为3－5。第一接触孔的底部和顶部的截面尺寸相等，第二接触孔的底部和顶部的截面尺寸相等。
上述实施例中的半导体装置的制造方法及半导体装置，采用非自对准工艺生成上半部分接触孔，并在孔壁上形成侧壁电介质层，以侧壁电介质层作为掩模刻蚀生成下半部分接触孔，使得接触孔的孔径较小，接触件距离栅极较远，能够有效避免接触件与栅极之间的漏电现象发生，并且，由于添加了侧壁电介质层，使得栅极之间的电容较小，能够提高半导体装置的性能。
至此，已经详细描述了根据本发明的制造半导体器件的方法和所形成的半导体器件。为了避免遮蔽本发明的构思，没有描述本领域所公知的一些细节。本领域技术人员根据上面的描述，完全可以明白如何实施这里公开的技术方案。
虽然已经通过示例对本发明的一些特定实施例进行了详细说明，但是本领域的技术人员应该理解，以上示例仅是为了进行说明，而不是为了限制本发明的范围。本领域的技术人员应该理解，可在不脱离本发明的范围和精神的情况下，对以上实施例进行修改。本发明的范围由所附权利要求来限定。

Claims (17)

1.一种半导体装置的制造方法，其特征在于，包括以下步骤：
提供衬底结构，所述衬底结构包括：
衬底；
位于所述衬底上的一个或多个半导体鳍片；
位于所述鳍片上的栅极结构；
位于所述鳍片中在所述栅极结构至少一侧的有源区；以及
至少覆盖所述有源区的层间电介质层；
在所述层间电介质层和所述栅极结构之上形成硬掩模层；
利用图案化的掩模通过刻蚀形成在所述有源区上方的穿过所述硬掩膜层并延伸到所述层间电介质层的一部分中的第一接触孔；
在所述第一接触孔的侧壁上形成侧壁电介质层，以部分填充所述第一接触孔；其中，通过沉积工艺在所述第一接触孔的侧壁上形成低K氮化硅层作为所述侧壁电介质层；
以所述侧壁电介质层作为掩模，刻蚀所述第一接触孔的底部的层间电介质层，以形成延伸至所述有源区的第二接触孔。
2.如权利要求1所述的方法，其特征在于，还包括：
以导电材料填充所述第一接触孔和所述第二接触孔以形成到所述有源区的接触件。
3.如权利要求1所述的方法，其特征在于：
对所述衬底结构进行刻蚀以形成第一接触孔的步骤以下列条件执行：
将C4F8、C4F6连同氧气和载流气体通入反应腔室，在10毫托至100毫托的压强下，在100w至2000w的功率下执行；
其中，所述C4F8的气体流量范围为10sccm至50sccm；
所述C4F6的气体流量范围为10sccm至50sccm；
所述氧气的气体流量范围为5sccm至30sccm；
所述载流气体的气体流量范围为50sccm至1000sccm。
4.如权利要求1所述的方法，其特征在于：
所述第一接触孔的深度为3－30nm，所述第一接触孔的宽度为30－40nm。
5.如权利要求1所述的方法，其特征在于：
所述低K氮化硅层的厚度为2－10nm，K值为3－5。
6.如权利要求1所述的方法，其特征在于：
在形成低k氮化硅层之后，以及形成第二接触孔之前，所述方法还包括：对所述低k氮化硅层进行表面刻蚀处理。
7.如权利要求6所述的方法，其特征在于：
所述表面刻蚀处理以下列条件执行：
将CH3F连同氧气通入反应腔室，在2毫托至30毫托的压强下，在100w至1000w的功率下执行；
其中，所述CH3F的气体流量范围为20sccm至200sccm；
所述氧气的气体流量范围为50sccm至200sccm。
8.如权利要求1所述的方法，其特征在于：
自对准地刻蚀以形成第二接触孔的步骤以下列条件执行：
将C4F8、C4F6连同氧气和载流气体通入反应腔室，在10毫托至100毫托的压强下，在100w至2000w的功率下执行；
其中，所述C4F8的气体流量范围为10sccm至50sccm；
所述C4F6的气体流量范围为10sccm至50sccm；
所述氧气的气体流量范围为5sccm至30sccm；
所述载流气体的气体流量范围为50sccm至1000sccm。
9.如权利要求1所述的方法，其特征在于：
所述栅极结构包括：
包绕所述鳍片的至少一部分的栅极电介质；
在所述栅极电介质上的金属栅极；
以及在所述金属栅极两侧的间隔物。
10.如权利要求1所述的方法，其特征在于：
所述第一接触孔的底部和顶部的截面尺寸相等；
所述第二接触孔的底部和顶部的截面尺寸相等。
11.如权利要求1所述的方法，其特征在于，还包括：
去除所述图案化的掩模。
12.如权利要求1所述的方法，其特征在于：
所述有源区包括源极和/或漏极。
13.一种半导体装置，其特征在于，包括：
半导体衬底；
位于所述半导体衬底上的一个或多个鳍片；
位于所述鳍片上的栅极结构；
位于所述鳍片上在所述栅极结构两侧的源极和漏极；
覆盖在所述源极和所述漏极上的层间电介质层；以及
在所述层间电介质层和所述栅极结构上的硬掩模层；
在所述源极或所述漏极上方穿过所述硬掩膜层并延伸到所述层间电介质层中的第一接触孔；
在所述第一接触孔的侧壁上的低k氮化硅层；
在所述第一接触孔的下方且延伸至所述源极或所述漏极的第二接触孔；以及
在所述第一接触孔和所述第二接触孔中接触所述源极或所述漏极的金属连接件。
14.如权利要求13所述的半导体装置，其特征在于：
所述栅极结构为高k金属栅极结构。
15.根据权利要求13所述半导体装置，其特征在于，
所述第一接触孔的深度为3－30nm，所述第一接触孔的宽度为30－40nm。
16.根据权利要求13所述半导体装置，其特征在于，
所述低k氮化硅层的厚度为2－10nm，k值为3－5。
17.如权利要求13所述的半导体装置，其特征在于：
所述第一接触孔的底部和顶部的截面尺寸相等；
所述第二接触孔的底部和顶部的截面尺寸相等。
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