CN108063114A - TSV pinboards based on transverse diode and preparation method thereof - Google Patents
TSV pinboards based on transverse diode and preparation method thereof Download PDFInfo
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- CN108063114A CN108063114A CN201711349175.3A CN201711349175A CN108063114A CN 108063114 A CN108063114 A CN 108063114A CN 201711349175 A CN201711349175 A CN 201711349175A CN 108063114 A CN108063114 A CN 108063114A
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- 238000000034 method Methods 0.000 claims abstract description 118
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- 229910052802 copper Inorganic materials 0.000 claims abstract description 24
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 21
- 238000005530 etching Methods 0.000 claims description 20
- 238000011049 filling Methods 0.000 claims description 20
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- 238000000708 deep reactive-ion etching Methods 0.000 claims description 6
- 238000000227 grinding Methods 0.000 claims description 6
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- 238000003701 mechanical milling Methods 0.000 claims description 5
- 238000011946 reduction process Methods 0.000 claims description 5
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- 238000001039 wet etching Methods 0.000 claims description 5
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- 238000000137 annealing Methods 0.000 claims description 4
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- 239000004020 conductor Substances 0.000 description 3
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
- H01L27/0262—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements including a PNP transistor and a NPN transistor, wherein each of said transistors has its base coupled to the collector of the other transistor, e.g. silicon controlled rectifier [SCR] devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Memories (AREA)
Abstract
The present invention relates to a kind of TSV pinboards based on transverse diode and preparation method thereof, and this method includes：Choose Si substrates；It etches the Si substrates and is respectively formed multiple TSV and multiple isolated grooves；It etches the Si substrates and multiple device trenches is formed between the isolated groove；It fills the isolated groove and the TSV is respectively formed isolated area and TSV areas；Transverse diode is prepared in the device trenches；Prepare the first end face in the TSV areas and the copper interconnecting line of the transverse diode；Second end face in the TSV areas prepares copper bump to complete the preparation of the TSV pinboards.TSV pinboards provided by the invention are used as ESD protection device by processing diode on TSV pinboards, solve the problems, such as that the IC system grade encapsulation antistatic effect based on TSV techniques is weak, enhance the antistatic effect of IC system grade encapsulation.
Description
Technical field
The invention belongs to semiconductor integrated circuit technology field, more particularly to a kind of TSV pinboards based on transverse diode
And preparation method thereof.
Background technology
One of target of semiconductor integrated circuit be with relatively low cost manufacture miniaturization, multi-functional, large capacity and/or
The semiconductor product of high reliability.Semiconductor packaging plays an important role in target as realization.With half
Integrated level and the memory capacity increase of conductor device have developed to stack three-dimensional (3D) encapsulation of one single chip.For example,
Employed be formed with the through hole for penetrating substrate and in through-holes formed electrode silicon hole (Through-Silicon Via,
Abbreviation TSV) contact technique as can replace existing Wire Bonding Technology a kind of 3D encapsulating structures.
TSV technology is a kind of new technical solution that stacked chips realize interconnection in 3D integrated circuits.Due to TSV skills
Art can make that the density that chip stacks in three-dimensional is maximum, the interconnection line between chip is most short, appearance and size is minimum, Ke Yiyou
This 3D chip laminates are realized on effect ground, produce that structure is more complicated, performance is more powerful, more cost-efficient chip, are become
Most noticeable a kind of technology in Electronic Encapsulating Technology at present.
Pinboard typically refers to the functional layer of the interconnection and pin redistribution between chip and package substrate.Pinboard can be with
Intensive I/O leads are redistributed, the high density interconnection of multi-chip is realized, it is grand with grade to become nanometer-grade IC
Electric signal connects one of most effective means between seeing the world.When realizing that multifunction chip is integrated using pinboard, not same core
The antistatic effect of piece is different, and the weak chip of antistatic effect influences whether the anti-quiet of whole system after encapsulation when three-dimensional stacked
Electric energy power, therefore it is urgently to be resolved hurrily as semicon industry how to improve the antistatic effect of the system in package based on TSV techniques
The problem of.
The content of the invention
In order to improve the antistatic effect of the system in package based on TSV techniques, the present invention provides one kind based on laterally
TSV pinboards of diode and preparation method thereof；The technical problem to be solved in the present invention is achieved through the following technical solutions：
The embodiment provides a kind of preparation method of the TSV pinboards based on transverse diode, including：
S101, Si substrates are chosen；
S102, etching Si substrates are respectively formed TSV holes and isolated groove；
S103, etching Si substrates form device trenches between isolated groove；
S104, filling isolated groove and TSV are respectively formed isolated area and TSV areas；
S105, transverse diode is prepared in device trenches；
S106, interconnection line is formed between the first end face in TSV areas and transverse diode；
S107, the second end face in TSV areas prepare metal salient point to complete the preparation of TSV pinboards.
In one embodiment of the invention, S102 includes：
S1021, using photoetching process, form the etched features of TSV and isolated groove in the upper surface of Si substrates；
S1022, using deep reaction ion etching method (Deep Reactive Ion Etching, abbreviation DRIE) technique,
It etches Si substrates and forms TSV and isolated groove；
Wherein, the depth of TSV and isolated groove is less than the thickness of Si substrates.
In one embodiment of the invention, S103 includes：
S1031, photoetching process, the etched features of the Si substrates formation device trenches between isolated groove are utilized；
S1032, dry etch process, etching Si substrate formation device trenches are utilized；
Wherein, the depth of device trenches is less than the depth of TSV and isolated groove.
In one embodiment of the invention, S104 includes：
S1041, thermal oxide TSV and isolated groove are in the inner wall of TSV and isolated groove formation oxide layer；
S1042, using wet-etching technology, etching oxidation layer is to complete the planarizing of TSV and isolated groove inner wall；
S1043, the filling figure that isolated groove is formed using photoetching process；
S1044, using chemical vapor deposition (Chemical Vapor Deposition, abbreviation CVD) technique, isolating
Filling SiO in groove2Form isolated area；
S1045, the filling figure that TSV is formed using photoetching process；
S1046, using CVD techniques, polysilicon is filled in TSV, and is passed through impurity gas and carries out doping in situ and form TSV
Area.
In one embodiment of the invention, S105 includes：
S1051, the filling figure that device trenches are formed using photoetching process；
S1052, using CVD techniques, fill polycrystalline silicon material in device trenches；
S1053, photoetching P+Active area carries out P using band glue ion implantation technology+Injection removes photoresist, is formed laterally
The anode of diode；
S1054, photoetching N+Active area carries out N using band glue ion implantation technology+Injection removes photoresist, is formed laterally
The cathode of diode；
S1055, high annealing, activator impurity are carried out.
In one embodiment of the invention, further included before S107：
X1, by the use of aiding in supporting item of the disk as Si substrate top surfaces；
X2, Si substrates lower surface is thinned using mechanical grinding reduction process, recycles chemically mechanical polishing
(Chemical Mechanical Polishing, abbreviation CMP) technique carries out planarizing process, directly to the lower surface of Si substrates
To the second end face for exposing TSV areas.
In one embodiment of the invention, S107 includes：
S1071, using sputtering technology, form laying and barrier layer in the lower surface of Si substrates, existed using CVD techniques
The second end face in TSV areas forms tungsten plug；
S1072, deposition insulating layer in the figure of the second end face photolithographic salient point in TSV areas, utilize electrochemical plating coppersmith
Skill deposits metal, and extra metal is removed by chemical mechanical milling tech, and the second end face in TSV areas forms metal salient point；
S1073, auxiliary disk is removed.
In one embodiment of the invention, the doping concentration of Si substrates is 1014~1017cm-3, thickness is 150~250 μ
m。
In one embodiment of the invention, the depth of TSV areas and isolated area is 40~80 μm.
Compared with prior art, the invention has the advantages that：
1st, TSV pinboards provided by the invention on TSV pinboards by processing static discharge (Electro-Static
Discharge, abbreviation ESD) protective device diode, enhance the antistatic effect of laminate packaging chip；
2nd, the present invention, using the higher heat-sinking capability of pinboard, improves device by processing diode on TSV pinboards
High current handling capacity in part work；
3rd, the isolated groove of up/down perforation is utilized around the diode of TSV pinboards provided by the invention, is had smaller
Leakage current and parasitic capacitance；
4th, the preparation method of the TSV pinboards provided by the invention based on transverse diode can be in existing TSV techniques
It is realized in platform, therefore compatibility is strong, it is applied widely.
Description of the drawings
In order to illustrate the technical solution of the embodiments of the present invention more clearly, required use in being described below to embodiment
Attached drawing be briefly described, it should be apparent that, the accompanying drawings in the following description is only some embodiments of the present invention, for this
For the those of ordinary skill of field, without creative efforts, others are can also be obtained according to these attached drawings
Attached drawing.
Through the following detailed description with reference to the accompanying drawings, other aspects of the invention and feature become apparent.But it should know
Road, which is only the purpose design explained, not as the restriction of the scope of the present invention, this is because it should refer to
Appended claims.It should also be noted that unless otherwise noted, it is not necessary to which scale attached drawing, they only try hard to concept
Ground illustrates structure and flow described herein.
Fig. 1 shows for a kind of preparation method flow of the TSV pinboards based on transverse diode provided in an embodiment of the present invention
It is intended to；
Fig. 2 is the preparation method flow of another TSV pinboards based on transverse diode provided in an embodiment of the present invention
Figure；
Fig. 3 a- Fig. 3 i are the preparation side of another TSV pinboard based on transverse diode provided in an embodiment of the present invention
Method flow chart；
Fig. 4 is a kind of TSV adapter plate structures schematic diagram provided in an embodiment of the present invention.
Specific embodiment
Further detailed description is done to the present invention with reference to specific embodiment, but embodiments of the present invention are not limited to
This.
Embodiment one
Fig. 1 is referred to, Fig. 1 is a kind of preparation of the TSV pinboards based on transverse diode provided in an embodiment of the present invention
Method flow schematic diagram, including：
S101, Si substrates are chosen；
S102, etching Si substrates are respectively formed TSV holes and isolated groove；
S103, etching Si substrates form device trenches between isolated groove；
S104, filling isolated groove and TSV are respectively formed isolated area and TSV areas；
S105, transverse diode is prepared in device trenches；
S106, interconnection line is formed between the first end face in TSV areas and transverse diode；
S107, the second end face in TSV areas prepare metal salient point to complete the preparation of TSV pinboards.
Preferably, S102 can include：
S1021, using photoetching process, form the etched features of TSV and isolated groove in the upper surface of Si substrates；
S1022, DRIE techniques, etching Si substrates formation TSV and isolated groove are utilized；
Wherein, the depth of TSV and isolated groove is less than the thickness of Si substrates.
Preferably, S103 can include：
S1031, photoetching process, the etched features of the Si substrates formation device trenches between isolated groove are utilized；
S1032, dry etch process, etching Si substrate formation device trenches are utilized；
Wherein, the depth of device trenches is less than the depth of TSV and isolated groove.
Preferably, S104 can include：
S1041, thermal oxide TSV and isolated groove are in the inner wall of TSV and isolated groove formation oxide layer；
S1042, using wet-etching technology, etching oxidation layer is to complete the planarizing of TSV and isolated groove inner wall；
S1043, the filling figure that isolated groove is formed using photoetching process；
S1044, using CVD techniques, SiO is filled in isolated groove2Form isolated area；
S1045, the filling figure that TSV is formed using photoetching process；
S1046, using CVD techniques, polysilicon is filled in TSV, and is passed through impurity gas and carries out doping in situ and form TSV
Area.
Preferably, S105 can include：
S1051, the filling figure that device trenches are formed using photoetching process；
S1052, using CVD techniques, fill polycrystalline silicon material in device trenches；
S1053, photoetching P+Active area carries out P using band glue ion implantation technology+Injection removes photoresist, is formed laterally
The anode of diode；
S1054, photoetching N+Active area carries out N using band glue ion implantation technology+Injection removes photoresist, is formed laterally
The cathode of diode；
S1055, high annealing, activator impurity are carried out.
Preferably, further included before S107：
X1, by the use of aiding in supporting item of the disk as Si substrate top surfaces；
X2, Si substrates lower surface is thinned using mechanical grinding reduction process, CMP process is recycled, to Si substrates
Lower surface carry out planarizing process, the second end face until exposing TSV areas.
Preferably, S107 can include：
S1071, using sputtering technology, form laying and barrier layer in the lower surface of Si substrates, existed using CVD techniques
The second end face in TSV areas forms tungsten plug；
S1072, deposition insulating layer in the figure of the second end face photolithographic salient point in TSV areas, utilize electrochemical plating coppersmith
Skill deposits metal, and extra metal is removed by chemical mechanical milling tech, and the second end face in TSV areas forms metal salient point；
S1073, auxiliary disk is removed.
Preferably, the doping concentration of Si substrates is 1014~1017cm-3, thickness is 150~250 μm.
Preferably, the depth of TSV areas and isolated area is 40~80 μm.
The preparation method of TSV pinboards provided in this embodiment by the cross machine diode on TSV pinboards, increases
The strong antistatic effect of laminate packaging chip, after the weak chip of antistatic effect influences whether encapsulation when solving three-dimensional stacked
The problem of antistatic effect of whole system；Meanwhile it is provided with around the diode the present embodiment provides TSV pinboards and passes through up and down
Logical isolated area has smaller leakage current and parasitic capacitance.
Embodiment two
Fig. 2 is refer to, Fig. 2 is the system of another TSV pinboards based on transverse diode provided in an embodiment of the present invention
Preparation Method flow chart, the present embodiment is on the basis of above-described embodiment, to the TSV pinboards based on transverse diode of the present invention
Preparation method be described in detail it is as follows.Specifically, include the following steps：
S201, Si substrates are chosen；
S202, multiple TSV and multiple isolated grooves are prepared on a si substrate using etching technics；
S203, multiple device trenches are prepared on a si substrate using etching technics；
S204, using CVD techniques, deposit SiO on a si substrate2Isolated groove is filled to form isolated area；
S205, using CVD techniques, depositing polysilicon material is filled TSV to form TSV areas on a si substrate；
S206, using CVD techniques, depositing polysilicon material is filled device trenches on a si substrate, and prepares horizontal stroke
To the diode of structure；
S207, using electroplating technology, surface prepares copper interconnecting line on a si substrate；
S208, using CMP process, Si substrates are thinned, until leaking out TSV；
S209, in Si substrates lower surface electric plating method is utilized to form copper bump to complete the preparation of TSV pinboards.
Wherein, choose Si substrates the reason for be, the thermodynamic property of Si is identical with chip, by the use of Si materials as transfer
Plate can reduce the bending of chip and die stress caused by the difference and residual stress of coefficient of thermal expansion to the full extent.
The crystal orientation of Si substrates can be (100), (110) or (111), in addition, the doping type of substrate can be N-type, or P
Type.
Preferably, S202 may include steps of：
S2021, TSV and isolated groove figure are etched using photoetching process；
S2022, DRIE techniques, etching Si substrates formation TSV and isolated groove are utilized.
Wherein, the quantity of TSV is one or more, and the depth of TSV is less than the thickness of Si substrates；The quantity of isolated groove is
Multiple, the depth of isolated groove is less than Si substrate thickness；
Preferably, the depth of TSV is equal to the depth of isolated groove.
Preferably, S103 can include：
S2031, using photoetching process, form the etched features of device trenches in Si substrates；
S2032, dry etch process, etching Si substrate formation device trenches are utilized；
Wherein, for device trenches between isolated groove, the depth of device trenches is less than the depth of TSV and isolated groove.
Further, S204 may include steps of：
S2041, thermal oxide TSV and isolated groove make the inner wall of blind hole form oxide layer；
S2042, the oxide layer of TSV and isolated groove inner wall is etched using wet-etching technology to complete the flat of blind hole inner wall
Integralization.
Wherein, the protrusion that can prevent blind hole side wall by the planarizing of blind hole inner wall forms electric field concentrated area.
S2043, using photoetching process, pass through the techniques such as gluing, photoetching, development and complete isolated groove and fill figure；
S2044, CVD techniques, deposit SiO are utilized2Isolated groove is filled to form isolated area.
Wherein, isolated area run through entire pinboard, effectively device can be isolated with substrate, reduce active area and
Parasitic capacitance between substrate.
Preferably, S205 may include steps of：
S2051, using photoetching process, pass through the techniques such as gluing, photoetching, development and complete TSV and fill figure
S2052, using CVD techniques, depositing polysilicon material is filled TSV, at the same be passed through impurity gas carry out it is former
Position doping realizes the activation in situ of doped chemical, forms highly doped polysilicon TSV areas.
Wherein, filled by carrying out highly doped polysilicon in TSV areas, it is uniformly and highly doped that Impurity Distribution can be formed
The conductive material of concentration is conducive to reduce the resistance of TSV.
Preferably, S206 may include steps of：
S2061, the filling figure that device trenches are formed using photoetching process；
S2062, using CVD techniques, fill polycrystalline silicon material in device trenches；
S2063, photoetching P+Active area carries out P using band glue ion implantation technology+Injection removes photoresist, is formed laterally
The anode of diode；
S2064, photoetching N+Active area carries out N using band glue ion implantation technology+Injection removes photoresist, is formed laterally
The cathode of diode；
S2065, high annealing, activator impurity are carried out.
Preferably, S207 may include steps of：
S2071, sputtering or CVD techniques, on a si substrate surface formation laying and barrier layer, and utilize CVD works are utilized
The first end in Yi TSV areas and the anode and cathode of diode form tungsten plug；
S2072, deposition insulating layer, photoetching copper-connection figure deposit copper using electrochemical plating process for copper, pass through chemical machinery
Grinding technics removes extra copper, forms the copper interconnecting line that the first end in TSV areas is concatenated with diode.
Further, when preparing copper interconnecting line, surround spiral using metal interconnecting wires and make it have inductance
Characteristic to be more particularly for the electrostatic protection of RF IC.
Preferably, S208 may include steps of：
S2081, by the use of high molecular material as interlayer, by Si substrate top surfaces and auxiliary wafer bonding, pass through auxiliary
Disk supports Si substrate top surfaces；
S2082, Si substrates lower surface is thinned using mechanical grinding reduction process, is slightly larger than TSV depths until reducing to
The thickness of degree；
S2083, smooth, the second end until exposing TSV areas is carried out to Si substrates lower surface using CMP process.
Preferably, S209 may include steps of：
S2091, laying and barrier layer are formed in Si substrates lower surface using sputtering or CVD techniques, is existed using CVD techniques
The second end in TSV areas forms tungsten plug；
S2092, deposition insulating layer, the second end photoetching copper bump figure in TSV areas are deposited using electrochemical plating process for copper
Copper removes extra copper by chemical mechanical milling tech, and the second end in TSV areas forms copper bump.
S2093, the auxiliary disk being bonded temporarily using the technique dismounting of heated mechanical.
The preparation method of TSV pinboards provided in this embodiment, it is mutually compatible with typical CMOS technology, be conducive to industry
Change；Using the diode component of transversary, parasitic capacitance is small, RF IC is influenced small.
Embodiment three
The present embodiment is on the basis of above-described embodiment, to the system of the TSV pinboards based on transverse diode of the present invention
Design parameter citing is described as follows in Preparation Method.Specifically, Fig. 3 a- Fig. 3 i, Fig. 3 a- Fig. 3 i are refer to carry for the embodiment of the present invention
The preparation method flow chart of another the TSV pinboard based on transverse diode supplied,
S301, Si substrates 301 are chosen, as shown in Figure 3a；
Preferably, the doping concentration of Si substrates is 1014~1017cm-3, thickness is 150~250 μm.
S302, as shown in Figure 3b；Prepare two TSV302 and three isolated grooves on a si substrate using etching technics
303, it may include steps of：
S3021, at a temperature of 1050 DEG C~1100 DEG C, utilize thermal oxidation technology on a si substrate surface grow one layer
The SiO of 800nm~1000nm2Layer；
S3022, using photoetching process, pass through the techniques such as gluing, photoetching, development and complete TSV and isolated groove etched features；
S3023, Si substrates are etched using DRIE techniques, forms the TSV and isolated groove of 40~80 μm of depths；
S3024, using CMP process, remove the SiO on Si substrates2, substrate surface is planarized.
S303, as shown in Figure 3c；It prepares two device trenches 304 on a si substrate using etching technics, can specifically wrap
Include following steps：
S3031, CVD techniques deposit silicon nitride layer on a si substrate is utilized；
S3032, using photoetching process, pass through the techniques such as gluing, photoetching, development and complete device trenches etched features；
S3033, device trenches are formed using dry etch process, etch nitride silicon layer and Si substrates；The depth of device trenches
It spends for 15~25 μm；
S3034, using CMP process, remove the silicon nitride layer on Si substrates, substrate surface planarized.
S304, as shown in Figure 3d；Using CVD techniques, SiO is deposited on a si substrate2Shape is filled to isolated groove 303
Into isolated area, specifically may include steps of：
S3041, at a temperature of 1050 DEG C~1100 DEG C, the inner wall of thermal oxide TSV, isolated groove and device trenches are formed
Thickness is the oxide layer of 200nm~300nm；
S3042, using wet-etching technology, the oxide layer of the inner wall of etching TSV, isolated groove and device trenches is to complete
The planarizing of TSV and isolated groove inner wall.To prevent the protrusion of TSV, isolated groove and device trenches side wall form electric field from concentrating
Region；
S3043, using photoetching process, pass through the techniques such as gluing, photoetching, development and complete isolated groove and fill figure；
S3044, at a temperature of 690 DEG C~710 DEG C, utilize low-pressure chemical vapor deposition (Low Pressure
Chemical Vapor Deposition, LPCVD) technique, deposit SiO2Isolated groove is filled, forms isolated area；It can
With understanding, the SiO2Material is mainly used for isolating, and can be substituted by other materials such as undoped polycrystalline silicons.
S3045, using CMP process, substrate surface is planarized.
S305, as shown in Figure 3 e；Using CVD techniques, depositing polysilicon material is filled TSV302 on a si substrate,
Impurity gas is passed through simultaneously, TSV areas are formed to polysilicon progress doping in situ, specifically may include steps of：
S3051, using photoetching process, pass through the techniques such as gluing, photoetching, development and complete TSV and fill figure；
S3052, at a temperature of 600 DEG C~620 DEG C, TSV is filled using CVD technique depositing polysilicon materials,
Impurity gas is passed through simultaneously and carries out doping in situ, and realizes the activation in situ of doped chemical, forms highly doped polysilicon filling.
Impurity Distribution can be so formed when being filled to TSV uniformly and the conductive material of high-dopant concentration is filled, beneficial to reduction TSV
Resistance.Polysilicon doping concentration preferably 2 × 1021cm-3, the preferred phosphorus of impurity；
S3054, substrate surface is planarized using CMP process.
S306, as illustrated in figure 3f；Using CVD techniques, depositing polysilicon material carries out device trenches 304 on a si substrate
Filling, and the anode 305 of diode and cathode 306 are formed using ion implantation technology, the diode of transversary is formed, specifically
It may include steps of：
S3061, using photoetching process, between two adjacent isolated areas, pass through the techniques shape such as gluing, photoetching, development
Into the filling figure of device trenches.
S3062, using LPCVD techniques, at a temperature of 600 DEG C~950 DEG C, selective epitaxial growth polysilicon, simultaneously
It is passed through impurity gas and carries out doping in situ, and realize the activation in situ of doped chemical, form N-The polysilicon filling of doping.Doping
Concentration is 5 × 1014cm-3, the preferred phosphorus of impurity.
S3063, using CMP process, substrate surface is planarized.
S3064, photoetching P+Active area carries out P using band glue ion implantation technology+Injection removes photoresist, forms two poles
The anode of pipe.Doping concentration is 5 × 1018cm-3, impurity is boron.
S3065, photoetching N+Active area carries out N using band glue ion implantation technology+Injection removes photoresist, forms two poles
The cathode of pipe.Doping concentration preferably 5 × 1018cm-3, the preferred phosphorus of impurity.
S3066, by substrate at a temperature of 950~1100 DEG C, anneal 15~120s, carry out impurity activation.
S307, as shown in figure 3g；Using electroplating technology, surface forms copper interconnecting line 307 on a si substrate, can specifically wrap
Include following steps：
S3071, plasma enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapor are utilized
Deposition, PECVD) technique, deposit SiO in substrate surface2Layer；
S3072, in the first end in TSV areas and the anode of diode and cathode, using photoetching process, pass through gluing, light
The techniques such as quarter, development complete contact hole graph；
S3073, using CVD techniques, in the first end in TSV areas and the anode of diode and cathode deposition Ti films, TiN film
With tungsten to form tungsten plug；
S3074, substrate surface is planarized using CMP process.
S3075, deposit SiO2Insulating layer, photoetching copper-connection figure deposit copper, passing through using the method for Cu electroplating
The method for learning mechanical lapping removes extra copper, and the first end for forming TSV areas concatenates copper interconnecting line with diode；
S3076, substrate surface is planarized using CMP process.
S3077, using pecvd process, deposit SiO in substrate surface2Layer；
S308, as illustrated in figure 3h；Si substrates are thinned using CMP process, TSV areas is leaked out, specifically may be used
To include the following steps：
S3081, by the use of high molecular material as interlayer, by Si substrate top surfaces and auxiliary wafer bonding, pass through auxiliary
Being thinned for Si substrates is completed in the support of disk；
S3082, Si substrates lower surface is thinned using mechanical grinding reduction process, is slightly larger than TSV areas until reducing to
The thickness of depth, preferably greater than 10 μm of TSV depth；
S3083, Si substrates lower surface is carried out using CMP process it is smooth, until exposing TSV areas；
S309, as shown in figure 3i；Copper bump 308 is formed using electric plating method in Si substrates lower surface, can specifically be wrapped
Include following steps：
S3091, using pecvd process, deposit SiO in substrate lower surface2Layer；
Using photoetching process, contact hole is completed by techniques such as gluing, photoetching, developments for S3092, the second end in TSV areas
Figure；
S3093, using CVD techniques, in second end face deposit Ti films, TiN film and the tungsten in TSV areas to form tungsten plug；
S3094, substrate surface is planarized using CMP process；
S3095, deposit SiO2Insulating layer, the second end photoetching copper bump figure in TSV areas, utilizes electrochemical plating process for copper
Copper is deposited, extra copper is removed by chemical mechanical milling tech, etches SiO2Layer, the second end in TSV areas form copper bump；
S3096, the auxiliary disk being bonded temporarily using the method dismounting of heated mechanical.
The preparation method of TSV pinboards provided in this embodiment, using diode component periphery by SiO2Insulating layer surrounds
Technique, the parasitic capacitance between active area and substrate can be effectively reduced.The present invention passes through on the basis of technological feasibility is considered
The TSV holes of optimal design-aside certain length and the doping concentration using given range, and consider the electric current handling capacity of device, subtract
Small parasitic capacitance and resistance, and a degree of tuning is carried out to the parasitic capacitance of device using the inductance that TSV holes introduce,
The working range of esd protection circuit is expanded while improving system in package anti-ESD abilities.
Example IV
Fig. 4 is refer to, Fig. 4 shows for a kind of TSV adapter plate structures based on transverse diode provided in an embodiment of the present invention
It is intended to；The TSV pinboards are made using the above-mentioned preparation process as shown in Fig. 3 a- Fig. 3 i.
Specifically, TSV pinboards include：Si substrates 40, horizontal the first TSV areas 401 being set in turn in Si substrates, the
One isolated area 402, the first transverse diode 403, the second isolated area 404, the second transverse diode 405, the 3rd isolated area 406 with
And the 2nd TSV areas 407.
Further, the first TSV areas 401, the first isolated area 402, the second isolated area 404, the 3rd isolated area 406 and
Two TSV areas, the 407 equal entire Si substrates of up/down perforation.
Preferably, the material of 407 interior filling of the first TSV areas 401 and the 2nd TSV areas is polysilicon；First isolated area 402,
The material of filling is SiO in second isolated area 404 and the 3rd isolated area 4062。
Wherein, the first TSV areas 401, the first transverse diode 403, the second transverse diode 405 and the 2nd TSV areas 407
It is connected in series successively；
Specifically, the first end in the first TSV areas 401 and anode, the first transverse diode of the first transverse diode 403
The anode of 403 cathode and the second transverse diode 405, the of the cathode of the second transverse diode 405 and the 2nd TSV areas 407
One end is connected respectively by copper interconnecting line 408.
Wherein, the first end in the first TSV areas 401, the anode of the first transverse diode 403, first transverse diode 403
Cathode, the anode of the second transverse diode 405, the cathode of the second transverse diode 405, the 2nd TSV areas 407 first end on according to
It is secondary to be provided with tungsten plug and copper interconnecting line；It is set gradually in the second end in the first TSV areas 401 and the second end in the 2nd TSV areas 407
There are tungsten plug and copper bump 409.
Further, TSV pinboards further include the SiO for being arranged at Si substrate top surfaces and lower surface2Insulating layer.
Specifically, the first isolated area 402, the second isolated area 404 and the 3rd isolated area 406 and Si substrate top surfaces and following table
The SiO in face2Insulating layer is used to form the area of isolation of closing to isolate the first transverse diode 403 and the second transverse diode
405。
TSV pinboards provided in this embodiment, it is simple in structure, very big ESD electric currents can be born and be unlikely to make partly to lead
Body device heating fails；Using the higher heat-sinking capability of pinboard, the high current handling capacity in device work is improved；Together
When, the isolated groove of up/down perforation around the diode of TSV pinboards is set, there is smaller leakage current and parasitic capacitance.
The above content is a further detailed description of the present invention in conjunction with specific preferred embodiments, it is impossible to assert
The specific implementation of the present invention is confined to these explanations.For example, the multiple isolated areas referred in the present invention are only according to this hair
The device architecture sectional view of bright offer illustrates, wherein, multiple isolated areas can also be such as ring bodies in some entirety
The first portion that shows of sectional view and second portion, for those of ordinary skill in the art to which the present invention belongs, no
These explanations should be confined to, without departing from the inventive concept of the premise, several simple deduction or replace can also be made, all should
When being considered as belonging to protection scope of the present invention.
Claims (10)
1. a kind of preparation method of the TSV pinboards based on transverse diode, which is characterized in that including：
S101, Si substrates are chosen；
S102, the etching Si substrates are respectively formed TSV holes and isolated groove；
S103, the etching Si substrates form device trenches between the isolated groove；
S104, the filling isolated groove and the TSV are respectively formed isolated area and TSV areas；
S105, transverse diode is prepared in the device trenches；
S106, interconnection line is formed between the first end face in the TSV areas and the transverse diode；
S107, the second end face in the TSV areas prepare metal salient point to complete the preparation of the TSV pinboards.
2. preparation method according to claim 1, which is characterized in that S102 includes：
S1021, using photoetching process, form the etching figure of the TSV and the isolated groove in the upper surface of the Si substrates
Shape；
S1022, using DRIE techniques, etch the Si substrates and form the TSV and the isolated groove；The TSV and described
The depth of isolated groove is less than the thickness of the Si substrates.
3. preparation method according to claim 2, which is characterized in that S103 includes：
S1031, using photoetching process, the Si substrates between the isolated groove form the etching figure of the device trenches
Shape；
S1032, using dry etch process, etch the Si substrates and form the device trenches；
Wherein, the depth of the device trenches is less than the depth of the TSV and the isolated groove.
4. preparation method according to claim 3, which is characterized in that S104 includes：
TSV described in S1041, thermal oxide and the isolated groove are aoxidized with being formed in the inner wall of the TSV and the isolated groove
Layer；
S1042, using wet-etching technology, etch the oxide layer to complete the flat of the TSV and the isolated groove inner wall
Integralization；
S1043, the filling figure that the isolated groove is formed using photoetching process；
S1044, using CVD techniques, fill SiO in the isolated groove2Form the isolated area；
S1045, the filling figure that the TSV is formed using photoetching process；
S1046, using CVD techniques, polysilicon is filled in the TSV, and is passed through impurity gas and carries out doping in situ and form institute
State TSV areas.
5. preparation method according to claim 4, which is characterized in that S105 includes：
S1051, the filling figure that the device trenches are formed using photoetching process；
S1052, using CVD techniques, fill polycrystalline silicon material in the device trenches；
S1053, photoetching P+Active area carries out P using band glue ion implantation technology+Injection removes photoresist, forms laterally two poles
The anode of pipe；
S1054, photoetching N+Active area carries out N using band glue ion implantation technology+Injection removes photoresist, forms laterally two poles
The cathode of pipe；
S1055, high annealing, activator impurity are carried out.
6. preparation method according to claim 1, which is characterized in that further included before S107：
X1, by the use of aiding in supporting item of the disk as the Si substrate top surfaces；
X2, the Si substrates lower surface is thinned using mechanical grinding reduction process, CMP process is recycled, to the Si
The lower surface of substrate carries out planarizing process, the second end face until exposing the TSV areas.
7. preparation method according to claim 6, which is characterized in that S107 includes：
S1071, sputtering technology, formation laying and barrier layer in the lower surface of the Si substrates, using CVD techniques in institute are utilized
The second end face for stating TSV areas forms tungsten plug；
S1072, deposition insulating layer, the figure of metal salient point, utilizes electrochemical plating described in the second end face photoetching in the TSV areas
Process for copper deposits metal, and extra metal is removed by chemical mechanical milling tech, and the second end face in the TSV areas forms institute
State metal salient point；
S1073, the auxiliary disk is removed.
8. preparation method according to claim 1, which is characterized in that the doping concentration of the Si substrates is 1014~
1017cm-3, thickness is 150~250 μm.
9. preparation method according to claim 8, which is characterized in that the depth of the TSV areas and the isolated area is 40
~80 μm.
10. a kind of TSV pinboards based on transverse diode, which is characterized in that the TSV pinboards are by claim 1~9 times
Method described in one prepares to be formed.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120329277A1 (en) * | 2009-03-05 | 2012-12-27 | International Business Machines Corporation | Two-sided semiconductor structure |
| CN104103655A (en) * | 2013-04-01 | 2014-10-15 | 全视科技有限公司 | Enhanced photon detection device with biased deep trench isolation |
| CN105190888A (en) * | 2013-05-06 | 2015-12-23 | 高通股份有限公司 | Electrostatic discharge diode |
| CN106170853A (en) * | 2014-02-28 | 2016-11-30 | 勒丰德里有限公司 | Manufacture method and the semiconductor product of semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120329277A1 (en) * | 2009-03-05 | 2012-12-27 | International Business Machines Corporation | Two-sided semiconductor structure |
| CN104103655A (en) * | 2013-04-01 | 2014-10-15 | 全视科技有限公司 | Enhanced photon detection device with biased deep trench isolation |
| CN105190888A (en) * | 2013-05-06 | 2015-12-23 | 高通股份有限公司 | Electrostatic discharge diode |
| CN106170853A (en) * | 2014-02-28 | 2016-11-30 | 勒丰德里有限公司 | Manufacture method and the semiconductor product of semiconductor device |
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