CN108022488B - Four-dimensional coupling power generation hyperchaotic system analog circuit - Google Patents
Four-dimensional coupling power generation hyperchaotic system analog circuit Download PDFInfo
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Abstract
A four-dimensional coupling power generation hyperchaotic system analog circuit comprises an output end of a first channel, a second channel and an input pin, wherein the output end of the first channel is connected with the input end of the first channel, the first input end of the second channel and the input pin of a multiplier A1 in a third channel; the output end of the previous stage of the output end of the first channel is connected with the first input pin of the multiplier A2 in the second channel; the output end of the second channel is connected with the second input end of the second channel and the input end of the fourth channel; the previous stage output end of the second channel output end is connected with the second input end of the first channel, the first input pin of the multiplier A3 in the first channel and the second input pin of the multiplier A1 in the third channel; the output end of the previous stage of the output end of the third channel is connected with the second input pin of the multiplier A3 in the first channel, the second input pin of the multiplier A2 in the second channel and the input end of the third channel; the previous stage output end of the fourth channel is connected with the third input end of the first channel; the invention has the advantages of simple circuit structure and easy realization.
Description
Technical Field
The invention relates to the technical field of nonlinear signal generator device design, in particular to a four-dimensional coupling power generation hyperchaotic system analog circuit.
Background
The chaotic system has wide application in circuits, communication, information science, engineering technology, medicine and the like, and is also generally accepted by people. The polarity reversal in the long-term variation of the geomagnetic field is one of the most difficult problems to explain in the theory of geomagnetism, and many models have been proposed by the geomagnetism to describe the phenomenon, wherein the coupled generator model is the earliest and most classical model. However, with the knowledge of people to the nature, the complexity of the geomagnetic model is found to be a high-dimensional system, and based on the high-dimensional system, a system with higher dimensions, namely a four-dimensional coupling power generation hyperchaotic system, is proposed by people on the basis of three dimensions.
At present, the realization of a chaotic system, namely the realization of a chaotic circuit, designs a four-dimensional coupling generator hyper-chaotic system circuit, and has important application value for recognizing and analyzing magnetic polarity reversal. The invention aims to solve the problems that the high-dimensional geomagnetic coupling power generation system is not easy to realize by using a circuit, the circuit is not reliable and the like in the prior art.
Disclosure of Invention
The invention aims to provide a four-dimensional coupling power generation hyperchaotic system analog circuit, which has strong chaotic characteristics and the like.
In order to achieve the purpose, the invention adopts the technical scheme that:
a four-dimensional coupling power generation hyperchaotic system analog circuit comprises a first channel, a second channel, a third channel and a fourth channel;
the output end of the first channel is connected with the first input end of the first channel, the first input end of the second channel and the first input pin of the multiplier A1 in the third channel; the output end of the previous stage of the output end of the first channel is connected with the first input pin of the multiplier A2 in the second channel;
the output end of the second channel is connected with the second input end of the second channel and the input end of the fourth channel; the previous stage output end of the second channel output end is connected with the second input end of the first channel, the first input pin of the multiplier A3 in the first channel and the second input pin of the multiplier A1 in the third channel;
the output end of the previous stage of the output end of the third channel is connected with the second input pin of the multiplier A3 in the first channel, the second input pin of the multiplier A2 in the second channel and the input end of the third channel;
and the previous stage output end of the fourth channel is connected with the third input end of the first channel.
The first channel comprises an inverter U1, a pin 2 of the inverter U1 is connected with one ends of a resistor R11, a resistor R12, a resistor R13, a resistor R14 and a resistor R17, the other end of the resistor R11 is connected with the output end of a multiplier A3, the other end of the resistor R12 is connected with the output end of the first channel, a resistor R13 is connected with the previous-stage output end of the second channel output end, the other end of the resistor R14 is connected with the previous-stage output end of the fourth channel output end, the other end of a resistor R17 is connected with a pin 6 of an inverter U1 and one end of a resistor R18, the other end of a resistor R18 is connected with a pin 2 of an inverse integrator U3 and one end of a capacitor C1, the other end of a capacitor C1 is connected with a pin 6 of an inverse integrator U3 and one end of a resistor R19, the other end of a resistor R19 is connected with a pin 2 of the inverter U19; the 4-pin of the inverter U1, the 4-pin of the inverter U2, and the 4-pin of the inverting integrator U3 are connected to VDD (negative voltage), and the 7-pin of the inverter U1, the 7-pin of the inverter U2, and the 7-pin of the inverting integrator U3 are connected to VCC (positive voltage).
The output of the inverter U2 of the first channel is signal-x, and the output of the inverting integrator U3 is signal x.
The second channel comprises an inverter U4, a pin 2 of the inverter U4 is connected with one end of a resistor R21, a resistor R22, a resistor R23 and one end of a resistor R24, the other end of the resistor R21 is connected with the output end of a multiplier A2, the other end of the resistor R22 is connected with the output end of the first channel, the other end of a resistor R23 is connected with the output end of the second channel, the other end of a resistor R24 is connected with a pin 6 of the inverter U4 and one end of a resistor R25, the other end of a resistor R25 is connected with a pin 2 of an inverse integrator U6 and one end of a capacitor C2, the other end of the capacitor C2 is connected with a pin 6 of the inverse integrator U5968642 and one end of a resistor R5968628, the other end of a resistor R9 is connected with a pin 2 of the inverter U5 and one end of a resistor R; the 3 pin of the inverting amplifier U4, the 3 pin of the inverting amplifier U5 and the 3 pin of the inverting integrator U6 are grounded; the 4 pins of the inverter U4, the 4 pins of the inverter U5 and the 4 pins of the inverse integrator U6 are connected with VDD (negative voltage), and the 7 pins of the inverter U4, the 7 pins of the inverter U5 and the 7 pins of the inverse integrator U6 are connected with VCC (positive voltage);
the signal at the output of the second channel inverter U5 is-y, and the signal at the output of the second channel inverting integrator U6 is y.
The third channel comprises an inverter U7, a2 script of the inverter U7 is connected with one ends of a resistor R31, a resistor R32 and a resistor R34, the other end of the resistor R31 is connected with the output end of a multiplier A1, the other end of a resistor R32 is connected with the previous-stage output end of the third channel, the other end of a resistor R34 is connected with the 6 pin of the inverter U7 and one end of a resistor R35, the other end of a resistor R35 is connected with one end of a capacitor C3 and the pin 2 of the inverse integrator U9, the other end of a capacitor C3 is connected with the 6 pin of the inverse integrator U9 and one end of a resistor R36, the other end of a resistor R36 is connected with one end of the resistor R38 and the 2 pin of the inverter U573; the 3 pin of the inverting amplifier U7, the 3 pin of the inverting amplifier U8 and the 3 pin of the inverting integrator U9 are grounded; the 4-pin of the inverter U7, the 4-pin of the inverter U8, and the 4-pin of the inverting integrator U9 are connected to VDD (negative voltage), and the 7-pin of the inverter U7, the 7-pin of the inverter U8, and the 7-pin of the inverting integrator U9 are connected to VCC (positive voltage).
The output end signal of the third channel inverter U8 is-z, and the output end of the third channel inverting integrator U9 is the signal z.
The fourth channel comprises an inverter U10, a2 script of the inverter U10 is connected with one ends of a resistor R41 and a resistor R43, the other end of the resistor R41 is connected with the output end of the second channel, the other end of a resistor R43 is connected with a pin 6 of the inverter U10 and one end of a resistor R44, the other end of the resistor R44 is connected with one end of a capacitor C4 and a pin 2 of an inverse integrator U12, the other end of the capacitor C4 is connected with a pin 6 of the inverse integrator U12 and one end of a resistor R45, the other end of the resistor R45 is connected with one end of a resistor R47 and a pin 2 of the inverter U11, and the other end of the resistor R47 is connected with a pin 6 of the; the 3 pin of the inverter U10, the 3 pin of the inverter U11 and the 3 pin of the inverse integrator U12 are grounded; the 4-pin of the inverter U10, the 4-pin of the inverter U11, and the 4-pin of the inverting integrator U12 are connected to VDD (negative voltage), and the 7-pin of the inverter U10, the 7-pin of the inverter U11, and the 7-pin of the inverter integration U12 are connected to VCC (positive voltage).
The output end signal of the fourth channel inverter U11 is-w, and the output end of the fourth channel inverting integrator U12 is the signal w.
The inverter U1, the inverter U2, the inverse integrator U3, the inverter U4, the inverter U5, the inverse integrator U6, the inverter U7, the inverter U8, the inverse integrator U9, the inverter U10, the inverter U11 and the inverse integrator U12 adopt an operational amplifier LM 741.
The multiplier a1, the multiplier a2 and the multiplier A3 adopt a multiplier AD 633.
In the first channel, the resistance R11 is 1K Ω, the resistance R12 is 33K Ω, the resistance R13 is 1K Ω, the resistance R16 is 10K Ω, the resistance R17 is 10K Ω, the resistance R18 is 10K Ω, the resistance R14 is 1K Ω, the resistance R19 is 1K Ω, the resistance R20 is 1K Ω, and the capacitance C1 is 10 nF; in the second channel, the resistance R21 is 0.5K Ω, the resistance R22 is 3.3K Ω, the resistance R23 is 10K Ω, the resistance R24 is 10K Ω, the resistance R25 is 10K Ω, the resistance R26 is 10K Ω, the resistance R27 is 10K Ω, and the capacitance C2 is 0.1 μ F; in the third channel, the resistor R31 is 1K Ω, the resistor R32 is 10K Ω, the resistor R34 is 1K Ω, the resistor R35 is 5K Ω, the resistor R36 is 10K Ω, the resistor R38 is 10K Ω, and the capacitor C3 is 10 nF; in the fourth channel, the resistance R41 is 5K Ω, the resistance R43 is 10K Ω, the resistance R44 is 10K Ω, the resistance R45 is 10K Ω, the resistance R47 is 10K Ω, and the capacitance C4 is 10 nF; VCC-15V, VDD-15V.
The invention has the beneficial effects that:
the simulation oscilloscope of the invention is easy to observe x-y, x-z, y-z, x-w, y-w, z-w phase diagrams, has a simpler circuit structure, is easy to realize, and is suitable for teaching and demonstration of nonlinear chaotic circuits and model analysis research of coupled power generation systems.
Drawings
Fig. 1 is a circuit diagram of the present invention.
Fig. 2 is a graph of the x-output waveform of fig. 1.
Fig. 3 is a waveform diagram of the y output of fig. 1.
Fig. 4 is a waveform diagram of the z-output of fig. 1.
Fig. 5 is a w-output waveform diagram of fig. 1.
Fig. 6 is an x-y output phase diagram of fig. 1.
FIG. 7 is an x-z output phase diagram of FIG. 1.
FIG. 8 is a y-z output phase diagram of FIG. 1.
Fig. 9 is an x-w output phase diagram of fig. 1.
Fig. 10 is a y-w output phase diagram of fig. 1.
FIG. 11 is a z-w output phase diagram of FIG. 1.
Detailed Description
The invention is described in detail below with reference to the figures and examples.
Referring to fig. 1, a four-dimensional coupling power generation hyperchaotic system analog circuit includes a first channel, a second channel, a third channel and a fourth channel;
the output end of the first channel is connected with the first input end of the first channel, the first input end of the second channel and the first input pin of the multiplier A1 in the third channel; the output end of the previous stage of the output end of the first channel is connected with the first input pin of the multiplier A2 in the second channel;
the output end of the second channel is connected with the second input end of the second channel and the input end of the fourth channel; the previous stage output end of the second channel output end is connected with the second input end of the first channel, the first input pin of the multiplier A3 in the first channel and the second input pin of the multiplier A1 in the third channel;
the output end of the previous stage of the output end of the third channel is connected with the second input pin of the multiplier A3 in the first channel, the second input pin of the multiplier A2 in the second channel and the input end of the third channel;
and the previous stage output end of the fourth channel is connected with the third input end of the first channel.
The first channel comprises an inverter U1, a pin 2 of the inverter U1 is connected with one ends of a resistor R11, a resistor R12, a resistor R13, a resistor R14 and a resistor R17, the other end of the resistor R11 is connected with the output end of a multiplier A3, the other end of the resistor R12 is connected with the output end of the first channel, a resistor R13 is connected with the previous-stage output end of the second channel, the previous-stage output end of the fourth-channel output end of the resistor R14, the other end of the resistor R17 is connected with a pin 6 of the inverter U1 and one end of a resistor R18, the other end of the resistor R18 is connected with a pin 2 of an inverse integrator U3 and one end of a capacitor C1, the other end of the capacitor C1 is connected with a pin 6 of the inverse integrator U3 and one end of a resistor R19, the other end of the resistor R19 is connected with a pin 2 of the inverter U19; the 4-pin of the inverter U1, the 4-pin of the inverter U2, and the 4-pin of the inverting integrator U3 are connected to VDD (negative voltage), and the 7-pin of the inverter U1, the 7-pin of the inverter U2, and the 7-pin of the inverting integrator U3 are connected to VCC (positive voltage).
The output of the inverter U2 of the first channel is signal-x, and the output of the inverting integrator U3 is signal x.
The second channel comprises an inverter U4, a pin 2 of the inverter U4 is connected with one end of a resistor R21, a resistor R22, a resistor R23 and one end of a resistor R24, the other end of the resistor R21 is connected with the output end of a multiplier A2, the other end of the resistor R22 is connected with the output end of the first channel, one end of a resistor R23 is connected with the output end of the second channel, the other end of the resistor R24 is connected with a pin 6 of the inverter U4 and one end of a resistor R25, the other end of the resistor R25 is connected with a pin 2 of an inverse integrator U6 and one end of a capacitor C2, the other end of the capacitor C2 is connected with a pin 6 of the inverse integrator U5968642 and one end of a resistor R6368628, the other end of the resistor R6959 is connected with a pin 2 of the inverter U5 and one end of a resistor; the 3 pin of the inverting amplifier U4, the 3 pin of the inverting amplifier U5 and the 3 pin of the inverting integrator U6 are grounded; the 4 pins of the inverter U4, the 4 pins of the inverter U5 and the 4 pins of the inverse integrator U6 are connected with VDD (negative voltage), and the 7 pins of the inverter U4, the 7 pins of the inverter U5 and the 7 pins of the inverse integrator U6 are connected with VCC (positive voltage);
the signal at the output of the second channel inverter U5 is-y, and the signal at the output of the second channel inverting integrator U6 is y.
The third channel comprises an inverter U7, a2 script of the inverter U7 is connected with one ends of a resistor R31, a resistor R32 and a resistor R34, the other end of the resistor R31 is connected with the output end of a multiplier A1, the other end of a resistor R32 is connected with the previous-stage output end of the third channel, the other end of a resistor R34 is connected with the 6 pin of the inverter U7 and one end of a resistor R35, the other end of a resistor R35 is connected with one end of a capacitor C3 and the pin 2 of the inverse integrator U9, the other end of a capacitor C3 is connected with the 6 pin of the inverse integrator U9 and one end of a resistor R36, the other end of a resistor R36 is connected with one end of the resistor R38 and the 2 pin of the inverter U573; the 3 pin of the inverting amplifier U7, the 3 pin of the inverting amplifier U8 and the 3 pin of the inverting integrator U9 are grounded; the 4-pin of the inverter U7, the 4-pin of the inverter U8, and the 4-pin of the inverting integrator U9 are connected to VDD (negative voltage), and the 7-pin of the inverter U7, the 7-pin of the inverter U8, and the 7-pin of the inverting integrator U9 are connected to VCC (positive voltage).
The output end signal of the third channel inverter U8 is-z, and the output end of the third channel inverting integrator U9 is the signal z.
The fourth channel comprises an inverter U10, a2 script of the inverter U10 is connected with one ends of a resistor R41 and a resistor R43, the other end of the resistor R41 is connected with the output end of the second channel, the other end of a resistor R43 is connected with a pin 6 of the inverter U10 and one end of a resistor R44, the other end of the resistor R44 is connected with one end of a capacitor C4 and a pin 2 of an inverse integrator U12, the other end of the capacitor C4 is connected with a pin 6 of the inverse integrator U12 and one end of a resistor R45, the other end of the resistor R45 is connected with one end of a resistor R47 and a pin 2 of the inverter U11, and the other end of the resistor R47 is connected with a pin 6 of the; the 3 pin of the inverter U10, the 3 pin of the inverter U11 and the 3 pin of the inverse integrator U12 are grounded; the 4-pin of the inverter U10, the 4-pin of the inverter U11, and the 4-pin of the inverting integrator U12 are connected to VDD (negative voltage), and the 7-pin of the inverter U10, the 7-pin of the inverter U11, and the 7-pin of the inverter integration U12 are connected to VCC (positive voltage).
The output end signal of the fourth channel inverter U11 is-w, and the output end of the fourth channel inverting integrator U12 is the signal w.
The inverter U1, the inverter U2, the inverse integrator U3, the inverter U4, the inverter U5, the inverse integrator U6, the inverter U7, the inverter U8, the inverse integrator U9, the inverter U10, the inverter U11 and the inverse integrator U12 adopt an operational amplifier LM 741.
The multiplier a1, the multiplier a2 and the multiplier A3 adopt a multiplier AD 633.
In the first channel, the resistance R11 is 1K Ω, the resistance R12 is 33K Ω, the resistance R13 is 1K Ω, the resistance R16 is 10K Ω, the resistance R17 is 10K Ω, the resistance R18 is 10K Ω, the resistance R14 is 1K Ω, the resistance R19 is 1K Ω, the resistance R20 is 1K Ω, and the capacitance C1 is 10 nF; in the second channel, the resistance R21 is 0.5K Ω, the resistance R22 is 3.3K Ω, the resistance R23 is 10K Ω, the resistance R24 is 10K Ω, the resistance R25 is 10K Ω, the resistance R26 is 10K Ω, the resistance R27 is 10K Ω, and the capacitance C2 is 0.1 μ F; in the third channel, the resistor R31 is 1K Ω, the resistor R32 is 10K Ω, the resistor R34 is 1K Ω, the resistor R35 is 5K Ω, the resistor R36 is 10K Ω, the resistor R38 is 10K Ω, and the capacitor C3 is 10 nF; in the fourth channel, the resistance R41 is 5K Ω, the resistance R43 is 10K Ω, the resistance R44 is 10K Ω, the resistance R45 is 10K Ω, the resistance R47 is 10K Ω, and the capacitance C4 is 10 nF; VCC-15V, VDD-15V.
The working principle of the invention is as follows:
the four-dimensional coupling power generation hyperchaotic system related by the invention has very complex chaotic characteristics because the system contains two Lyapunov indexes which are more than 0. If the output signal of the circuit is used as a carrier signal, the carrier signal and the target signal are modulated through a correlation algorithm, and the effect of communication secrecy can be achieved. The dimensionless mathematical model related to the invention is as follows:
in the formula (1), x, y, z and w are state variables, α, b, c and k are parameters of the equation, and the system (1) is a four-dimensional coupling power generation hyperchaotic system.
The circuit according to the invention is composed of circuits of a first, a second, a third and a fourth channel, which realize a first, a second, a third and a fourth function in equation (1), respectively. When the inverse integrator and the inverter adopt LM741, and the analog multiplier adopts AD633, the output waveform diagrams of the circuit are shown in fig. 2, fig. 3, fig. 4 and fig. 5, the phase diagrams of the circuit output are shown in fig. 6, fig. 7, fig. 8, fig. 9, fig. 10 and fig. 11, and fig. 2 to fig. 11 reflect the basic chaotic characteristics of the four-dimensional coupling power generation system, so that the chaotic types are enriched, and a new model and thought are provided for describing the earth magnetic polarity reversal for the chaotic system.
Claims (4)
1. A four-dimensional coupling power generation hyperchaotic system analog circuit comprises a first channel, a second channel, a third channel and a fourth channel, and is characterized in that:
the output end of the first channel is connected with the first input end of the first channel, the first input end of the second channel and the first input pin of the multiplier A1 in the third channel; the output end of the previous stage of the output end of the first channel is connected with the first input pin of the multiplier A2 in the second channel;
the output end of the second channel is connected with the second input end of the second channel and the input end of the fourth channel; the previous stage output end of the second channel output end is connected with the second input end of the first channel, the first input pin of the multiplier A3 in the first channel and the second input pin of the multiplier A1 in the third channel;
the output end of the previous stage of the output end of the third channel is connected with the second input pin of the multiplier A3 in the first channel, the second input pin of the multiplier A2 in the second channel and the input end of the third channel;
the previous stage output end of the fourth channel is connected with the third input end of the first channel;
the first channel comprises an inverter U1, a pin 2 of the inverter U1 is connected with one ends of a resistor R11, a resistor R12, a resistor R13, a resistor R14 and a resistor R17, the other end of the resistor R11 is connected with the output end of a multiplier A3, the other end of the resistor R12 is connected with the output end of the first channel, a resistor R13 is connected with the previous-stage output end of the second channel output end, the other end of the resistor R14 is connected with the previous-stage output end of the fourth channel output end, the other end of the resistor R17 is connected with a pin 6 of an inverter U1 and one end of a resistor R18, the other end of the resistor R18 is connected with a pin 2 of an inverse integrator U3 and one end of a capacitor C1, the other end of the capacitor C1 is connected with a pin 6 of an inverse integrator U3 and one end of a resistor R19, the other end of the resistor R19 is connected with a pin 2 of the inverter U36; the 4 pins of the inverter U1, the 4 pins of the inverter U2 and the 4 pins of the inverse integrator U3 are connected with VDD, and the 7 pins of the inverter U1, the 7 pins of the inverter U2 and the 7 pins of the inverse integrator U3 are connected with VCC;
the second channel comprises an inverter U4, a pin 2 of the inverter U4 is connected with one end of a resistor R21, a resistor R22, a resistor R23 and one end of a resistor R24, the other end of the resistor R21 is connected with the output end of a multiplier A2, the other end of the resistor R22 is connected with the output end of the first channel, one end of a resistor R23 is connected with the output end of the second channel, the other end of the resistor R24 is connected with a pin 6 of the inverter U4 and one end of a resistor R25, the other end of the resistor R25 is connected with a pin 2 of an inverse integrator U6 and one end of a capacitor C2, the other end of the capacitor C2 is connected with a pin 6 of the inverse integrator U5968642 and one end of a resistor R6368628, the other end of the resistor R6959 is connected with a pin 2 of the inverter U5 and one end of a resistor; the 3 pin of the inverting amplifier U4, the 3 pin of the inverting amplifier U5 and the 3 pin of the inverting integrator U6 are grounded; the 4 pins of the inverter U4, the 4 pins of the inverter U5 and the 4 pins of the inverse integrator U6 are connected with VDD, and the 7 pins of the inverter U4, the 7 pins of the inverter U5 and the 7 pins of the inverse integrator U6 are connected with VCC;
the third channel comprises an inverter U7, a2 script of the inverter U7 is connected with one ends of a resistor R31, a resistor R32 and a resistor R34, the other end of the resistor R31 is connected with the output end of a multiplier A1, the other end of a resistor R32 is connected with the previous-stage output end of the third channel, the other end of a resistor R34 is connected with the 6 pin of the inverter U7 and one end of a resistor R35, the other end of a resistor R35 is connected with one end of a capacitor C3 and the pin 2 of the inverse integrator U9, the other end of a capacitor C3 is connected with the 6 pin of the inverse integrator U9 and one end of a resistor R36, the other end of a resistor R36 is connected with one end of the resistor R38 and the 2 pin of the inverter U573; the 3 pin of the inverting amplifier U7, the 3 pin of the inverting amplifier U8 and the 3 pin of the inverting integrator U9 are grounded; the 4 pins of the inverter U7, the 4 pins of the inverter U8 and the 4 pins of the inverse integrator U9 are connected with VDD, and the 7 pins of the inverter U7, the 7 pins of the inverter U8 and the 7 pins of the inverse integrator U9 are connected with VCC;
the fourth channel comprises an inverter U10, a2 script of the inverter U10 is connected with one ends of a resistor R41 and a resistor R43, the other end of the resistor R41 is connected with the output end of the second channel, the other end of a resistor R43 is connected with a pin 6 of the inverter U10 and one end of a resistor R44, the other end of the resistor R44 is connected with one end of a capacitor C4 and a pin 2 of an inverse integrator U12, the other end of the capacitor C4 is connected with a pin 6 of the inverse integrator U12 and one end of a resistor R45, the other end of the resistor R45 is connected with one end of a resistor R47 and a pin 2 of the inverter U11, and the other end of the resistor R47 is connected with a pin 6 of the; the 3 pin of the inverter U10, the 3 pin of the inverter U11 and the 3 pin of the inverse integrator U12 are grounded; the 4 pin of the inverter U10, the 4 pin of the inverter U11 and the 4 pin of the inverse integrator U12 are connected with VDD, and the 7 pin of the inverter U10, the 7 pin of the inverter U11 and the 7 pin of the inverter integration U12 are connected with VCC.
2. The four-dimensional coupled power generation hyperchaotic system analog circuit as claimed in claim 1, wherein the output of inverter U2 of the first channel is signal-x, and the output of inverting integrator U3 is signal x;
the output end signal of the second channel inverter U5 is-y, and the output end of the second channel inverting integrator U6 is a signal y;
the output end signal of the third channel inverter U8 is-z, and the output end of the third channel inverting integrator U9 is a signal z;
the output end signal of the fourth channel inverter U11 is-w, and the output end of the fourth channel inverting integrator U12 is the signal w.
3. The four-dimensional coupled power generation hyperchaotic system analog circuit of claim 1, wherein the inverter U1, the inverter U2, the inverse integrator U3, the inverter U4, the inverter U5, the inverse integrator U6, the inverter U7, the inverter U8, the inverse integrator U9, the inverter U10, the inverter U11 and the inverse integrator U12 adopt an operational amplifier LM 741.
4. The four-dimensional coupled power generation hyperchaotic system analog circuit of claim 1, wherein the multiplier a1, the multiplier a2 and the multiplier A3 are multiplier AD 633.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710557674.5A CN108022488B (en) | 2017-07-10 | 2017-07-10 | Four-dimensional coupling power generation hyperchaotic system analog circuit |
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