CN206341225U - A kind of Shimizu Morioka chaos circuits for containing four parameters - Google Patents
A kind of Shimizu Morioka chaos circuits for containing four parameters Download PDFInfo
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- CN206341225U CN206341225U CN201720015771.7U CN201720015771U CN206341225U CN 206341225 U CN206341225 U CN 206341225U CN 201720015771 U CN201720015771 U CN 201720015771U CN 206341225 U CN206341225 U CN 206341225U
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Abstract
A kind of Shimizu Morioka chaos circuits for containing four parameters, including first passage, second channel and third channel；The previous stage output end of first passage connects first, second input pin of the multiplier of the first input end, the first input pin of the multiplier of second channel and third channel of second channel；The output end of second channel connects the second input of second channel；The previous stage output signal of second channel output signal connects the signal input part of first passage；First input signal end of the output signal connection third channel of third channel and the second input pin of the multiplier of second channel；When using, the output end signal of first passage phase inverter is x, and the output end of inverting integrator is signal x, and the output end signal of second channel phase inverter is y, the output end of inverting integrator is that the output end signal of signal y roads phase inverter is z, and the output end of third channel inverting integrator is signal z；The utility model has the advantages that so that circuit module is simple and reliable.
Description
Technical field
The utility model belongs to nonlinear properties generator technical field, specifically related to a kind of Shimizu- for containing four parameters
Morioka chaos circuits.
Background technology
Early in 1980, Shimizu T. and Morioka N. just constructed Shimizu-Morioka systems, than classics
Lorenz chaos systems one item missing in structure, so it is particularly important to study such chaos system；Shimizu-Morioka chaos
System is applied in practice, and most direct method is just construction chaos circuit, and there are simple terms can produce abundant chaos system for design
Circuit, nonlinear circuit design in it is extremely important.If will be applied to containing the more chaos system circuit of parameter in teaching,
Student can more be strengthened and understand the understanding that parameter influences on chaos system, it is therefore desirable to resistance reasonable in design so that should
The output signal of chaos system has very strong chaotic characteristic.
The content of the invention
In order to overcome the shortcoming of above-mentioned prior art, the purpose of this utility model is to provide a kind of four parameters that contain
Shimizu-Morioka chaos circuits, by resistance reasonable in design, although can have the simple output signal of its system
There is very strong chaotic characteristic.
In order to achieve the above object, the technical scheme that the utility model is taken is：
A kind of Shimizu-Morioka chaos circuits for containing four parameters, including first passage, second channel and threeway
Road；
The first input end of the previous stage output end connection second channel of described first passage, the multiplier of second channel
First, second input pin of A2 the first input pin and the multiplier A1 of third channel；The output end connection of second channel
Second input of second channel；The signal input of the previous stage output signal connection first passage of second channel output signal
End；First input signal end of the output signal connection third channel of third channel and the second input of the multiplier of second channel
Pin.
Described first passage includes phase inverter U1, phase inverter U1 2 pin connecting resistance R11, resistance R12 one end, electricity
Draw the 6 of previous stage signal y, resistance the R12 other end connection phase inverter U1 of the output of resistance R11 other end connection second channel
Pin；Phase inverter U1 6 pins are by resistance R13 connection inverting integrators U3 2 pins and electric capacity C1 one end, and electric capacity C1's is another
One end connection inverting integrator U3 6 pins；Inverting integrator U3 6 pins 2 are drawn by what resistance R14 was connected to phase inverter U2
Pin, phase inverter U2 2 pins connection resistance R15 one end, resistance R15 other ends connection phase inverter U2 6 pins；Phase inverter U1's
The 3 pins ground connection of 3 pins, the U2 of phase inverter 3 pins and inverting integrator U3, phase inverter U1 4 pins, the 4 of phase inverter U2
Pin and inverting integrator U3 4 pins meet VDD (negative voltage), phase inverter U1 7 pins, phase inverter U2 7 pins with it is anti-phase
Integrator U3 7 pins meet VCC (positive voltage)；
Described second channel includes multiplier A2, the pin 2 that multiplier A2 output ends pass through resistance R22 and phase inverter U4
It is connected；The U4 of phase inverter 2 pins are connected with resistance R21, resistance R1 one end, and the resistance R21 other end and first passage is defeated
The previous stage output signal connection gone out, the resistance R1 other end is connected with second channel output signal, the U4 of phase inverter 2 pins
Pass through resistance R24 connection phase inverters U4 6 pins；Phase inverter U4 6 pins pass through the 2 of resistance R25 connection inverting integrators U6
One end of pin and electric capacity C2, electric capacity C2 other end connection inverting integrator U6 6 pins；Inverting integrator U6 6 pins
Phase inverter U5 2 pins are connected to by resistance R26；Phase inverter U5 2 pins connection resistance R27 one end, the resistance R27 other ends
Connect phase inverter U5 6 pins, the 3 pins ground connection of phase inverter U4 3 pins, phase inverter U5 3 pins and inverting integrator U6；
4 pins of phase inverter U4 4 pins, phase inverter U5 4 pins and inverting integrator U6 meet VDD (negative voltage), the 7 of phase inverter U4
7 pins of pin, phase inverter U5 7 pins and inverting integrator U6 meet VCC (positive voltage)；
Described third channel includes multiplier A1, and multiplier A1 output ends 2 are drawn by what R35 was connected to phase inverter U7
Pin, one end of resistance R34 and resistance R36 one end, the other end connection third channel output signal of resistance R34, resistance R36's
Other end connection phase inverter U7 pin 6；Phase inverter U7 pin 6 by resistance R37 connection inverting integrators U9 2 pins,
The connection electric capacity of inverting integrator U9 pins 2 C3 one end, electric capacity C3 other end connection inverting integrator U9 6 pins；It is anti-phase
Integrator U9 6 pins are connected to phase inverter U8 2 pins by resistance R38；Phase inverter U8 2 pins connection resistance R39 mono-
End, resistance R39 other ends connection phase inverter U8 6 pins；It is phase inverter U7 3 pins, inverting integrator U9 3 pins, anti-phase
Device U8 3 pins ground connection；Phase inverter U7 4 pins, inverting integrator U9 4 pins, phase inverter U8 4 pins connect VDD (negative electricity
Pressure), phase inverter U7 7 pins, phase inverter integration U9 7 pins, phase inverter U8 7 pins meet VCC (positive voltage)；
Described first passage phase inverter U2 output end signal is-x, and inverting integrator U3 output end is signal x, electricity
Hinder R11=83k Ω, R12=R13=R15=10K Ω, R14=1K Ω, C1=10nF.
Described second channel phase inverter U5 output end signal is-y, and inverting integrator U6 output end is signal y, electricity
Hinder R21=50K Ω, R22=10K Ω, R1=117K Ω, R27=10K Ω, C2=10nF, R24=R25=R26=10K Ω.
Described third channel phase inverter U8 output end signal is-z, and third channel inverting integrator U9 output end is
Signal z, resistance R34=200k Ω, R35=10k Ω, R36==R37=R38=R39=10K Ω, C3=10nF.
Described phase inverter U1, phase inverter U2, inverting integrator U3, phase inverter U4, phase inverter U5, inverting integrator U6,
Phase inverter U7, phase inverter U8, inverting integrator U9 use transport and placing device LM741.
Described multiplier A1, multiplier A2 uses multiplier AD633.
Described VCC=15, VDD=-15V.
The beneficial effects of the utility model：
Using the utility model, x-y, x-z, y-z phasors, with circuit structure can be observed on common oscillograph
Simply, circuit performance is reliable and easily realizes, it is adaptable to university's Chaotic Experiment teaching, nonlinear circuit demonstration etc., information security,
There is important value in the fields such as communication security.
Brief description of the drawings
Fig. 1 is circuit diagram of the present utility model.
Fig. 2 is Fig. 1 x output waveform figures.
Fig. 3 is Fig. 1 y output waveform figures.
Fig. 4 is Fig. 1 z output waveform figures.
Fig. 5 is Fig. 1 x-y output phasors.
Fig. 6 is Fig. 1 x-z output phasors.
Fig. 7 is Fig. 1 y-z output phasors.
Embodiment
The utility model is described in detail with reference to the accompanying drawings and examples.
Reference picture 1, a kind of Shimizu-Morioka chaos circuits for containing four parameters, including first passage, second channel and
Third channel；
The first input end of the previous stage output end connection second channel of described first passage, the multiplier of second channel
First, second input pin of A2 the first input pin and the multiplier A1 of third channel；The output end connection of second channel
Second input of second channel；The signal input of the previous stage output signal connection first passage of second channel output signal
End；First input signal end of the output signal connection third channel of third channel and the second input of the multiplier of second channel
Pin.
Described first passage includes phase inverter U1, phase inverter U1 2 pin connecting resistance R11, resistance R12 one end, electricity
Draw the 6 of previous stage signal y, resistance the R12 other end connection phase inverter U1 of the output of resistance R11 other end connection second channel
Pin；Phase inverter U1 6 pins are by resistance R13 connection inverting integrators U3 2 pins and electric capacity C1 one end, and electric capacity C1's is another
One end connection inverting integrator U3 6 pins；Inverting integrator U3 6 pins 2 are drawn by what resistance R14 was connected to phase inverter U2
Pin, phase inverter U2 2 pins connection resistance R15 one end, resistance R15 other ends connection phase inverter U2 6 pins；Phase inverter U1's
The 3 pins ground connection of 3 pins, the U2 of phase inverter 3 pins and inverting integrator U3, phase inverter U1 4 pins, the 4 of phase inverter U2
Pin and inverting integrator U3 4 pins meet VDD (negative voltage), phase inverter U1 7 pins, phase inverter U2 7 pins with it is anti-phase
Integrator U3 7 pins meet VCC (positive voltage)；
Described second channel includes multiplier A2, the pin 2 that multiplier A2 output ends pass through resistance R22 and phase inverter U4
It is connected；The U4 of phase inverter 2 pins are connected with resistance R21, resistance R1 one end, and the resistance R21 other end and first passage is defeated
The previous stage output signal connection gone out, the resistance R1 other end is connected with second channel output signal, the U4 of phase inverter 2 pins
Pass through resistance R24 connection phase inverters U4 6 pins；Phase inverter U4 6 pins pass through the 2 of resistance R25 connection inverting integrators U6
One end of pin and electric capacity C2, electric capacity C2 other end connection inverting integrator U6 6 pins；Inverting integrator U6 6 pins
Phase inverter U5 2 pins are connected to by resistance R26；Phase inverter U5 2 pins connection resistance R27 one end, the resistance R27 other ends
Connect phase inverter U5 6 pins, the 3 pins ground connection of phase inverter U4 3 pins, phase inverter U5 3 pins and inverting integrator U6；
4 pins of phase inverter U4 4 pins, phase inverter U5 4 pins and inverting integrator U6 meet VDD (negative voltage), the 7 of phase inverter U4
7 pins of pin, phase inverter U5 7 pins and inverting integrator U6 meet VCC (positive voltage)；
Described third channel includes multiplier A1, and multiplier A1 output ends 2 are drawn by what R35 was connected to phase inverter U7
Pin, one end of resistance R34 and resistance R36 one end, the other end connection third channel output signal of resistance R34, resistance R36's
Other end connection phase inverter U7 pin 6；Phase inverter U7 pin 6 by resistance R37 connection inverting integrators U9 2 pins,
The connection electric capacity of inverting integrator U9 pins 2 C3 one end, electric capacity C3 other end connection inverting integrator U9 6 pins；It is anti-phase
Integrator U9 6 pins are connected to phase inverter U8 2 pins by resistance R38；Phase inverter U8 2 pins connection resistance R39 mono-
End, resistance R39 other ends connection phase inverter U8 6 pins；It is phase inverter U7 3 pins, inverting integrator U9 3 pins, anti-phase
Device U8 3 pins ground connection；Phase inverter U7 4 pins, inverting integrator U9 4 pins, phase inverter U8 4 pins connect VDD (negative electricity
Pressure), phase inverter U7 7 pins, phase inverter integration U9 7 pins, phase inverter U8 7 pins meet VCC (positive voltage)；
Described first passage phase inverter U2 output end signal is-x, and inverting integrator U3 output end is signal x, electricity
Hinder R11=83k Ω, R12=R13=R15=10K Ω, R14=1K Ω, C1=10nF.
Described second channel phase inverter U5 output end signal is-y, and inverting integrator U6 output end is signal y, electricity
Hinder R21=50K Ω, R22=10K Ω, R1=117K Ω, R27=10K Ω, C2=10nF, R24=R25=R26=10K Ω.
Described third channel phase inverter U8 output end signal is-z, and third channel inverting integrator U9 output end is
Signal z, resistance R34=200k Ω, R35=10k Ω, R36==R37=R38=R39=10K Ω, C3=10nF.
Described phase inverter U1, phase inverter U2, inverting integrator U3, phase inverter U4, phase inverter U5, inverting integrator U6,
Phase inverter U7, phase inverter U8, inverting integrator U9 use transport and placing device LM741.
Described multiplier A1, multiplier A2 uses multiplier AD633.
Described VCC=15, VDD=-15V.
Operation principle of the present utility model is：
The chaotic characteristic of the circuit is extremely complex, if the output signal is passed through into phase with echo signal as carrier signal
Algorithm modulation is closed, because the pseudo-randomness of chaotic signal, then secret communication and the anti-purpose cracked can be met.Involved
Dimensionless Mathematical Modeling is as follows：
In formula (1), x, y, z is system variable, a, b, and c, d is systematic parameter, works as a=1.2, b=2, c=0.85, d=
When 0.5, system (1) contains four parameter Shimizu-Morioka chaos systems, now the side of oscillating circuit of the present utility model
Cheng Wei：
Circuit involved by the utility model includes first, second, third passage, the circuit of first, second, third passage
Timesharing realizes first, second, third function in formula (2), when analog multiplier uses AD633, the output waveform figure of circuit
See Fig. 2, Fig. 3, Fig. 4, the phasor of circuit output, which is shown on Fig. 5, Fig. 6, Fig. 7, figure to have shown out, contains four parameter Shimizu-
The chaotic characteristic of Morioka circuit systems, enriches the type of chaos, is provided for chaos applications in communication security device and encryption
Selection.
Claims (8)
1. a kind of Shimizu-Morioka chaos circuits for containing four parameters, including first passage, second channel and third channel,
It is characterized in that：
The previous stage output end connection first input end of second channel of described first passage, the multiplier A2 of second channel
The multiplier A1 of first input pin and third channel first, second input pin；The output end connection second of second channel
Second input of passage；The previous stage output signal of second channel output signal connects the signal input part of first passage；The
First input signal end of the output signal connection third channel of triple channel and the second input pin of the multiplier of second channel.
2. a kind of Shimizu-Morioka chaos circuits for containing four parameters according to claim 1, it is characterised in that：
Described first passage includes phase inverter U1, phase inverter U1 2 pin connecting resistance R11, resistance R12 one end, resistance R11
Other end connection second channel output previous stage signal y, resistance the R12 other end connection phase inverter U1 6 pins；It is anti-phase
Device U1 6 pins are connected by resistance R13 connection inverting integrators U3 2 pins and electric capacity C1 one end, the electric capacity C1 other end
Connect inverting integrator U3 6 pins；Inverting integrator U3 6 pins are connected to phase inverter U2 2 pins by resistance R14, instead
Phase device U2 2 pins connection resistance R15 one end, resistance R15 other ends connection phase inverter U2 6 pins；Draw the 3 of phase inverter U1
The 3 pins ground connection of pin, the U2 of phase inverter 3 pins and inverting integrator U3, phase inverter U1 4 pins, phase inverter U2 4 pins
VDD (negative voltage), phase inverter U1 7 pins, phase inverter U2 7 pins and anti-phase integration are connect with inverting integrator U3 4 pins
Device U3 7 pins meet VCC (positive voltage)；
Described second channel includes multiplier A2, the phase of pin 2 that multiplier A2 output ends pass through resistance R22 and phase inverter U4
Even；The U4 of phase inverter 2 pins are connected with resistance R21, resistance R1 one end, and resistance the R21 other end and first passage are exported
The connection of previous stage output signal, the resistance R1 other end is connected with second channel output signal, and the U4 of phase inverter 2 pins are logical
Cross resistance R24 connection phase inverters U4 6 pins；Phase inverter U4 6 pins draw by the 2 of resistance R25 connection inverting integrators U6
One end of pin and electric capacity C2, electric capacity C2 other end connection inverting integrator U6 6 pins；Inverting integrator U6 6 pins lead to
Cross 2 pins that resistance R26 is connected to phase inverter U5；Phase inverter U5 2 pins connection resistance R27 one end, the resistance R27 other ends connect
Connect phase inverter U5 6 pins, the 3 pins ground connection of phase inverter U4 3 pins, phase inverter U5 3 pins and inverting integrator U6；Instead
4 pins of phase device U4 4 pins, phase inverter U5 4 pins and inverting integrator U6 meet VDD (negative voltage), and the 7 of phase inverter U4 draws
7 pins of pin, phase inverter U5 7 pins and inverting integrator U6 meet VCC (positive voltage)；
Described third channel includes multiplier A1, and multiplier A1 output ends are connected to phase inverter U7 2 pins by R35, electricity
R34 one end and resistance R36 one end are hindered, the other end of resistance R34 connects third channel output signal, and resistance R36's is another
End connection phase inverter U7 pin 6；Phase inverter U7 pin 6 is anti-phase by resistance R37 connection inverting integrators U9 2 pins
The connection electric capacity of integrator U9 pins 2 C3 one end, electric capacity C3 other end connection inverting integrator U9 6 pins；Anti-phase integration
Device U9 6 pins are connected to phase inverter U8 2 pins by resistance R38；Phase inverter U8 2 pins connection resistance R39 one end, electricity
Hinder R39 other ends connection phase inverter U8 6 pins；Phase inverter U7 3 pins, inverting integrator U9 3 pins, phase inverter U8
3 pins are grounded；Phase inverter U7 4 pins, inverting integrator U9 4 pins, phase inverter U8 4 pins meet VDD (negative voltage), instead
Phase device U7 7 pins, phase inverter integration U9 7 pins, phase inverter U8 7 pins meet VCC (positive voltage).
3. a kind of Shimizu-Morioka chaos circuits for containing four parameters according to claim 2, it is characterised in that：Institute
The first passage phase inverter U2 stated output end signal is-x, and inverting integrator U3 output end is signal x, resistance R11=83k
Ω, R12=R13=R15=10K Ω, R14=1K Ω, C1=10nF.
4. a kind of Shimizu-Morioka chaos circuits for containing four parameters according to claim 2, it is characterised in that：Institute
The second channel phase inverter U5 stated output end signal is-y, and inverting integrator U6 output end is signal y, resistance R21=50K
Ω, R22=10K Ω, R1=117K Ω, R27=10K Ω, C2=10nF, R24=R25=R26=10K Ω.
5. a kind of Shimizu-Morioka chaos circuits for containing four parameters according to claim 2, it is characterised in that：Institute
The third channel phase inverter U8 stated output end signal is-z, and third channel inverting integrator U9 output end is signal z, resistance
R34=200k Ω, R35=10k Ω, R36==R37=R38=R39=10K Ω, C3=10nF.
6. a kind of Shimizu-Morioka chaos circuits for containing four parameters according to claim 2, it is characterised in that：Institute
It is the phase inverter U1 that states, phase inverter U2, inverting integrator U3, phase inverter U4, phase inverter U5, inverting integrator U6, phase inverter U7, anti-
Phase device U8, inverting integrator U9 use transport and placing device LM741.
7. a kind of Shimizu-Morioka chaos circuits for containing four parameters according to claim 2, it is characterised in that：Institute
Multiplier A1, the multiplier A2 stated uses multiplier AD633.
8. a kind of Shimizu-Morioka chaos circuits for containing four parameters according to claim 2, it is characterised in that：Institute
The VCC=15 stated, VDD=-15V.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107612677A (en) * | 2017-11-10 | 2018-01-19 | 西京学院 | A kind of four hyperchaotic circuits of four-dimension |
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2017
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107612677A (en) * | 2017-11-10 | 2018-01-19 | 西京学院 | A kind of four hyperchaotic circuits of four-dimension |
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