CN205265706U - Chaos circuit of three -dimensional autonomy transition T of system - Google Patents
Chaos circuit of three -dimensional autonomy transition T of system Download PDFInfo
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- CN205265706U CN205265706U CN201520995801.6U CN201520995801U CN205265706U CN 205265706 U CN205265706 U CN 205265706U CN 201520995801 U CN201520995801 U CN 201520995801U CN 205265706 U CN205265706 U CN 205265706U
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Abstract
The utility model provides a chaos circuit of three -dimensional autonomy transition T of system, including three passageway, the output signal of first passageway feeds back the input, as incoming signal of the same kind, multiplier A1's input pin in this signal connection second channel, the multiplier A2 in the preceding one -level output connection third passageway of first passageway and the input of second channel, the multiplier A2's in the input of third passageway input pin is still connected in the output of second channel, output feedback to the input of third passageway, and the output signal of preceding one -level connects the input pin that multiplier A1 is connected to the second channel. The utility model discloses it is simple to have circuit structure, circuit dependable performance and easy realization, and wherein resistance is national standard resistance, is applicable to the chaos circuit demonstration of university etc. Provides important value in fields such as communication security and multi -media encryption.
Description
Technical field
The utility model belongs to nonlinear properties generator technical field, is specifically related to a kind of three-dimensional autonomous transitionSystem T chaos circuit.
Background technology
Chaotic signal has the characteristics such as class is random, initial value is responsive, wide range, thus be widely used in secret communication withAnd the security fields such as figure encryption. In the chaos circuit of current research, mainly taking classical circuit as main asLorenz circuit, Chen circuit, LV circuit etc. Recent years, new chaos system constantly occurs,And whether one of standard that whether is a kind of new chaos is exactly known system more simple. And T chaos systemContain 6, there is different topology than Lorenz system one item missing and with classical system.
At present, chaos science is transitioned into practical application from theoretical research gradually, and in the most directly plan of engineeringThe slightly realization of chaos circuit, it is T chaotic circuit system that design has this type of transition system, seems particularly heavyWant. If will, containing this type of chaos system circuit application in teaching, more can strengthen student to nonlinear system electricityThe intuitive of road design.
Above-mentioned prior art exists in chaos circuit all resistance to be GB and T chaos system as a classTransition system is difficult for the problems such as design.
Summary of the invention
In order to overcome the shortcoming of above-mentioned prior art, the purpose of this utility model is to provide a kind of three-dimensional autonomous mistakeCross system T chaos circuit, communication security is higher, and the defeated signal of its nonlinear system has very strong chaosCharacteristic.
In order to achieve the above object, the technical scheme that the utility model is taked is:
A kind of three-dimensional autonomous transition system T chaos circuit, comprises first passage, second channel and third channel,The output signal of first passage feeds back to the input of first passage, and as a road input signal, this signal connectsConnect the input pin of multiplier A1 in second channel, the previous stage output of first passage connects in third channelThe input of multiplier A2 and second channel, the output of second channel also connects the multiplication in the input of third channelThe input pin of device A2, the output of third channel feeds back to the input of third channel, and third channel outputThe output signal of the previous stage of signal connects the input pin that second channel connects multiplier A1;
Described first passage comprises phase inverter U1, the 2 pin connecting resistance R11 of phase inverter U1, resistance R 12, electricityOne end of resistance R13, the other end of resistance R 11 is connected with the output signal of first passage, another of resistance R 12End is connected with the output signal of second channel, and resistance R 13 other ends connect 6 pins of phase inverter U1, phase inverter6 pins of U1 connect 2 pins of inverting integrator U3 by resistance R 14; Capacitor C 1 one end connects anti-phase integration2 pins of device U3, the other end of capacitor C 1 connects 6 pins of inverting integrator U3,6 of inverting integrator U3Pin is connected to 2 pins of phase inverter U2 by resistance R 15; The 2 pin contact resistance R16 mono-of phase inverter U2End, resistance R 16 other ends connect 6 pins of phase inverter U2; 3 of 3 pins of phase inverter U1, the U2 of phase inverterThe 3 pin ground connection of pin and inverting integrator U3; 4 pins of phase inverter U1,4 pins of phase inverter U2 are with anti-4 pins of phase integral device U3 meet VDD (negative voltage), 7 pins of phase inverter U1,7 pins of phase inverter U2Meet VCC (positive voltage) with 7 pins of inverting integrator U3, the output of the phase inverter U2 of first passage isSignal-x, the output of inverting integrator U3 is signal x;
Described second channel comprises multiplier A1, and multiplier A1 is by resistance R 22 and 2 of phase inverter U4Pin is connected; The output signal of resistance R 21 one end and first passage is connected, resistance R 21 other ends and anti-phase2 pins of the U4 of device are connected, and 2 pins of the U4 of the phase inverter resistance R 23 that was connected connects phase inverter6 pins of U4; 6 pins of phase inverter U4 connect 2 pins of inverting integrator U6 by resistance R 24,2 pins of inverting integrator U6 connect one end of capacitor C 2, and the other end of capacitor C 2 connects anti-phase integration6 pins of device U6; 6 pins of inverting integrator U6 are connected to 2 of phase inverter U5 by resistance R 25Pin; 2 pin contact resistance R26 one end of phase inverter U5, resistance R 26 other ends connect phase inverter U56 pins; 3 of 3 pins of the anti-phase U4 of putting, 3 pins of phase inverter U5 and inverting integrator U6 drawsPin ground connection; 4 pins of 4 pins of phase inverter U4,4 pins of phase inverter U5 and inverting integrator U6Meet VDD (negative voltage), 7 pins of phase inverter U4,7 pins and the inverting integrator of phase inverter U57 pins of U6 meet VCC (positive voltage), and the output end signal of second channel phase inverter U5 is-y, and secondThe output of passage inverting integrator U6 is signal y;
Described third channel comprises multiplier A2, and multiplier A2 output is connected to phase inverter by R312 pins of U7, the output signal of resistance R 32 one end and third channel is connected, and resistance R 32 other ends connect2 pins of phase inverter U7,2 pins of phase inverter U7 connect 6 of phase inverter U7 by resistance R 33 and drawPin; 6 pins of phase inverter U7 connect 2 pins of inverting integrator U9, anti-phase integration by resistance R 342 pins of device U9 connect one end of capacitor C 3, and the other end of capacitor C 3 connects 6 of inverting integrator U9Pin; 6 pins of inverting integrator U9 are connected to 2 pins of phase inverter U8 by resistance R 35; Anti-phase2 pin contact resistance R36 one end of device U8, resistance R 36 other ends connect 6 pins of phase inverter U8;The 3 pin ground connection of 3 pins of phase inverter U7,3 pins of inverting integrator U9, phase inverter U8; InsteadIt is (negative that 4 pins of 4 pins of phase device U7,4 pins of inverting integrator U9, phase inverter U8 meet VDDVoltage), 7 pins of phase inverter U7,7 pins of phase inverter integration U9,7 pins of phase inverter U8Meet VCC (positive voltage), the output end signal of third channel phase inverter U8 is-z, the anti-phase integration of third channelThe output of device U9 is signal z.
Described phase inverter U1, phase inverter U2, inverting integrator U3, phase inverter U4, phase inverter U5,Inverting integrator U6, phase inverter U7, phase inverter U8, inverting integrator U9 adopt transport and placing device LM741.
Described multiplier A1, multiplier A2 adopts multiplier AD633.
Of the present utility model is that observable goes out x-y on common oscillograph, x-z, and y-z phasor, has circuit knotStructure is simple, and circuit performance reliably and is easily realized, and is applicable to university's Chaotic Experiment teaching, nonlinear circuit demonstrationDeng, in the field such as information security, communication security, there is important value.
Brief description of the drawings
Fig. 1 is circuit diagram of the present utility model.
Fig. 2 is the x output waveform figure of Fig. 1.
Fig. 3 is the y output waveform figure of Fig. 1.
Fig. 4 is the z output waveform figure of Fig. 1.
Fig. 5 is the x-y output phasor of Fig. 1.
Fig. 6 is the x-z output phasor of Fig. 1.
Fig. 7 is the y-z output phasor of Fig. 1.
Detailed description of the invention
Below in conjunction with drawings and Examples, the utility model is described in detail.
With reference to Fig. 1, a kind of three-dimensional autonomous transition system T chaos circuit, comprises first passage, second channel and theTriple channel, the output signal of first passage feeds back to the input of first passage, as a road input signal,This signal connects the input pin of multiplier A1 in second channel, and the previous stage output of first passage connects the 3rdMultiplier A2 in passage and the input of second channel, the output of second channel also connects the input of third channelIn the input pin of multiplier A2, the output of third channel feeds back to the input of third channel, and the 3rdThe output signal of the previous stage of passage output signal connects the input pin that second channel connects multiplier A1;
Described first passage comprises phase inverter U1, the 2 pin connecting resistance R11 of phase inverter U1, resistance R 12, electricityOne end of resistance R13, the other end of resistance R 11 is connected with the output signal of first passage, another of resistance R 12End is connected with the output signal of second channel, and resistance R 13 other ends connect 6 pins of phase inverter U1, phase inverter6 pins of U1 connect 2 pins of inverting integrator U3 by resistance R 14; Capacitor C 1 one end connects anti-phase integration2 pins of device U3, the other end of capacitor C 1 connects 6 pins of inverting integrator U3,6 of inverting integrator U3Pin is connected to 2 pins of phase inverter U2 by resistance R 15; The 2 pin contact resistance R16 mono-of phase inverter U2End, resistance R 16 other ends connect 6 pins of phase inverter U2; 3 of 3 pins of phase inverter U1, the U2 of phase inverterThe 3 pin ground connection of pin and inverting integrator U3; 4 pins of phase inverter U1,4 pins of phase inverter U2 are with anti-4 pins of phase integral device U3 meet VDD (negative voltage), 7 pins of phase inverter U1,7 pins of phase inverter U2Meet VCC (positive voltage) with 7 pins of inverting integrator U3, the output of the phase inverter U2 of first passage isSignal-x, the output of inverting integrator U3 is signal x;
Described second channel comprises multiplier A1, and multiplier A1 is by resistance R 22 and 2 of phase inverter U4Pin is connected; The output signal of resistance R 21 one end and first passage is connected, resistance R 21 other ends and anti-phase2 pins of the U4 of device are connected, and 2 pins of the U4 of the phase inverter resistance R 23 that was connected connects phase inverter6 pins of U4; 6 pins of phase inverter U4 connect 2 pins of inverting integrator U6 by resistance R 24,2 pins of inverting integrator U6 connect one end of capacitor C 2, and the other end of capacitor C 2 connects anti-phase integration6 pins of device U6; 6 pins of inverting integrator U6 are connected to 2 of phase inverter U5 by resistance R 25Pin; 2 pin contact resistance R26 one end of phase inverter U5, resistance R 26 other ends connect phase inverter U56 pins; 3 of 3 pins of the anti-phase U4 of putting, 3 pins of phase inverter U5 and inverting integrator U6 drawsPin ground connection; 4 pins of 4 pins of phase inverter U4,4 pins of phase inverter U5 and inverting integrator U6Meet VDD (negative voltage), 7 pins of phase inverter U4,7 pins and the inverting integrator of phase inverter U57 pins of U6 meet VCC (positive voltage), and the output end signal of second channel phase inverter U5 is-y, and secondThe output of passage inverting integrator U6 is signal y;
Described third channel comprises multiplier A2, and multiplier A2 output is connected to phase inverter by R312 pins of U7, the output signal of resistance R 32 one end and third channel is connected, and resistance R 32 other ends connect2 pins of phase inverter U7,2 pins of phase inverter U7 connect 6 of phase inverter U7 by resistance R 33 and drawPin; 6 pins of phase inverter U7 connect 2 pins of inverting integrator U9, anti-phase integration by resistance R 342 pins of device U9 connect one end of capacitor C 3, and the other end of capacitor C 3 connects 6 of inverting integrator U9Pin; 6 pins of inverting integrator U9 are connected to 2 pins of phase inverter U8 by resistance R 35; Anti-phase2 pin contact resistance R36 one end of device U8, resistance R 36 other ends connect 6 pins of phase inverter U8;The 3 pin ground connection of 3 pins of phase inverter U7,3 pins of inverting integrator U9, phase inverter U8; InsteadIt is (negative that 4 pins of 4 pins of phase device U7,4 pins of inverting integrator U9, phase inverter U8 meet VDDVoltage), 7 pins of phase inverter U7,7 pins of phase inverter integration U9,7 pins of phase inverter U8Meet VCC (positive voltage), the output end signal of third channel phase inverter U8 is-z, the anti-phase integration of third channelThe output of device U9 is signal z.
Described phase inverter U1, phase inverter U2, inverting integrator U3, phase inverter U4, phase inverter U5,Inverting integrator U6, phase inverter U7, phase inverter U8, inverting integrator U9 adopt transport and placing device LM741.
Described multiplier A1, multiplier A2 adopts multiplier AD633.
In Fig. 1, first passage resistance R 11=R12=51k Ω, R13=R15=R16=10K Ω, R14=1KΩ, C1=100nF; Two passage resistance R 22=5.1K Ω, R21=R23=R25=R26=10K Ω, R24=10KΩ, C2=100nF; Third channel resistance R 31=1K Ω, R32=R33==R34=R35=R36=10K Ω,C3＝100nF；VCC＝15，VDD＝-15V。
The operation principle that the utility model relates to is:
The utility model is different from Lorenz system and Chen system, makes to draw that chaotic waves is more obvious,If this output signal is had to reference value at chaotic secret communication and the anti-field such as crack.
The dimensionless mathematics model that the utility model relates to is as follows:
In formula (1), x, y, z is state variable, a, the parameter that b is equation. Choose a=2.1, c=10, when b=1,System (1) is T chaos system, and now the equation of oscillating circuit of the present invention is:
The circuit of first, second, third passage of the present utility model realized respectively first in formula (2),Second, third function, analog multiplier uses when AD633, the output waveform figure of circuit see Fig. 2, Fig. 3,Fig. 4, the phasor of circuit output is shown in Fig. 5, Fig. 6, Fig. 7, reflected transition system circuit on figureChaotic characteristic, has enriched the type of chaos, for chaos is in secret communication, anti-application in cracking and encryptingReference value is provided.
Claims (3)
1. the autonomous transition system T of a three-dimensional chaos circuit, comprises first passage, second channelAnd third channel, it is characterized in that: the output signal of first passage feeds back to the defeated of first passageEnter end, as a road input signal, this signal connects the input of multiplier A1 in second channel and drawsPin, the multiplier A2 in the previous stage output connection third channel of first passage and second channelInput, the output of second channel also connects the input of the multiplier A2 in the input of third channel and drawsPin, the output of third channel feeds back to the input of third channel, and third channel output signalThe output signal of previous stage connect the input pin that second channel connects multiplier A1;
Described first passage comprises phase inverter U1, the 2 pin connecting resistance R11 of phase inverter U1, electricityOne end of resistance R12, resistance R 13, the other end of resistance R 11 and the output signal of first passage connectConnect, the other end of resistance R 12 is connected with the output signal of second channel, resistance R 13 other endsConnect 6 pins of phase inverter U1,6 pins of phase inverter U1 connect anti-phase long-pending by resistance R 14Divide 2 pins of device U3; Capacitor C 1 one end connects 2 pins of inverting integrator U3, capacitor C 1The other end connects 6 pins of inverting integrator U3, and 6 pins of inverting integrator U3 pass through resistanceR15 is connected to 2 pins of phase inverter U2; 2 pin contact resistance R16 one end of phase inverter U2,Resistance R 16 other ends connect 6 pins of phase inverter U2; 3 pins of phase inverter U1, phase inverterThe 3 pin ground connection of 3 pins of U2 and inverting integrator U3; 4 pins of phase inverter U1, phase inverter4 pins of U2 and 4 pins of inverting integrator U3 meet VDD (negative voltage), phase inverter U1's7 pins of 7 pins, phase inverter U2 and 7 pins of inverting integrator U3 meet VCC (positive voltage),The output of the phase inverter U2 of first passage is signal-x, and the output of inverting integrator U3 isSignal x;
Described second channel comprises multiplier A1, and multiplier A1 is by resistance R 22 and anti-2 pins of phase device U4 are connected; The output signal of resistance R 21 one end and first passage is connected,Resistance R 21 other ends are connected with 2 pins of the U4 of phase inverter, and 2 of the U4 of phase inverter drawsThe pin resistance R 23 that was connected connects 6 pins of phase inverter U4; 6 pins of phase inverter U42 pins that connect inverting integrator U6 by resistance R 24,2 of inverting integrator U6 drawsPin connects one end of capacitor C 2, and the other end of capacitor C 2 connects 6 of inverting integrator U6 and drawsPin; 6 pins of inverting integrator U6 are connected to 2 of phase inverter U5 by resistance R 25 and drawPin; 2 pin contact resistance R26 one end of phase inverter U5, resistance R 26 other ends connect anti-6 pins of phase device U5; 3 pins of anti-phase 3 pins of putting U4, phase inverter U5 and anti-phaseThe 3 pin ground connection of integrator U6; 4 pins of phase inverter U4,4 pins of phase inverter U5Meet VDD (negative voltage) with 4 pins of inverting integrator U6,7 pins of phase inverter U4,7 pins of phase inverter U5 and 7 pins of inverting integrator U6 meet VCC (positive voltage),The output end signal of second channel phase inverter U5 is-y, second channel inverting integrator U6'sOutput is signal y;
Described third channel comprises multiplier A2, and multiplier A2 output connects by R31Receive 2 pins of phase inverter U7, the output signal of resistance R 32 one end and third channel is connected,Resistance R 32 other ends connect 2 pins of phase inverter U7, and 2 pins of phase inverter U7 pass throughResistance R 33 connects 6 pins of phase inverter U7; 6 pins of phase inverter U7 are by resistance R 34Connect 2 pins of inverting integrator U9,2 pins of inverting integrator U9 connect capacitor C 3One end, the other end of capacitor C 3 connects 6 pins of inverting integrator U9; Anti-phase integration6 pins of device U9 are connected to 2 pins of phase inverter U8 by resistance R 35; Phase inverter U82 pin contact resistance R36 one end, resistance R 36 other ends connect 6 of phase inverter U8 and drawPin; 3 of 3 pins of phase inverter U7,3 pins of inverting integrator U9, phase inverter U8Pin ground connection; 4 pins of phase inverter U7,4 pins of inverting integrator U9, phase inverter4 pins of U8 meet VDD (negative voltage), 7 pins of phase inverter U7, phase inverter integration7 pins of U9,7 pins of phase inverter U8 meet VCC (positive voltage), and third channel is anti-The output end signal of phase device U8 is-z that the output of third channel inverting integrator U9 is signalz。
2. the three-dimensional autonomous transition system T chaos circuit of one according to claim 1,It is characterized in that: described phase inverter U1, phase inverter U2, inverting integrator U3, anti-phaseDevice U4, phase inverter U5, inverting integrator U6, phase inverter U7, phase inverter U8, anti-phaseIntegrator U9 adopts transport and placing device LM741.
3. the three-dimensional autonomous transition system T chaos circuit of one according to claim 1,It is characterized in that: described multiplier A1, multiplier A2 adopts multiplier AD633.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107104786A (en) * | 2017-03-29 | 2017-08-29 | 西京学院 | A kind of four-dimensional autonomous continuous chaos tangles circuit |
| CN107566109A (en) * | 2017-10-16 | 2018-01-09 | 中船第九设计研究院工程有限公司 | A kind of three-dimensional chaotic circuit |
| CN110138363A (en) * | 2019-04-12 | 2019-08-16 | 齐鲁理工学院 | A kind of analog circuit of three-dimensional integer contrast display system |
| CN110611560A (en) * | 2019-09-18 | 2019-12-24 | 湘潭大学 | Three-dimensional non-autonomous chaotic model and circuit |
| CN111404660A (en) * | 2020-03-12 | 2020-07-10 | 华东交通大学 | Four-order memristor chaotic signal source circuit |
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2015
- 2015-12-03 CN CN201520995801.6U patent/CN205265706U/en not_active Expired - Fee Related
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107104786A (en) * | 2017-03-29 | 2017-08-29 | 西京学院 | A kind of four-dimensional autonomous continuous chaos tangles circuit |
| CN107566109A (en) * | 2017-10-16 | 2018-01-09 | 中船第九设计研究院工程有限公司 | A kind of three-dimensional chaotic circuit |
| CN107566109B (en) * | 2017-10-16 | 2023-06-13 | 中船第九设计研究院工程有限公司 | Three-dimensional chaotic circuit |
| CN110138363A (en) * | 2019-04-12 | 2019-08-16 | 齐鲁理工学院 | A kind of analog circuit of three-dimensional integer contrast display system |
| CN110611560A (en) * | 2019-09-18 | 2019-12-24 | 湘潭大学 | Three-dimensional non-autonomous chaotic model and circuit |
| CN110611560B (en) * | 2019-09-18 | 2023-09-12 | 湘潭大学 | Three-dimensional non-autonomous chaotic model and circuit |
| CN111404660A (en) * | 2020-03-12 | 2020-07-10 | 华东交通大学 | Four-order memristor chaotic signal source circuit |
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