CN206524843U - One kind deformation Rikitake chaos system analog circuits - Google Patents
One kind deformation Rikitake chaos system analog circuits Download PDFInfo
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- CN206524843U CN206524843U CN201720211048.6U CN201720211048U CN206524843U CN 206524843 U CN206524843 U CN 206524843U CN 201720211048 U CN201720211048 U CN 201720211048U CN 206524843 U CN206524843 U CN 206524843U
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Abstract
One kind deformation Rikitake chaos system analog circuits, it is made up of three passages, the output signal of first passage feeds back to first passage input, and the input of connection second channel, it is used as input signal all the way, the input pin of the multiplier of the previous stage output signal connection second channel of first passage output signal, while being connected with the input pin of the multiplier of third channel；The output of second channel feeds back to the input of second channel as input signal all the way, the signal is also connected with the input pin of third channel multiplier, the input pin of the previous stage output connection first passage multiplier of the signal, while connecting the input of first passage, is used as input signal all the way；The output of third channel feeds back to the input of third channel, while the input pin of second channel multiplier is connected to, while being also connected with the input pin of multiplier in first passage；The signal that the utility model completes deformation Rikitake chaos systems is produced, and circuit structure is simple, and circuit performance is reliable.
Description
Technical field
The utility model is related to chaotic signal technical field, specifically related to a kind of deformation Rikitake chaos systems simulation electricity
Road.
Background technology
The model for the double plate generator that Rikitake in 1958 is proposed first is once as the earliest origin for explaining earth magnetism and ground
The model of polarity inversion phenomenon in the change in long term of magnetic field, be this earth magnetism it is theoretical in need and be addressed the problem of being most difficult to explanation.
In recent years, the model of double plate generator was had application in engineering, and existing document is carried out to the chaotic motion of Rikitake systems
Analysis, and control, but be theoretical proof and checking.
At present, on the one hand, using circuit realiration its Rikitake chaos system, the document then researched and analysed compared with
It is few；On the other hand, with reference to Mechanical ＆ Electrical Combination System, the loss-type coupled dynamos system of proposition is deformation Rikitake chaos systems
Circuit realiration, to research coupling Mechatronic Systems it is particularly important, but a disadvantage is that deformation Rikitake chaos systems because of complexity
It is difficult to.
The content of the invention
In order to overcome the shortcoming of above-mentioned prior art, the purpose of this utility model is to provide a kind of deformation Rikitake chaos
Circuit system, the signal for completing deformation Rikitake chaos systems is produced.
In order to achieve the above object, the technical scheme that the utility model is taken is：
One kind deformation Rikitake chaos system analog circuits, are made up of, the output signal of first passage is anti-three passages
It is fed to first passage input, and the input of connection second channel, as input signal all the way, first passage output signal
The multiplier A2 of previous stage output signal connection second channel input pin, while the input with the multiplier A1 of third channel
Pin is connected；The output of second channel feeds back to the input of second channel as input signal all the way, and the signal is also connected with
Triple channel multiplier A1 input pin, the previous stage output connection first passage multiplier A3 of signal input pin, together
When connect first passage input, be used as input signal all the way；The output of third channel feeds back to the input of third channel, together
When be connected to second channel multiplier A2 input pin, while being also connected with the input pin of multiplier A3 in first passage；
Described first passage includes phase inverter U1, phase inverter U1 2 pin connecting resistance R11, resistance R12, resistance R14,
The resistance R11 other end connects the output signal-x of first passage, resistance the R12 other end connection output signal y, resistance R13
Other end connection multiplier A3 output end；Resistance R14 other ends connection phase inverter U1 6 pins, phase inverter U1 6 pins
Pass through resistance R15 connection inverting integrators U3 2 pins；Inverting integrator U3 2 pins and the connection of electric capacity C1 one end, electric capacity C1
Other end connection inverting integrator U3 6 pins, inverting integrator U3 6 pins pass through the 2 of resistance R16 connection phase inverters U2
Pin；Phase inverter U2 2 pins connection resistance R17 one end, resistance R17 other ends connection phase inverter U2 6 pins；Phase inverter U1
3 pins, the U2 of phase inverter 3 pins and inverting integrator U3 3 pins are grounded；Phase inverter U1 4 pins, phase inverter U2
4 pins and inverting integrator U3 4 pins connect negative voltage VDD, phase inverter U1 7 pins, phase inverter U2 7 pins and anti-phase product
Device U3 7 pins are divided to meet VCC, the phase inverter U2 of first passage output end is signal-x, and inverting integrator U3 output end is
Signal x；
Described second channel includes multiplier A2, and multiplier A2 is connected by resistance R22 with phase inverter U4 2 pins；
The U4 of phase inverter 2 pins and resistance R21, resistance R28, resistance R23 connections, the resistance R21 other end and second channel are anti-phase
Output signal-y the connections of device, the output signal-x connections of resistance the R28 other end and first passage, the resistance R23 other end
Connect phase inverter U4 6 pins；Phase inverter U4 6 pins pass through resistance R24 connection inverting integrators U6 2 pins, anti-phase product
Divide device U6 2 pins connection electric capacity C2 one end, electric capacity C2 other end connection inverting integrator U6 6 pins；Anti-phase integration
2 pins that device U6 6 pins pass through resistance R25 connection phase inverters U5；Phase inverter U5 2 pins connection resistance R26 one end, resistance
R26 other ends connection phase inverter U5 6 pins, phase inverter U4 3 pins, the 3 of phase inverter U5 3 pins and inverting integrator U6
Pin is grounded；4 pins of phase inverter U4 4 pins, phase inverter U5 4 pins and inverting integrator U6 meet negative voltage VDD, anti-phase
7 pins of device U4 7 pins, phase inverter U5 7 pins and inverting integrator U6 meet positive voltage VCC, second channel phase inverter U5
Output end be signal-y, second channel inverting integrator U6 output end is signal y；
Described third channel includes multiplier A3, and multiplier A3 output ends are drawn by the 2 of resistance R34 connection phase inverter U7
Pin, phase inverter U7 2 pins and resistance R35, resistance R36 connections, the resistance R35 other end and third channel inverting integrator
Output signal z connections, the resistance R36 other end and connection phase inverter U7 6 pins；Phase inverter U7 6 pins pass through resistance R37
Inverting integrator U8 2 pins are connected, inverting integrator U8 2 pins connection electric capacity C3 one end, the electric capacity C3 other end connects
Connect inverting integrator U8 6 pins；Phase inverter U7 3 pins are grounded with inverting integrator U8 3 pins；Draw the 4 of phase inverter U7
Pin and inverting integrator U8 4 pins meet negative voltage VDD, and phase inverter U7 7 pins connect positive electricity with inverting integrator U8 7 pins
VCC is pressed, third channel inverting integrator U8 output end is signal z.
Described phase inverter U1, phase inverter U2, inverting integrator U3, phase inverter U4, phase inverter U5, inverting integrator U6,
Phase inverter U7 and inverting integrator U8 uses transport and placing device LM741.
Described multiplier A1, multiplier A2 and multiplier A3 uses multiplier AD633.
The beneficial effects of the utility model：The utility model can observe x-y, x-z, y-z on common oscillograph
Phasor, simple with circuit structure, circuit performance is reliable and easily realizes, it is adaptable to polarity inversion in the change in long term of earth magnetism magnetic field
Visual phenomenon is studied and nonlinear circuit is demonstrated etc..
Brief description of the drawings
Fig. 1 is circuit diagram of the present utility model.
Fig. 2 is Fig. 1 x output waveform figures.
Fig. 3 is Fig. 1 y output waveform figures.
Fig. 4 is Fig. 1 z output waveform figures.
Fig. 5 is Fig. 1 x-y output phasors.
Fig. 6 is Fig. 1 x-z output phasors.
Fig. 7 is Fig. 1 y-z output phasors.
Embodiment
The utility model is described in detail with reference to the accompanying drawings and examples.
Reference picture 1, one kind deformation Rikitake chaos system analog circuits, be made up of three passages, first passage it is defeated
Go out signal and feed back to first passage input, and the input of connection second channel, as input signal all the way, first passage is defeated
Go out the multiplier A2 of the previous stage output signal connection second channel of signal input pin, while the multiplier with third channel
A1 input pin is connected；The output of second channel feeds back to the input of second channel, the signal as input signal all the way
It is also connected with third channel multiplier A1 input pin, the previous stage output connection first passage multiplier A3 of signal input
Pin, while connecting the input of first passage, is used as input signal all the way；The output of third channel feeds back to third channel
Input, while second channel multiplier A2 input pin is connected to, while being also connected with the input of multiplier A3 in first passage
Pin；
Described first passage includes phase inverter U1, phase inverter U1 2 pin connecting resistance R11, resistance R12, resistance R14,
Output signal-the x of the first passage of resistance R11 other end connection, resistance R12 other end connection output signal y, resistance
R13 other end connection multiplier A3 output end；Resistance R14 other ends connection phase inverter U1 6 pins, the 6 of phase inverter U1
2 pins that pin passes through resistance R15 connection inverting integrators U3；Inverting integrator U3 2 pins and the connection of electric capacity C1 one end, electricity
Hold C1 other end connection inverting integrator U3 6 pins, inverting integrator U3 6 pins pass through resistance R16 connection phase inverters
U2 2 pins；Phase inverter U2 2 pins connection resistance R17 one end, resistance R17 other ends connection phase inverter U2 6 pins；Instead
The 3 pins ground connection of phase device U1 3 pins, the U2 of phase inverter 3 pins and inverting integrator U3；It is phase inverter U1 4 pins, anti-phase
Device U2 4 pins and inverting integrator U3 4 pins meet negative voltage VDD, phase inverter U1 7 pins, phase inverter U2 7 pins with
Inverting integrator U3 7 pins meet VCC, and the phase inverter U2 of first passage output end is signal-x, and inverting integrator U3's is defeated
It is signal x to go out end；
Described second channel includes multiplier A2, and multiplier A2 is connected by resistance R22 with phase inverter U4 2 pins；
The U4 of phase inverter 2 pins and resistance R21, resistance R28, resistance R23 connections, the resistance R21 other end and second channel are anti-phase
Output signal-y the connections of device, the output signal-x connections of resistance the R28 other end and first passage, the resistance R23 other end
Connect phase inverter U4 6 pins；Phase inverter U4 6 pins pass through resistance R24 connection inverting integrators U6 2 pins, anti-phase product
Divide device U6 2 pins connection electric capacity C2 one end, electric capacity C2 other end connection inverting integrator U6 6 pins；Anti-phase integration
2 pins that device U6 6 pins pass through resistance R25 connection phase inverters U5；Phase inverter U5 2 pins connection resistance R26 one end, resistance
R26 other ends connection phase inverter U5 6 pins, phase inverter U4 3 pins, the 3 of phase inverter U5 3 pins and inverting integrator U6
Pin is grounded；4 pins of phase inverter U4 4 pins, phase inverter U5 4 pins and inverting integrator U6 meet negative voltage VDD, anti-phase
7 pins of device U4 7 pins, phase inverter U5 7 pins and inverting integrator U6 meet positive voltage VCC, second channel phase inverter U5
Output end be signal-y, second channel inverting integrator U6 output end is signal y；
Described third channel includes multiplier A3, and multiplier A3 output ends are drawn by the 2 of resistance R34 connection phase inverter U7
Pin, phase inverter U7 2 pins and resistance R35, resistance R36 connections, the resistance R35 other end and third channel inverting integrator
Output signal z connections, the resistance R36 other end and connection phase inverter U7 6 pins；Phase inverter U7 6 pins pass through resistance R37
Inverting integrator U8 2 pins are connected, inverting integrator U8 2 pins connection electric capacity C3 one end, the electric capacity C3 other end connects
Connect inverting integrator U8 6 pins；Phase inverter U7 3 pins are grounded with inverting integrator U8 3 pins；Draw the 4 of phase inverter U7
Pin and inverting integrator U8 4 pins meet negative voltage VDD, and phase inverter U7 7 pins connect positive electricity with inverting integrator U8 7 pins
VCC is pressed, third channel inverting integrator U8 output end is signal z.
Described phase inverter U1, phase inverter U2, inverting integrator U3, phase inverter U4, phase inverter U5, inverting integrator U6,
Phase inverter U7 and inverting integrator U8 uses transport and placing device LM741.
Described multiplier A1, multiplier A2 and multiplier A3 uses multiplier AD633.In Fig. 1, first passage resistance
R11=50k Ω, R13=1K Ω, R14=R15=R16=R17=10K Ω, R12=100K Ω, C1=10nF；Second channel
Resistance R21=33K Ω, R22=1K Ω, R22=100K Ω, R23=R24=R25=10K Ω, R26=10K Ω, C2=
10nF；Third channel resistance R34=1k Ω, R34=33k Ω, R35=135k Ω, R36=R37=10K Ω, C3=10nF；
VCC=15, VDD=-15V.
Operation principle of the present utility model is：
The chaotic characteristic of the circuit is extremely complex, is applicable to encryption system, to study in the change in long term of earth magnetism magnetic field
The research of polarity inversion phenomenon provides real model and related data, and involved dimensionless mathematical modeling is as follows：
The dimensionless mathematical modeling that the utility model is related to is as follows：
In formula (1), x, y, z is state variable, a, b, c, and d is the parameter of equation.Choose a=2, b=3, c=1, d=
When 0.75, system (1) is deformation Rikitake chaos systems, and now the equation of oscillating circuit of the present utility model is：
Circuit involved by the utility model is made up of the circuit of first, second, third passage, and first, second, third leads to
The circuit timesharing in road realizes first, second, third function in formula (2).Analog multiplier use AD633 when, circuit it is defeated
Go out oscillogram and see Fig. 2, Fig. 3, Fig. 4, the phasor of circuit output, which is shown on Fig. 5, Fig. 6, Fig. 7, figure, has shown out deformation Rikitake systems
The chaotic characteristic of system, enriches the type of chaos, is chaos applications in chaos cipher and chaos mechanical-electric coupling, generator system
Control provide new thinking.
Claims (3)
1. one kind deformation Rikitake chaos system analog circuits, are made up of three passages, it is characterised in that：First passage it is defeated
Go out signal and feed back to first passage input, and the input of connection second channel, as input signal all the way, first passage is defeated
Go out the multiplier A2 of the previous stage output signal connection second channel of signal input pin, while the multiplier with third channel
A1 input pin is connected；The output of second channel feeds back to the input of second channel, the signal as input signal all the way
It is also connected with third channel multiplier A1 input pin, the previous stage output connection first passage multiplier A3 of signal input
Pin, while connecting the input of first passage, is used as input signal all the way；The output of third channel feeds back to third channel
Input, while second channel multiplier A2 input pin is connected to, while being also connected with the input of multiplier A3 in first passage
Pin；
Described first passage includes phase inverter U1, phase inverter U1 2 pin connecting resistance R11, resistance R12, resistance R14, resistance
Output signal-the x of the first passage of R11 other end connection, resistance R12 other end connection output signal y, resistance R13's
Other end connection multiplier A3 output end；Resistance R14 other ends connection phase inverter U1 6 pins, phase inverter U1 6 pins lead to
Cross resistance R15 connection inverting integrators U3 2 pins；Inverting integrator U3 2 pins and the connection of electric capacity C1 one end, electric capacity C1's
Other end connection inverting integrator U3 6 pins, inverting integrator U3 6 pins draw by the 2 of resistance R16 connection phase inverters U2
Pin；Phase inverter U2 2 pins connection resistance R17 one end, resistance R17 other ends connection phase inverter U2 6 pins；Phase inverter U1's
The 3 pins ground connection of 3 pins, the U2 of phase inverter 3 pins and inverting integrator U3；Phase inverter U1 4 pins, the 4 of phase inverter U2
Pin and inverting integrator U3 4 pins connect negative voltage VDD, phase inverter U1 7 pins, phase inverter U2 7 pins and anti-phase product
Device U3 7 pins are divided to meet VCC, the phase inverter U2 of first passage output end is signal-x, and inverting integrator U3 output end is
Signal x；
Described second channel includes multiplier A2, and multiplier A2 is connected by resistance R22 with phase inverter U4 2 pins；It is anti-phase
The U4 of device 2 pins and resistance R21, resistance R28, resistance R23 connections, the resistance R21 other end and second channel phase inverter
Output signal-y connections, the output signal-x connections of resistance the R28 other end and first passage, resistance R23 other end connection
Phase inverter U4 6 pins；Phase inverter U4 6 pins pass through resistance R24 connection inverting integrators U6 2 pins, inverting integrator
U6 2 pins connection electric capacity C2 one end, electric capacity C2 other end connection inverting integrator U6 6 pins；Inverting integrator U6
6 pins 2 pins that pass through resistance R25 connection phase inverters U5；Phase inverter U5 2 pins connection resistance R26 one end, resistance R26
Other end connection phase inverter U5 6 pins, phase inverter U4 3 pins, the 3 of phase inverter U5 3 pins and inverting integrator U6 are drawn
Pin is grounded；4 pins of phase inverter U4 4 pins, phase inverter U5 4 pins and inverting integrator U6 meet negative voltage VDD, phase inverter
7 pins of U4 7 pins, phase inverter U5 7 pins and inverting integrator U6 meet positive voltage VCC, second channel phase inverter U5's
Output end is signal-y, and second channel inverting integrator U6 output end is signal y；
Described third channel includes multiplier A3, and multiplier A3 output ends connect phase inverter U7 2 pins by resistance R34,
Phase inverter U7 2 pins and resistance R35, resistance R36 connections, the resistance R35 other end and third channel inverting integrator it is defeated
Go out signal z connections, the resistance R36 other end and connection phase inverter U7 6 pins；Phase inverter U7 6 pins are connected by resistance R37
Connect inverting integrator U8 2 pins, inverting integrator U8 2 pins connection electric capacity C3 one end, electric capacity C3 other end connection
Inverting integrator U8 6 pins；Phase inverter U7 3 pins are grounded with inverting integrator U8 3 pins；Phase inverter U7 4 pins
Negative voltage VDD is met with inverting integrator U8 4 pins, phase inverter U7 7 pins connect positive voltage with inverting integrator U8 7 pins
VCC, third channel inverting integrator U8 output end are signal z.
2. a kind of deformation Rikitake chaos system analog circuits according to claim 1, it is characterised in that：Described is anti-
Phase device U1, phase inverter U2, inverting integrator U3, phase inverter U4, phase inverter U5, inverting integrator U6, phase inverter U7 and anti-phase product
Device U8 is divided to use transport and placing device LM741.
3. a kind of deformation Rikitake chaos system analog circuits according to claim 1, it is characterised in that：Described multiplies
Musical instruments used in a Buddhist or Taoist mass A1, multiplier A2 and multiplier A3 use multiplier AD633.
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| CN201720211048.6U CN206524843U (en) | 2017-03-06 | 2017-03-06 | One kind deformation Rikitake chaos system analog circuits |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107566109A (en) * | 2017-10-16 | 2018-01-09 | 中船第九设计研究院工程有限公司 | A kind of three-dimensional chaotic circuit |
| CN107612677A (en) * | 2017-11-10 | 2018-01-19 | 西京学院 | A kind of four hyperchaotic circuits of four-dimension |
| CN110138363A (en) * | 2019-04-12 | 2019-08-16 | 齐鲁理工学院 | A kind of analog circuit of three-dimensional integer contrast display system |
| CN110782755A (en) * | 2019-11-21 | 2020-02-11 | 齐鲁理工学院 | Rikitake hyperchaotic system simulation circuit based on memristor |
-
2017
- 2017-03-06 CN CN201720211048.6U patent/CN206524843U/en not_active Expired - Fee Related
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107566109A (en) * | 2017-10-16 | 2018-01-09 | 中船第九设计研究院工程有限公司 | A kind of three-dimensional chaotic circuit |
| CN107566109B (en) * | 2017-10-16 | 2023-06-13 | 中船第九设计研究院工程有限公司 | Three-dimensional chaotic circuit |
| CN107612677A (en) * | 2017-11-10 | 2018-01-19 | 西京学院 | A kind of four hyperchaotic circuits of four-dimension |
| CN110138363A (en) * | 2019-04-12 | 2019-08-16 | 齐鲁理工学院 | A kind of analog circuit of three-dimensional integer contrast display system |
| CN110782755A (en) * | 2019-11-21 | 2020-02-11 | 齐鲁理工学院 | Rikitake hyperchaotic system simulation circuit based on memristor |
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