CN207184501U - The secondary class Liu hyperchaotic system analog circuits of the dimension of one kind five - Google Patents
The secondary class Liu hyperchaotic system analog circuits of the dimension of one kind five Download PDFInfo
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- CN207184501U CN207184501U CN201720627833.XU CN201720627833U CN207184501U CN 207184501 U CN207184501 U CN 207184501U CN 201720627833 U CN201720627833 U CN 201720627833U CN 207184501 U CN207184501 U CN 207184501U
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Abstract
The secondary class Liu hyperchaotic system analog circuits of the dimension of one kind five, including five passages, first passage output signal feeds back to first passage, connect second channel multiplication simulator simultaneously, all the way input signal of the previous stage output signal of the signal as second channel, while connect the 3rd, Five-channel multiplication simulator；Second channel output signal feeds back to second channel, and the previous stage of the signal exports the input signal all the way as first passage, and connects fourth, fifth passage multiplication simulator；Third channel output signal feeds back to third channel, the previous stage output signal connection second of the signal, four, Five-channel multiplication simulator；The output signal of the signal previous stage is connected to fourth lane multiplier；Fourth lane output signal feeds back to fourth lane, the input signal all the way of the previous stage signal of the signal as first passage；All the way input signal of the previous stage signal of Five-channel output signal as first passage；The utility model circuit is simple, highly reliable.
Description
Technical field
The utility model belongs to the design field of chaos signal generator, more particularly to the secondary class Liu of the dimension of one kind five
Hyperchaotic system analog circuit.
Background technology
Nearest decades, with the development and perfection of theory of chaotic dynamics, the chaos system (low-dimensional) of new especially occurs,
Thinking is provided for the structure of high-dimension chaotic system.Recently, can chaotic secret communication professional committee member in 2016 in Chinese cryptography
Meeting academic conference professor Yu Simin further provides importance and criterion and application of the construction without degeneracy high-dimension chaotic system,
From side it can be seen that structure high-dimension chaotic system has turned into one of the important application in present chaos field and research.Chaos system
System the most direct strategy be chaos circuit realization, for high-dimension chaotic system engineer applied it is critical that circuit realiration with
Control circuit realizes that such circuit provides new thinking for communication security system Complicated design.Higher-dimension be present in prior art
Chaos system because complexity be not easy to design circuit and poor circuit realiration reliability the shortcomings that.
The content of the invention
The shortcomings that in order to overcome above-mentioned prior art, the purpose of this utility model are to provide the secondary class Liu of the dimension of one kind five and surpassed
Chaos system analog circuit, complexity is higher, has stronger chaotic characteristic (spectrum entropy and its height).
In order to achieve the above object, the technical scheme that the utility model is taken is：
The secondary class Liu hyperchaotic system analog circuits of the dimension of one kind five, including first passage, second channel, third channel, the
Four-way and Five-channel；The input that the output signal of first passage feeds back to first passage is used as input signal all the way,
Connect multiplication simulator A1 input pins in second channel simultaneously, the previous stage output signal of the signal as second channel one
Road input signal, while the signal connects two input pins of multiplication simulator A2 in third channel, also connects Five-channel
Multiplication simulator A5 input pin；The output of second channel feeds back to the input of second channel as input signal all the way
End, the previous stage of the signal exports the input signal all the way as first passage, and connects multiplication simulator A3 in fourth lane
Input pin phase, also connect the input pin of multiplication simulator A5 and multiplication simulator A4 in Five-channel；Third channel
Output signal feeds back to the input of third channel, the previous stage output signal connection second of the signal as input signal all the way
Multiplier A1 input pin in passage, and the input pin of multiplication simulator A3 in fourth lane is connected, it is logical also to connect the 5th
Multiplication simulator A4 input pin in road；The output signal of the signal previous stage is connected to the defeated of the multiplier A3 of fourth lane
Enter pin；The output signal of fourth lane feeds back to the input of fourth lane as input signal all the way, the signal it is previous
All the way input signal of the level signal as first passage；The previous stage signal of the output signal of Five-channel is as first passage
Input signal all the way；
Described first passage includes phase inverter U1, phase inverter U1 2 pins connection resistance R11, resistance R12, resistance
R18, resistance R19 and resistance R13, the connection output signal-x of the resistance R11 other end；The resistance R12 other end and output
Signal y is connected；Resistance R18 other ends connection output signal w；Resistance R19 connection output signals u；The resistance R13 other end connects
Connect phase inverter U1 6 pins；2 pins that phase inverter U1 6 pins pass through resistance R14 connection inverting integrators U3；Electric capacity C1 mono-
End connection inverting integrator U3 2 pins, electric capacity C1 other end connection inverting integrator U3 6 pins, inverting integrator U3
6 pins phase inverter U2 2 pins are connected to by resistance R16；Phase inverter U2 2 pins connection resistance R17 one end, resistance
R17 other ends connection phase inverter U2 6 pins；3 pins and inverting integrator U3 of phase inverter U1 3 pins, the U2 of phase inverter
3 pins ground connection；Phase inverter U1 4 pins, 4 pins of phase inverter U2 4 pins and inverting integrator U3 meet negative voltage VDD,
Phase inverter U1 7 pins, phase inverter U2 7 pins and inverting integrator U3 7 pins meet positive voltage VCC, first passage it is anti-
Phase device U2 output signal-x, inverting integrator U3 output signal x；
Described second channel includes phase inverter U4, phase inverter U4 2 pin connecting resistance R21, resistance R22, resistance R23 with
And resistance R24, resistance the R21 other end connection multiplier A1 output end；The resistance R22 other end is connected with output signal x
Connect, the resistance R23 other end is connected with output signal-y；Resistance R24 other ends connection phase inverter U4 6 pins, phase inverter
U4 6 pins connection resistance R25, resistance R25 connection inverting integrators U6 2 pins, inverting integrator U6 2 pins connection
Electric capacity C2 one end, electric capacity C2 other end connection inverting integrator U6 6 pins；Inverting integrator U6 6 pins pass through electricity
Resistance R26 is connected to phase inverter U5 2 pins；Phase inverter U5 2 pins connection resistance R27 one end, the connection of the resistance R27 other ends
Phase inverter U5 6 pins；Phase inverter U4 3 pins, 3 pins of phase inverter U5 3 pins and inverting integrator U6 are grounded；It is anti-phase
Device U4 4 pins, 4 pins of phase inverter U5 4 pins and inverting integrator U6 meet negative voltage VDD, and the 7 of phase inverter U4 draws
Pin, phase inverter U5 7 pins and inverting integrator U6 7 pins connect positive voltage VCC, second channel phase inverter U5 output letter
Number-y, second channel inverting integrator U6 output signal y；
Described third channel includes multiplier A2, and what multiplier A2 output ends were connected to phase inverter U9 by R32 2 draws
Pin, resistance R31 one end connection phase inverter U9 2 pins, resistance R31 other end connection output signal-z；Phase inverter U9 passes through
Resistance R33 connection phase inverters U9 6 pins；Phase inverter U9 6 pins draw by the 2 of resistance R34 connection inverting integrator U11
Pin, inverting integrator U11 2 pins connection electric capacity C3 one end, the 6 of electric capacity C3 other end connection inverting integrator U11 draws
Pin；Inverting integrator U11 6 pins are connected to phase inverter U10 2 pins by resistance R35；Phase inverter U10 2 pins connect
Connecting resistance R36 one end, resistance R36 other ends connection phase inverter U10 6 pins；Phase inverter U9 3 pins, the 3 of phase inverter U10
3 pins of pin and inverting integrator U11 are grounded；Phase inverter U9 4 pins, phase inverter U10 4 pins and inverting integrator
U11 4 pins connect negative voltage VDD, phase inverter U9 7 pins, 7 pins of phase inverter U10 7 pins and inverting integrator U11
Meet positive voltage VCC, third channel phase inverter U10 output signal-z, third channel inverting integrator U11 output signal z；
Described fourth lane includes phase inverter U7, and resistance R41, resistance R42 are connected to phase inverter U7 2 pins, resistance
R41 other end connection output signal-w；Resistance R42 other ends connection multiplier A3 output pin；Phase inverter U7 2 pins
Pass through resistance R43 connection phase inverters U7 6 pins；Phase inverter U7 6 pins pass through resistance R44 connection inverting integrators U12's
2 pins, inverting integrator U12 2 pins connection electric capacity C4 one end, the 6 of electric capacity C4 other end connection inverting integrator U12
Pin；Inverting integrator U12 6 pins are connected to phase inverter U8 2 pins by resistance R45；Phase inverter U8 2 pins connect
Connecting resistance R47 one end, resistance R47 other ends connection phase inverter U8 6 pins；Phase inverter U7 3 pins, the 3 of phase inverter U8 are drawn
Pin is grounded to be grounded with inverting integrator U12 3 pins；Phase inverter U7 4 pins, phase inverter U8 4 pins and anti-phase integration
Device U12 4 pins meet negative voltage VDD, and phase inverter U7 7 pins, the 7 of phase inverter U8 7 pins and phase inverter integration U12 are drawn
Pin meets positive voltage VCC, fourth lane phase inverter U8 output signal-w, fourth lane inverting integrator U12 output signal w；
Described Five-channel includes phase inverter U13, and resistance R51, resistance R52 one end are connected to the 2 of phase inverter U13 and drawn
Pin, resistance R51 other ends connection multiplication simulator A5 output pin；Resistance R52 other ends connection multiplication simulator A4's is defeated
Go out pin；6 pins that phase inverter U13 2 pins pass through resistance R53 connection phase inverters U13；Phase inverter U13 6 pins pass through
Resistance R54 connection inverting integrators U15 2 pins, inverting integrator U15 2 pins connection electric capacity C5 one end, electric capacity C5
Other end connection inverting integrator U15 6 pins；Inverting integrator U15 6 pins are connected to phase inverter by resistance R55
U14 2 pins；Phase inverter U14 2 pins connection resistance R56 one end, the 6 of resistance R56 other ends connection phase inverter U14 draws
Pin；Phase inverter U13 3 pins, phase inverter U14 3 pins ground connection and inverting integrator U15 3 pins are grounded；Phase inverter U13
4 pins, phase inverter U14 4 pins and inverting integrator U15 4 pins meet negative voltage VDD, phase inverter U13 7 pins,
Phase inverter U14 7 pins and phase inverter integration U15 7 pins connect positive voltage VCC, fourth lane phase inverter U14 output
Signal-u, fourth lane inverting integrator U15 output signal u；
Described phase inverter U1, phase inverter U2, inverting integrator U3, phase inverter U4, phase inverter U5, inverting integrator U6,
It is phase inverter U7, phase inverter U8, phase inverter U9, phase inverter U10, inverting integrator U11, inverting integrator U12, phase inverter U13, anti-
Phase device U14 and inverting integrator U15 uses transport and placing device LM741.
Described multiplication simulator A1, multiplication simulator A2, multiplication simulator A3, multiplication simulator A4 and multiplication simulator
A5 uses multiplier AD633.
It is of the present utility model that x-y, x-z, y-z, x-w, y-w, z-w, x-u, y-u can be observed on digital oscilloscope,
Z-u, w-u, phasor, have circuit structure relatively simple, easily realize, the multi-dimension Chaos electric circuit teaching suitable for university's Experiment of Electrical Circuits
And higher-dimension Mechanical ＆ Electrical Combination System model analysis realization etc..
Brief description of the drawings
Fig. 1 is circuit diagram of the present utility model.
Fig. 2 is Fig. 1 x-y output phasors.
Fig. 3 is Fig. 1 x-z output phasors.
Fig. 4 is Fig. 1 y-z output phasors.
Fig. 5 is Fig. 1 x-w output phasors.
Fig. 6 is Fig. 1 y-w output phasors.
Fig. 7 is Fig. 1 z-w output phasors.
Fig. 8 is Fig. 1 x-u output phasors.
Fig. 9 is Fig. 1 y-u output phasors.
Figure 10 is Fig. 1 z-u output phasors.
Figure 11 is Fig. 1 w-u output phasors.
Embodiment
The utility model is described in detail with reference to the accompanying drawings and examples.
Reference picture 1, the secondary class Liu hyperchaotic system analog circuits of the dimension of one kind five, including first passage, second channel, the
Triple channel, fourth lane and Five-channel；The output signal of first passage feeds back to the input of first passage as all the way
Input signal, while multiplication simulator A1 input pins in second channel are connected, the previous stage output signal of the signal is as
The input signal all the way of two passages, while the signal connects two input pins of multiplication simulator A2 in third channel, also connects
Connect the multiplication simulator A5 of Five-channel input pin；The output of second channel feeds back to second as input signal all the way and led to
The input in road, the previous stage of the signal exports the input signal all the way as first passage, and connects multiplication in fourth lane
Simulator A3 input pin phase, also connect the input pin of multiplication simulator A5 and multiplication simulator A4 in Five-channel；
The output signal of third channel feeds back to the input of third channel, the previous stage output letter of the signal as input signal all the way
Multiplier A1 input pin in number connection second channel, and the input pin of multiplication simulator A3 in fourth lane is connected,
Connect the input pin of multiplication simulator A4 in Five-channel；The output signal of the signal previous stage is connected to multiplying for fourth lane
Musical instruments used in a Buddhist or Taoist mass A3 input pin；The output signal of fourth lane feeds back to the input of fourth lane as input signal all the way, should
All the way input signal of the previous stage signal of signal as first passage；The previous stage signal conduct of the output signal of Five-channel
The input signal all the way of first passage；
Described first passage includes phase inverter U1, phase inverter U1 2 pins connection resistance R11, resistance R12, resistance
R18, resistance R19 and resistance R13, the connection output signal-x of the resistance R11 other end；The resistance R12 other end and output
Signal y is connected；Resistance R18 other ends connection output signal w；Resistance R19 connection output signals u；The resistance R13 other end connects
Connect phase inverter U1 6 pins；2 pins that phase inverter U1 6 pins pass through resistance R14 connection inverting integrators U3；Electric capacity C1 mono-
End connection inverting integrator U3 2 pins, electric capacity C1 other end connection inverting integrator U3 6 pins, inverting integrator U3
6 pins phase inverter U2 2 pins are connected to by resistance R16；Phase inverter U2 2 pins connection resistance R17 one end, resistance
R17 other ends connection phase inverter U2 6 pins；3 pins and inverting integrator U3 of phase inverter U1 3 pins, the U2 of phase inverter
3 pins ground connection；Phase inverter U1 4 pins, 4 pins of phase inverter U2 4 pins and inverting integrator U3 meet negative voltage VDD,
Phase inverter U1 7 pins, phase inverter U2 7 pins and inverting integrator U3 7 pins meet positive voltage VCC, first passage it is anti-
Phase device U2 output signal-x, inverting integrator U3 output signal x；
Described second channel includes phase inverter U4, phase inverter U4 2 pin connecting resistance R21, resistance R22, resistance R23 with
And resistance R24, resistance the R21 other end connection multiplier A1 output end；The resistance R22 other end is connected with output signal x
Connect, the resistance R23 other end is connected with output signal-y；Resistance R24 other ends connection phase inverter U4 6 pins, phase inverter
U4 6 pins connection resistance R25, resistance R25 connection inverting integrators U6 2 pins, inverting integrator U6 2 pins connection
Electric capacity C2 one end, electric capacity C2 other end connection inverting integrator U6 6 pins；Inverting integrator U6 6 pins pass through electricity
Resistance R26 is connected to phase inverter U5 2 pins；Phase inverter U5 2 pins connection resistance R27 one end, the connection of the resistance R27 other ends
Phase inverter U5 6 pins；Phase inverter U4 3 pins, 3 pins of phase inverter U5 3 pins and inverting integrator U6 are grounded；It is anti-phase
Device U4 4 pins, 4 pins of phase inverter U5 4 pins and inverting integrator U6 meet negative voltage VDD, and the 7 of phase inverter U4 draws
Pin, phase inverter U5 7 pins and inverting integrator U6 7 pins connect positive voltage VCC, second channel phase inverter U5 output letter
Number-y, second channel inverting integrator U6 output signal y；
Described third channel includes multiplier A2, and what multiplier A2 output ends were connected to phase inverter U9 by R32 2 draws
Pin, resistance R31 one end connection phase inverter U9 2 pins, resistance R31 other end connection output signal-z；Phase inverter U9 passes through
Resistance R33 connection phase inverters U9 6 pins；Phase inverter U9 6 pins draw by the 2 of resistance R34 connection inverting integrator U11
Pin, inverting integrator U11 2 pins connection electric capacity C3 one end, the 6 of electric capacity C3 other end connection inverting integrator U11 draws
Pin；Inverting integrator U11 6 pins are connected to phase inverter U10 2 pins by resistance R35；Phase inverter U10 2 pins connect
Connecting resistance R36 one end, resistance R36 other ends connection phase inverter U10 6 pins；Phase inverter U9 3 pins, the 3 of phase inverter U10
3 pins of pin and inverting integrator U11 are grounded；Phase inverter U9 4 pins, phase inverter U10 4 pins and inverting integrator
U11 4 pins connect negative voltage VDD, phase inverter U9 7 pins, 7 pins of phase inverter U10 7 pins and inverting integrator U11
Meet positive voltage VCC, third channel phase inverter U10 output signal-z, third channel inverting integrator U11 output signal z；
Described fourth lane includes phase inverter U7, and resistance R41, resistance R42 are connected to phase inverter U7 2 pins, resistance
R41 other end connection output signal-w；Resistance R42 other ends connection multiplier A3 output pin；Phase inverter U7 2 pins
Pass through resistance R43 connection phase inverters U7 6 pins；Phase inverter U7 6 pins pass through resistance R44 connection inverting integrators U12's
2 pins, inverting integrator U12 2 pins connection electric capacity C4 one end, the 6 of electric capacity C4 other end connection inverting integrator U12
Pin；Inverting integrator U12 6 pins are connected to phase inverter U8 2 pins by resistance R45；Phase inverter U8 2 pins connect
Connecting resistance R47 one end, resistance R47 other ends connection phase inverter U8 6 pins；Phase inverter U7 3 pins, the 3 of phase inverter U8 are drawn
Pin is grounded to be grounded with inverting integrator U12 3 pins；Phase inverter U7 4 pins, phase inverter U8 4 pins and anti-phase integration
Device U12 4 pins meet negative voltage VDD, and phase inverter U7 7 pins, phase inverter U8 7 pins and phase inverter integrate the 7 of U12
Pin connects positive voltage VCC, fourth lane phase inverter U8 output signal-w, fourth lane inverting integrator U12 output signal
w；
Described Five-channel includes phase inverter U13, and resistance R51, resistance R52 one end are connected to the 2 of phase inverter U13 and drawn
Pin, resistance R51 other ends connection multiplication simulator A5 output pin；Resistance R52 other ends connection multiplication simulator A4's is defeated
Go out pin；6 pins that phase inverter U13 2 pins pass through resistance R53 connection phase inverters U13；Phase inverter U13 6 pins pass through
Resistance R54 connection inverting integrators U15 2 pins, inverting integrator U15 2 pins connection electric capacity C5 one end, electric capacity C5
Other end connection inverting integrator U15 6 pins；Inverting integrator U15 6 pins are connected to phase inverter by resistance R55
U14 2 pins；Phase inverter U14 2 pins connection resistance R56 one end, the 6 of resistance R56 other ends connection phase inverter U14 draws
Pin；Phase inverter U13 3 pins, phase inverter U14 3 pins ground connection and inverting integrator U15 3 pins are grounded；Phase inverter U13
4 pins, phase inverter U14 4 pins and inverting integrator U15 4 pins meet negative voltage VDD, phase inverter U13 7 pins,
Phase inverter U14 7 pins and phase inverter integration U15 7 pins connect positive voltage VCC, fourth lane phase inverter U14 output
Signal-u, fourth lane inverting integrator U15 output signal u；
Described phase inverter U1, phase inverter U2, inverting integrator U3, phase inverter U4, phase inverter U5, inverting integrator U6,
It is phase inverter U7, phase inverter U8, phase inverter U9, phase inverter U10, inverting integrator U11, inverting integrator U12, phase inverter U13, anti-
Phase device U14 and inverting integrator U15 uses transport and placing device LM741.
Described multiplication simulator A1, multiplication simulator A2, multiplication simulator A3, multiplication simulator A4 and multiplication simulator
A5 uses multiplier AD633.
In Fig. 1, resistance R11=1k Ω in first passage, resistance R12=1k Ω, resistance R13=10K Ω, resistance R14=
10K Ω, resistance R16=10K Ω, resistance R17=10K Ω, resistance R18=10K Ω, resistance R19=10K Ω, electric capacity C1=0.1
μF；Resistance R21=1K Ω in second channel, resistance R22=33K Ω, resistance R23=10K Ω, resistance R24=10K Ω, resistance
R25=1K Ω, resistance R26=10K Ω, resistance R27=10K Ω, electric capacity C2=0.1 μ F；Resistance R31=3.3K in third channel
Ω, resistance R32=1K Ω, resistance R34=10K Ω, resistance R35=1K Ω, resistance R36=1K Ω, electric capacity C3=0.1 μ F；The
Resistance R41=5K Ω in four-way, resistance R42=1K Ω, resistance R43=10K Ω, resistance R44=1K Ω, resistance R45=
10K Ω, resistance R47=10K Ω, electric capacity C4=0.1 μ F,；Resistance R51=1K Ω in Five-channel, resistance R52=1K Ω, electricity
Hinder R53=1K Ω, resistance R54=1K Ω, resistance R55=1K Ω, electric capacity C5=0.1 μ F, VCC=15V, VDD=-15V.
Operation principle of the present utility model is：
The secondary class Liu hyperchaotic systems of the dimension of one kind five are the utility model is related to, because the system contains two LE indexes more than 0
Hyperchaotic system is become, higher-dimension make it that the application of the chaos circuit is relatively broad with hyperchaos characteristic.Because of the higher-dimension of system
Property, if using the output signal of the circuit as carrier signal, modulated with echo signal by related algorithm, you can reach communication and protect
Close effect is especially good.The dimensionless mathematical modeling that the utility model is related to is as follows：
In formula (1), x, y, z, w, u is state variable, and a, b, c, d are the parameter of equation, and system (1) is that five dimensions are secondary super
Chaos system, the circuit involved by the utility model are made up of the circuit of first, second, third, the 4th and Five-channel, the
First, second, third, the 4th and Five-channel circuit realize respectively in formula (1) the first, second, third, the 4th and
Five expression formulas.Inverting integrator uses LM741 with phase inverter, and when analog multiplier uses AD633, the phasor of circuit output is shown in
Fig. 2, Fig. 3, Fig. 4, Fig. 5, Fig. 6, Fig. 7, Fig. 8, Fig. 9, Figure 10, Figure 11, Fig. 2 to Figure 11 have reflected that five maintain system analog circuit
Chaotic characteristic, increase the species of chaos in a certain sense, be applied to maintain secrecy for chaos system and what motor model was analyzed grinds
Study carefully and provide new thinking.
Embodiment above is only that preferred embodiment of the present utility model is described, not new to this practicality
The scope of type is defined, on the premise of the utility model design spirit is not departed from, this area ordinary skill technical staff couple
The various modifications and improvement that the technical solution of the utility model is made all should fall into what claims of the present utility model determined
Protection domain.
Claims (3)
1. the secondary class Liu hyperchaotic system analog circuits of the dimension of one kind five, it is characterised in that：Including first passage, second channel,
Triple channel, fourth lane and Five-channel；The output signal of first passage feeds back to the input of first passage as all the way
Input signal, while multiplication simulator A1 input pins in second channel are connected, the previous stage output signal of the signal is as
The input signal all the way of two passages, while the signal connects two input pins of multiplication simulator A2 in third channel, also connects
Connect the multiplication simulator A5 of Five-channel input pin；The output of second channel feeds back to second as input signal all the way and led to
The input in road, the previous stage of the signal exports the input signal all the way as first passage, and connects multiplication in fourth lane
Simulator A3 input pin phase, also connect the input pin of multiplication simulator A5 and multiplication simulator A4 in Five-channel；The
The output signal of triple channel feeds back to the input of third channel, the previous stage output signal of the signal as input signal all the way
The input pin of multiplier A1 in second channel is connected, and connects the input pin of multiplication simulator A3 in fourth lane, is also connected
Connect the input pin of multiplication simulator A4 in Five-channel；The output signal of the signal previous stage is connected to the multiplication of fourth lane
Device A3 input pin；The output signal of fourth lane feeds back to the input of fourth lane as input signal all the way, the letter
Number all the way input signal of the previous stage signal as first passage；The previous stage signal of the output signal of Five-channel is as
The input signal all the way of one passage；
Described first passage includes phase inverter U1, phase inverter U1 2 pins connection resistance R11, resistance R12, resistance R18, electricity
Hinder R19 and resistance R13, the connection output signal-x of the resistance R11 other end；The resistance R12 other end and output signal y phases
Connection；Resistance R18 other ends connection output signal w；Resistance R19 connection output signals u；Resistance R13 other end connection is anti-phase
Device U1 6 pins；2 pins that phase inverter U1 6 pins pass through resistance R14 connection inverting integrators U3；Electric capacity C1 one end connects
Inverting integrator U3 2 pins, electric capacity C1 other end connection inverting integrator U3 6 pins, inverting integrator U3 6 pins
Phase inverter U2 2 pins are connected to by resistance R16；Phase inverter U2 2 pins connection resistance R17 one end, the resistance R17 other ends
Connect phase inverter U2 6 pins；Phase inverter U1 3 pins, the U2 of phase inverter 3 pins and inverting integrator U3 3 pins connect
Ground；Phase inverter U1 4 pins, 4 pins of phase inverter U2 4 pins and inverting integrator U3 meet negative voltage VDD, phase inverter U1's
7 pins, phase inverter U2 7 pins and inverting integrator U3 7 pins meet positive voltage VCC, and the phase inverter U2's of first passage is defeated
Go out signal-x, inverting integrator U3 output signal x；
Described second channel includes phase inverter U4, phase inverter U4 2 pin connecting resistance R21, resistance R22, resistance R23 and electricity
Hinder R24, resistance R21 other end connection multiplier A1 output end；The resistance R22 other end is connected with output signal x, electricity
The resistance R23 other end is connected with output signal-y；Resistance R24 other ends connection phase inverter U4 6 pins, the 6 of phase inverter U4
Pin connects resistance R25, resistance R25 connection inverting integrators U6 2 pins, inverting integrator U6 2 pins connection electric capacity C2
One end, electric capacity C2 other end connection inverting integrator U6 6 pins；Inverting integrator U6 6 pins are connected by resistance R26
It is connected to phase inverter U5 2 pins；Phase inverter U5 2 pins connection resistance R27 one end, resistance R27 other ends connection phase inverter U5
6 pins；Phase inverter U4 3 pins, 3 pins of phase inverter U5 3 pins and inverting integrator U6 are grounded；The 4 of phase inverter U4
Pin, phase inverter U5 4 pins and inverting integrator U6 4 pins meet negative voltage VDD, phase inverter U4 7 pins, phase inverter U5
7 pins and inverting integrator U6 7 pins connect positive voltage VCC, second channel phase inverter U5 output signal-y, second channel
Inverting integrator U6 output signal y；
Described third channel includes multiplier A2, and multiplier A2 output ends are connected to phase inverter U9 2 pins by R32, electricity
Hinder R31 one end connection phase inverter U9 2 pins, resistance R31 other end connection output signal-z；Phase inverter U9 passes through resistance
R33 connection phase inverters U9 6 pins；Phase inverter U9 6 pins connect inverting integrator U11 2 pins by resistance R34, instead
Phase integral device U11 2 pins connection electric capacity C3 one end, electric capacity C3 other end connection inverting integrator U11 6 pins；Instead
Phase integral device U11 6 pins are connected to phase inverter U10 2 pins by resistance R35；Phase inverter U10 2 pins connection resistance
R36 one end, resistance R36 other ends connection phase inverter U10 6 pins；Phase inverter U9 3 pins, phase inverter U10 3 pins with
Inverting integrator U11 3 pins ground connection；Phase inverter U9 4 pins, phase inverter U10 4 pins draw with the 4 of inverting integrator U11
Pin meets negative voltage VDD, and phase inverter U9 7 pins, 7 pins of phase inverter U10 7 pins and inverting integrator U11 connect positive voltage
VCC, third channel phase inverter U10 output signal-z, third channel inverting integrator U11 output signal z；
Described fourth lane includes phase inverter U7, and resistance R41, resistance R42 are connected to phase inverter U7 2 pins, resistance R41's
Other end connection output signal-w；Resistance R42 other ends connection multiplier A3 output pin；Phase inverter U7 2 pins pass through
Resistance R43 connection phase inverters U7 6 pins；Phase inverter U7 6 pins draw by the 2 of resistance R44 connection inverting integrators U12
Pin, inverting integrator U12 2 pins connection electric capacity C4 one end, the 6 of electric capacity C4 other end connection inverting integrator U12 draws
Pin；Inverting integrator U12 6 pins are connected to phase inverter U8 2 pins by resistance R45；Phase inverter U8 2 pins connection electricity
Hinder R47 one end, resistance R47 other ends connection phase inverter U8 6 pins；Phase inverter U7 3 pins, phase inverter U8 3 pins connect
Ground and inverting integrator U12 3 pins are grounded；Phase inverter U7 4 pins, phase inverter U8 4 pins and inverting integrator U12
4 pins meet negative voltage VDD, 7 pins of phase inverter U7 7 pins, phase inverter U8 7 pins and phase inverter integration U12 connect
Positive voltage VCC, fourth lane phase inverter U8 output signal-w, fourth lane inverting integrator U12 output signal w；
Described Five-channel includes phase inverter U13, and resistance R51, resistance R52 one end are connected to phase inverter U13 2 pins, electricity
Hinder R51 other ends connection multiplication simulator A5 output pin；Resistance R52 other ends connection multiplication simulator A4 output is drawn
Pin；6 pins that phase inverter U13 2 pins pass through resistance R53 connection phase inverters U13；Phase inverter U13 6 pins pass through resistance
R54 connection inverting integrators U15 2 pins, inverting integrator U15 2 pins connection electric capacity C5 one end, electric capacity C5's is another
End connection inverting integrator U15 6 pins；Inverting integrator U15 6 pins are connected to the 2 of phase inverter U14 by resistance R55
Pin；Phase inverter U14 2 pins connection resistance R56 one end, resistance R56 other ends connection phase inverter U14 6 pins；Phase inverter
U13 3 pins, phase inverter U14 3 pins ground connection and inverting integrator U15 3 pins are grounded；It is phase inverter U13 4 pins, anti-
Phase device U14 4 pins and inverting integrator U15 4 pins meet negative voltage VDD, phase inverter U13 7 pins, phase inverter U14
7 pins and phase inverter integration U15 7 pins meet positive voltage VCC, fourth lane phase inverter U14 output signal-u, the 4th
Passage inverting integrator U15 output signal u.
A kind of 2. secondary class Liu hyperchaotic system analog circuits of five dimension according to claim 1, it is characterised in that：It is described
Phase inverter U1, phase inverter U2, inverting integrator U3, phase inverter U4, phase inverter U5, inverting integrator U6, phase inverter U7, anti-phase
Device U8, phase inverter U9, phase inverter U10, inverting integrator U11, inverting integrator U12, phase inverter U13, phase inverter U14 with it is anti-phase
Integrator U15 uses transport and placing device LM741.
A kind of 3. secondary class Liu hyperchaotic system analog circuits of five dimension according to claim 1, it is characterised in that：It is described
Multiplication simulator A1, multiplication simulator A2, multiplication simulator A3, multiplication simulator A4 and multiplication simulator A5 use multiplier
AD633。
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| CN110113146A (en) * | 2019-06-04 | 2019-08-09 | 齐鲁理工学院 | A kind of analog circuit of chaotic systems with fractional order |
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| CN110113146A (en) * | 2019-06-04 | 2019-08-09 | 齐鲁理工学院 | A kind of analog circuit of chaotic systems with fractional order |
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