CN108010965A - 一种沟槽mis半导体装置及其制造方法 - Google Patents

一种沟槽mis半导体装置及其制造方法 Download PDF

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CN108010965A
CN108010965A CN201610925659.7A CN201610925659A CN108010965A CN 108010965 A CN108010965 A CN 108010965A CN 201610925659 A CN201610925659 A CN 201610925659A CN 108010965 A CN108010965 A CN 108010965A
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Abstract

本发明提出一种沟槽MIS半导体装置,通过沟槽内下部设置绝缘材料层包裹的第二传导类型半导体材料,将多种超结结构引入到沟槽MIS构中,降低器件电学性能对电荷非平衡的敏感度,优化超结结构导电漏区的电场分布,平滑电场,提高超结结构导电漏区的掺杂浓度。本发明提出一种沟槽MIS半导体装置的制备方法。

Description

一种沟槽MIS半导体装置及其制造方法
技术领域
本发明主要涉及到一种沟槽MIS半导体装置,本发明的半导体装置是功率MOSFET器件的基础结构,本发明还涉及一种沟槽MIS半导体装置的制造工艺。
背景技术
功率MOSFET是多子导电型开关器件,具有输入阻抗高、速度快及正温度系数等优点,使得在开关电源方面的应用得到快速发展,为器件发展的重要趋势。
为了降低功率MOSFET器件的导通电阻,人们将超结结构引入到功率UMOS器件,为了降低制造难度和成本,人们提出在沟槽内小倾斜角度注入形成超结结构,此方法可以将N柱或P柱做的很窄,同时提高N柱或P柱掺杂浓度,同时也带来问题:器件的电学性能对电荷非平衡很敏感,超结结构区域沟槽内的填充及栅沟槽在空间上矛盾。
发明内容
本发明针对上述问题提出,提出一种沟槽MIS半导体装置及其制造方法。
一种沟槽MIS半导体装置,衬底层,为半导体材料;漂移层,为第二导电类型半导体材料,位于衬底层之上;多个沟槽,位于漂移层中,沟槽内壁设置绝缘材料层,沟槽内下部设置第二导电类型半导体材料,沟槽内上部设置导电材料作为栅电极,为高浓度掺杂多晶或金属,所述的沟槽通过两次刻蚀形成,先形成浅沟槽,再形成深沟槽,沟槽上部宽度宽于沟槽下部宽度;多个漏区,位于漂移层中,为第一导电类型半导体材料,临靠沟槽下部侧壁,沟槽侧壁漏区之间为第二导电类型半导体材料,漏区杂质的峰值掺杂浓度大于沟槽侧壁漏区之间为第二导电类型半导体材料掺杂浓度,所述的漏区与漏区之间第二导电类型半导体材料和沟槽内下部第二导电类型半导体材料在反向偏压下形成电荷补偿结构;多个源区,位于漂移层中,为第一传导类型的半导体材料,临靠沟槽上部侧壁;多个体区接触区,位于漂移层表面,为欧姆接触,所述的体区接触区为沟槽结构,位于漂移层表面,领靠源区,沟槽底部为欧姆接触;多个沟道区,位于源区与漏区之间,临靠设置导电材料沟槽,为漂移层中第二导电类型半导体材料,为单个导电类型杂质掺杂,在远离沟槽方向上掺杂浓度逐渐升高,临靠沟槽第二导电类型半导体材料设置轻掺杂区域,沟道区底部高于沟槽内上部导电材料底部。
本发明半导体装置的MIS为沟槽内上部设置导电材料、沟槽内壁设置绝缘材料层和沟道区构成;所述的沟道区为通过在沟槽内生长厚氧化层吸收第二导电类型杂质形成;所述的沟槽内上部导电材料与沟槽内下部设置第二导电类型半导体材料形成沟槽接触,其中包括沟槽内上部导电材料为第一导电类型多晶硅,其中包括沟槽内下部设置第二导电类型多晶硅;所述的半导体装置在源区与栅电极之间设置整流二极管,栅电极到源区为截止,源区到栅电极为导通。
一种沟槽MIS半导体装置的制备方法,包括如下步骤:在衬底层上通过外延生长形成第二传导类型的半导体材料漂移层;在表面形成钝化层,包括为氮化硅层,在待形成沟槽区域表面去除钝化层,进行刻蚀半导体材料,形成浅沟槽;在沟槽内进行氧化,形成半导体材料厚氧化层,干法刻蚀去除沟槽底部氧化层,干法刻蚀半导体材料形成深沟槽;小角度倾斜注入第一导电类型杂质;去除沟槽内厚氧化层,在沟槽内形成绝缘材料层,沟槽内设置第二导电类型半导体材料;去除表面部分钝化层,注入第二导电类型杂质,在表面形成钝化层,去除部分钝化层,注入第一导电类型杂质,进行退火;在器件表面形成钝化层,去除部分钝化层。
本发明的一种沟槽MIS半导体装置,通过沟槽内下部的第二传导类型半导体材料区,并与栅电极相连,将绝缘层隔离超结结构引入到沟槽MOS结构中,使得漏区两侧通过两种电荷补偿方式实现超结结构,有利于形成高掺杂浓度的窄N柱,或者有利于降低器件的电学性能对电荷非平衡的敏感度;本发明的半导体装置,解决了沟槽内电荷补偿半导体材料电势引入与栅电极沟槽空间相互侵占问题;本发明的半导体装置,通过沟槽底部的绝缘材料提高了漏区底部电场,通过栅电极材料低于沟道区降低了漏区顶部峰值电场,以此可提高提高漏区掺杂浓度,或者降低器件的电学性能对电荷非平衡的敏感度;本发明半导体装置通过本身结构和制造特点,设置沟道区为单一杂质掺杂,在远离沟槽方向上掺杂浓度逐渐升高,临靠沟槽第二导电类型半导体材料设置轻掺杂区域,以此降低器件阈值开启压降和沟道区的导通电阻。
附图说明
图1为本发明一种沟槽MIS半导体装置剖面示意图;
图2为本发明第二种沟槽MIS半导体装置剖面示意图;
图3为本发明装置制造第三步中剖面示意图;
图4为本发明装置制造第四步中剖面示意图;
其中,1、衬底层;2、漂移层;3、体区;4、源区;5、绝缘材料层;6、漏区;7、多晶硅导电材料;8、第二导电类型半导体材料;9、氮化硅。
具体实施方式
实施例1
图1示出了本发明一种超结沟槽MIS半导体装置的示意性剖面图,下面结合图1详细说明通过本发明的半导体装置制造功率MOSFET器件。
一种超结沟槽MIS半导体装置如图1所示,包括衬底层1,为N导电类型半导体硅材料,磷原子掺杂浓度为1E19cm-3;漂移层2,位于衬底层1之上,为P传导类型的半导体硅材料,硼原子掺杂浓度为1E16cm-3,厚度为30um;体区3,位于漂移层2之上,为P传导类型的半导体材料,具有硼原子重掺杂接触区;源区4,临靠沟槽和体区3,为磷原子重掺杂N传导类型的半导体材料;绝缘材料层5,为硅材料的氧化物,位于沟槽内壁;漏区6,为N型单晶半导体硅材料,临靠下部沟槽,磷原子掺杂浓度为2E16cm-3;沟槽上下的宽度为3um和2um,沟槽下部之间的间距为4um;N型多晶硅导电材料7,位于沟槽内上部,为高浓度杂质掺杂的多晶半导体材料,第二导电类型半导体材料位于沟槽内下部,为P型多晶硅,P型多晶硅顶端为重掺杂。沟道区,位于源区与漏区之间,临靠多晶硅导电材料7填充的沟槽,为漂移层中第二导电类型半导体材料,为单个导电类型杂质掺杂,在远离沟槽方向上掺杂浓度逐渐升高,临靠沟槽第二导电类型半导体材料设置轻掺杂区域,沟道区底部高于沟槽内上部导电材料7底部。
本实施例的工艺制造流程如下:
第一步,在衬底层1上通过外延生产形成漂移层2;
第二步,在表面淀积生成氮化硅9,在待形成沟槽区域表面去除氮化硅9,进行刻蚀半导体硅材料,形成浅沟槽;
第三步,在沟槽内进行氧化,形成半导体材料厚氧化层,干法刻蚀去除沟槽底部氧化层,干法刻蚀半导体材料形成深沟槽,如图3所示;
第四步,小角度倾斜注入第一导电类型杂质磷原子,如图4所示;
第五步,去除沟槽内厚氧化层,在沟槽内形成绝缘材料层5为二氧化硅,沟槽内设置第二导电类型半导体材料;
第六步,去除表面部分钝化层氮化硅,注入第二导电类型杂质,在表面形成钝化层二氧化硅,去除部分钝化层氮化硅和二氧化硅,露出源区接触区和沟槽内多晶硅,注入第一导电类型杂质,进行退火;
第七步,在器件表面形成二氧化硅,去除部分二氧化硅,如图1所示。
然后在此基础上,淀积金属,然后反刻,为器件引出体源极和栅极。通过背面金属化工艺为器件引出漏极。
实施例2
图2示出了本发明一种无源超结沟槽MOS半导体装置的示意性剖面图,下面结合图2详细说明通过本发明的半导体装置制造功率MOSFET器件。
一种超结沟槽MIS半导体装置如图2所示,包括衬底层1,为N导电类型半导体硅材料,磷原子掺杂浓度为1E19cm-3;漂移层2,位于衬底层1之上,为P传导类型的半导体硅材料,硼原子掺杂浓度为1E16cm-3,厚度为30um;体区3,位于漂移层2表面沟槽底部,为P传导类型的半导体材料,具有硼原子重掺杂接触区;源区4,临靠沟槽和体区3,为磷原子重掺杂N传导类型的半导体材料;绝缘材料层5,为硅材料的氧化物,位于沟槽内壁;漏区6,为N型单晶半导体硅材料,临靠下部沟槽,磷原子掺杂浓度为2E16cm-3;沟槽上下的宽度为3um和2um,沟槽下部之间的间距为4um;N型多晶硅导电材料7,位于沟槽内上部,为高浓度杂质掺杂的多晶半导体材料,第二导电类型半导体材料位于沟槽内下部,为P型多晶硅,P型多晶硅顶端为重掺杂。沟道区,位于源区与漏区之间,临靠多晶硅导电材料7填充的沟槽,为漂移层中第二导电类型半导体材料,为单个导电类型杂质掺杂,在远离沟槽方向上掺杂浓度逐渐升高,临靠沟槽第二导电类型半导体材料设置轻掺杂区域,沟道区底部高于沟槽内上部导电材料7底部。
本实施例的工艺制造流程如下:
第一步,在衬底层1上通过外延生产形成漂移层2;
第二步,在表面淀积生成氮化硅9,在待形成沟槽区域表面去除氮化硅9,进行刻蚀半导体硅材料,形成浅沟槽;
第三步,在沟槽内进行氧化,形成半导体材料厚氧化层,干法刻蚀去除沟槽底部氧化层,干法刻蚀半导体材料形成深沟槽,如图3所示;
第四步,小角度倾斜注入第一导电类型杂质磷原子,如图4所示;
第五步,去除沟槽内厚氧化层,在沟槽内形成绝缘材料层5为二氧化硅,沟槽内设置第二导电类型半导体材料;
第六步,表面形成光刻胶钝化层,刻蚀氮化硅9和半导体材料形成体区接触沟槽,注入第二导电类型杂质,在表面形成钝化层,去除部分钝化层,注入第一导电类型杂质,进行退火;
第七步,在器件表面形成二氧化硅,去除部分二氧化硅,如图2所示。
然后在此基础上,淀积金属,然后反刻,为器件引出体源极和栅极。通过背面金属化工艺为器件引出漏极。
通过上述实例阐述了本发明,同时也可以采用其它实例实现本发明。本发明不局限于上述具体实例,因此本发明由所附权利要求范围限定。

Claims (9)

1.一种沟槽MIS半导体装置,其特征在于:包括:
衬底层,为半导体材料;
漂移层,为第二导电类型半导体材料,位于衬底层之上;多个
沟槽,位于漂移层中,沟槽内壁设置绝缘材料层,沟槽内下部设置第二导电类型半导体材料,沟槽内上部设置导电材料作为栅电极,为高浓度掺杂多晶或金属;多个
漏区,位于漂移层中,为第一导电类型半导体材料,临靠沟槽下部侧壁,沟槽侧壁漏区之间为第二导电类型半导体材料,漏区杂质的峰值掺杂浓度大于沟槽侧壁漏区之间为第二导电类型半导体材料掺杂浓度;多个
源区,位于漂移层中,为第一传导类型的半导体材料,临靠沟槽上部侧壁;多个
体区接触区,位于漂移层表面,为欧姆接触;多个
沟道区,位于源区与漏区之间,临靠设置导电材料沟槽,为漂移层中第二导电类型半导体材料,为单个导电类型杂质掺杂,在远离沟槽方向上掺杂浓度逐渐升高,临靠沟槽第二导电类型半导体材料设置轻掺杂区域,沟道区底部高于沟槽内上部导电材料底部。
2.如权利要求1所述的半导体装置,其特征在于:所述的MIS为沟槽内上部设置导电材料、沟槽内壁设置绝缘材料层和沟道区构成。
3.如权利要求1所述的半导体装置,其特征在于:所述的沟槽通过两次刻蚀形成,先形成浅沟槽,再形成深沟槽,沟槽上部宽度宽于沟槽下部宽度。
4.如权利要求1所述的半导体装置,其特征在于:所述的漏区与沟槽内下部第二导电类型半导体材料和漏区之间第二导电类型半导体材料在反向偏压下形成电荷补偿结构。
5.如权利要求1所述的半导体装置,其特征在于:所述的体区接触区为沟槽结构,位于漂移层表面,领靠源区,沟槽底部为欧姆接触。
6.如权利要求1所述的半导体装置,其特征在于:所述的沟道区为通过在沟槽内生长厚氧化层吸收第二导电类型杂质形成。
7.如权利要求1所述的层结构,其特征在于:所述的沟槽内上部导电材料与沟槽内下部设置第二导电类型半导体材料形成欧姆接触,其中包括沟槽内上部导电材料为第一导电类型多晶硅,其中包括沟槽内下部设置第二导电类型多晶硅。
8.如权利要求1所述的层结构,其特征在于:所述的半导体装置在源区与栅电极之间设置整流二极管,包括栅电极到源区为截止,源区到栅电极为导通。
9.一种沟槽MIS半导体装置的制备方法,其特征在于:包括如下步骤:
1)在衬底层上通过外延生长形成第二传导类型的半导体材料漂移层;
2)在表面形成钝化层,包括为氮化硅层,在待形成沟槽区域表面去除钝化层,进行刻蚀半导体材料,形成浅沟槽;
3)在沟槽内进行氧化,形成半导体材料厚氧化层,干法刻蚀去除沟槽底部氧化层,干法刻蚀半导体材料形成深沟槽;
4)小角度倾斜注入第一导电类型杂质;
5)去除沟槽内厚氧化层,在沟槽内形成绝缘材料层,沟槽内设置第二导电类型半导体材料;
6)去除表面部分钝化层,注入第二导电类型杂质,形成体区接触区,在表面形成钝化层,去除部分钝化层,露出源区接触区和沟槽内栅电极材料,注入第一导电类型杂质,进行退火;
7)在器件表面形成钝化层,去除部分钝化层。
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