CN108010962A - 具有高特征频率-击穿电压优值的SOI SiGe异质结双极晶体管 - Google Patents
具有高特征频率-击穿电压优值的SOI SiGe异质结双极晶体管 Download PDFInfo
- Publication number
- CN108010962A CN108010962A CN201711227122.4A CN201711227122A CN108010962A CN 108010962 A CN108010962 A CN 108010962A CN 201711227122 A CN201711227122 A CN 201711227122A CN 108010962 A CN108010962 A CN 108010962A
- Authority
- CN
- China
- Prior art keywords
- layer
- collecting zone
- breakdown voltage
- merit
- thickness
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 229910000577 Silicon-germanium Inorganic materials 0.000 title claims abstract description 8
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 23
- 239000001301 oxygen Substances 0.000 claims abstract description 23
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 23
- 229910052681 coesite Inorganic materials 0.000 claims description 11
- 229910052906 cristobalite Inorganic materials 0.000 claims description 11
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 11
- 229920005591 polysilicon Polymers 0.000 claims description 11
- 239000000377 silicon dioxide Substances 0.000 claims description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 11
- 229910052682 stishovite Inorganic materials 0.000 claims description 11
- 229910052905 tridymite Inorganic materials 0.000 claims description 11
- 239000000758 substrate Substances 0.000 claims description 9
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 4
- 238000002955 isolation Methods 0.000 claims description 4
- 238000000926 separation method Methods 0.000 claims description 3
- 239000013078 crystal Substances 0.000 claims description 2
- 230000015556 catabolic process Effects 0.000 abstract description 13
- 230000005684 electric field Effects 0.000 abstract description 6
- 241000033695 Sige Species 0.000 description 51
- 238000010586 diagram Methods 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 230000010355 oscillation Effects 0.000 description 3
- 238000004891 communication Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 229920002472 Starch Polymers 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 235000019698 starch Nutrition 0.000 description 1
- 239000008107 starch Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/737—Hetero-junction transistors
- H01L29/7371—Vertical transistors
- H01L29/7378—Vertical transistors comprising lattice mismatched active layers, e.g. SiGe strained layer transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
- H01L29/0623—Buried supplementary region, e.g. buried guard ring
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Bipolar Transistors (AREA)
Abstract
本发明公开了一种具有高特征频率‑击穿电压优值的SOI SiGe异质结双极晶体管。所述晶体管采用薄的N+埋层结构来显著提高N‑集电区内靠近埋氧层一侧的电子浓度，从而通过减小器件的集电区串联电阻来降低集电结空间电荷区延迟时间，达到提高器件特征频率的目的。所述晶体管采用p型超结层结构来改善集电结空间电荷区的电场分布，使得集电结空间电荷区电场分布趋于平缓，从而可以降低峰值电子浓度，抑制碰撞电离，达到提高器件击穿电压的目的。与常规的功率异质结双极晶体管相比，同时兼顾了器件的高频特性和高击穿特性，从而保持了高的特征频率‑击穿电压优值(fT×BVCEO)，可有效拓展功率异质结双极晶体管在射频和微波功率领域的应用。
Description
技术领域
本发明涉及SOI硅锗(SiGe)异质结双极晶体管，特别是应用于射频/微波通信、无线局域网和数模混合信号电路等具有高特征频率-击穿电压优值的SOI SiGe异质结双极晶体管。
背景技术
随着第四代SiGe工艺的全面发展，现今的SiGe BiCMOS技术已能够实现器件的全介质隔离，从而达到减小衬底寄生电容，消除寄生衬底晶体管,提高SiGe HBT高频特性的目的,也使得SOI SiGe异质结双极晶体管可广泛应用于射频/微波通信、超高速集成电路、无线局域网和雷达等射频和微波功率领域。
图1(a)示出了常规SOI SiGe HBT纵向剖面示意图，主要由衬底(10)、埋氧层(11)、N-集电区(12)、SiGe基区(16)和发射区(18)组成。图1(b)示出了常规SOI SiGe HBT掺杂浓度分布图。可以看出，埋氧层(11)的引入使得器件N-集电区(12)内靠近埋氧层(11)一侧的电子浓度下降，器件的集电区串联电阻增大，虽可略有提高器件的击穿电压，但会造成特征频率的大幅下降。为了改善埋氧层(11)对特征频率的影响，可采用增加N-集电区(12)掺杂浓度的方法。但是，增加N-集电区(12)掺杂浓度又会减小集电结空间电荷区宽度，最终导致器件击穿电压的大幅下降。
可见，常规的SOI SiGe HBT无法同时兼顾高频特性和高击穿特性，不利于拓展其在高频大功率领域的应用。如何设计一种兼顾优异的高频特性和高击穿特性的微波功率SOI SiGe HBT具有重要的理论和实际意义。
发明内容
本发明公开了一种具有高特征频率-击穿电压优值的SOI SiGe异质结双极晶体管。
本发明的一种具有高特征频率-击穿电压优值的SOI SiGe异质结双极晶体管，其特征在于：包括衬底、埋氧层、N+埋层、N-集电区、p型超结层、SiGe基区和发射区。
图2(a)示出了本发明的一种具有高特征频率-击穿电压优值的SOI SiGe异质结双极晶体管的纵向剖面结构，其特征在于：包括衬底(10)、埋氧层(11)、N+埋层(121)、N-集电区(12)、p型超结层(123)、SiGe基区(16)、发射区(18)。其中在所述发射区(18)的两侧设置有由SiO2层围成的侧墙(19)，多晶硅层(20)位于所述由SiO2层围成的侧墙(19)中并且与所述发射区(18)相接触，所述多晶硅层(20)上表面引出发射极电极(21)；SiO2层所围侧墙(19)的下表面一侧设置有多晶硅层(17)并与所述SiGe基区(16)相接触，所述多晶硅层(17)上表面一侧引出基极电极(22)；所述多晶硅层(17)正下方且位于所述SiGe基区(16)的两侧设置有SiO2隔离层(15)；在外集电区(14)上表面一侧引出集电极电极(23)，器件两侧设置浅槽隔离(13)结构。所述晶体管结构是沿发射区(18)中心位置的纵向方向呈轴对称。
所述埋氧层(11)位于衬底(10)正上方由SiO2层构成，其厚度介于50nm到100nm之间。
所述浅槽隔离(13)结构位于埋氧层(11)正上方，且与外集电区(14)相邻，其厚度介于130nm到160nm之间。
所述薄的N+埋层位于N-集电区正下方，且与埋氧层相邻，同时所述N+埋层上表面与SiGe基区下表面相距130nm至150nm。其中薄的N+埋层的引入增加了N-集电区内靠近埋氧层一侧的电子浓度，减小了器件的集电区串联电阻，从而降低了集电结空间电荷区延迟时间，达到改善特征频率的目的。但是随着N-集电区内靠近埋氧层一侧的电子浓度的增加，集电结空间电荷宽度也会随之减小，进而使得器件的击穿电压大幅下降。
因此，本发明进一步在集电结空间电荷区内引入一层平行于N+埋层的p型超结层结构。所述p型超结层通过与两侧相邻的N-掺杂半导体层相互耗尽而引入电子加速电场，改善集电区的电场分布。与常规SOI SiGe HBT相比，所述晶体管的集电结空间电荷区内载流子碰撞电离率得以降低，从而减少了单位距离内因碰撞而产生的载流子数量，有利于器件击穿电压BVCEO的提高。
图2(b)示出了本发明的一种具有高特征频率-击穿电压优值的SOI SiGe异质结双极晶体管的掺杂浓度分布图。可以看出，薄的N+埋层位于N-集电区正下方，其掺杂浓度分布呈高斯分布且从N-集电区一侧向埋氧层一侧逐渐增加，从而增加了N-集电区内靠近埋氧层一侧的电子浓度，达到提高器件特征频率的目的。p型超结层位于N-集电区中的集电结空间电荷区内部，其掺杂浓度小于或等于N-集电区的掺杂浓度。所述p型超结层通过与两侧相邻的N-掺杂半导体层相互耗尽，达到提高击穿电压的目的。
与常规SOI SiGe异质结双极晶体管相比，本发明所述兼具N+埋层结构和p型超结层结构的SOI SiGe异质结双极晶体管的特征频率和击穿电压均得到提高，从而器件获得了高的特征频率-击穿电压优值，拓展了器件的高频大功率工作范围。
附图说明
结合附图所进行的下列描述，可进一步理解本发明的目的和优点。在这些附图中：
图1(a)示例了常规SOI SiGe HBT纵向剖面示意图；
图1(b)示例了常规SOI SiGe HBT掺杂浓度分布图；
图2(a)示例了本发明实施例纵向剖面示意图；
图2(b)示例了本发明实施例掺杂浓度分布图；
图3示例了本发明实施例对器件集电结空间电荷区载流子碰撞电离率的改善；
图4示例了本发明实施例对器件击穿电压BVCEO的改善；
图5示例了本发明实施例对器件电子浓度的改善；
图6示例了本发明实施例对器件特征频率的改善；
图7示例了本发明实施例对器件最大振荡频率的改善。
具体实施方式
本发明实施例以单指SOI SiGe HBT为例，对本发明内容进行具体表述。本发明涉及领域并不限制于此。
实施示例：
本发明实施例公开的具有高特征频率-击穿电压优值的SOI SiGe HBT，其同时具有薄的N+埋层结构和p型超结层结构。
图2(a)示例了本发明实施例的纵向剖面示意图，其中包括N+掺杂的硅(Si)衬底(10)，厚度为300nm，其掺杂浓度为3×1020cm-3；埋氧层(11)，厚度为50nm；N-掺杂的硅(Si)集电区(12)，厚度为150nm，掺杂浓度为3×1017cm-3；N+掺杂的硅(Si)埋层(121)，厚度为10nm，其掺杂浓度为1×1019cm-3；p型超结层(123)，厚度为10nm，其掺杂浓度为3×1017cm-3；器件两侧的浅槽隔离(13)，采用SiO2层结构，其厚度为160nm；N+掺杂的外集电区(14)，厚度为150nm，其掺杂浓度为5×1019cm-3；隔离层SiO2层(15),厚度为25nm；P+掺杂的硅锗(SiGe)基区(16)，厚度为25nm，均匀Ge组分x为0.25，其掺杂浓度为1×1019cm-3；P+掺杂的多晶硅(PolySi)层(17)，其掺杂浓度为5×1019cm-3，厚度为40nm；N+掺杂的硅(Si)发射区(18)，厚度为10nm，其掺杂浓度为1×1021cm-3，N+掺杂的多晶硅层(20)，其掺杂浓度为1×1021cm-3。
为提高器件的频率特性及功率处理能力，本发明实施例在常规SOI SiGe HBT集电区结构的基础上，引入一层薄的N+埋层结构和p型超结层结构。其中，本发明实施例所述N+埋层(121)位于N-集电区(12)正下方，且与埋氧层(11)相邻，同时所述N+埋层(121)上表面与SiGe基区(16)下表面相距150nm。N+埋层的厚度d3＝10nm，掺杂浓度为1×1019cm-3。具体地，本发明实施例的集电结空间电荷区(122)的厚度为d1，N-集电区的厚度为d2，N+埋层的厚度为d3，常规SOI SiGe HBT中N-集电区(12)的厚度为d，且有d1<d2，d2+d3＝d。
同时，本发明实施例所述p型超结层(123)位于N-集电区(12)中的集电结空间电荷区(122)内部，且平行于所述N+埋层(121)，所述p型超结层(123)掺杂浓度等于所述N-集电区(12)的掺杂浓度。具体地，本发明实施例的p型超结层厚度为10nm，掺杂浓度为3×1017cm-3，且所述p型超结层(123)与所述N+埋层(121)厚度相同。
图2(b)示出了具有高特征频率-击穿电压优值的SOI SiGe异质结双极晶体管的掺杂浓度分布。可以看出，本发明实施例所述N+埋层的掺杂浓度呈高斯分布且从N-集电区一侧向埋氧层一侧逐渐增加，并在靠近埋氧层一侧达到峰值浓度。
当器件处于工作状态时，N+埋层的引入能够显著增加N-集电区内靠近埋氧层一侧的电子浓度，减小器件的集电区串联电阻。
由SOI SiGe HBT的集电结空间电荷区渡越时间τcb,SOI SiGe表达式可知：
引入N+埋层所引起集电区串联电阻rc的减小，使得器件的τcb,SOISiGe下降，进而提高了器件的特征频率。
同时，本发明实施例所述p型超结层的掺杂浓度与N-集电区掺杂浓度相等。p型超结层的引入可有效改善集电结空间电荷区内的电场分布。这是因为，一方面p型超结层与靠近基区一侧的N-掺杂半导体层相互耗尽，将产生与集电结内建电场方向相反的电子减速电场；另一方面p型超结层与靠近N+埋层一侧的N-掺杂半导体层相互耗尽，将产生与集电结内建电场方向相同的电子加速电场。与同等条件下的常规SOI SiGe HBT相比，本发明实施例中的集电结空间电荷区内的电场分布更加平缓，进而可有效降低峰值电子温度，减少单位距离内因碰撞而产生的载流子数量，使得集电极-发射极间击穿电压BVCEO得以显著提高。
图3示例了本发明实施例集电结空间电荷区载流子碰撞电离率αi随着器件纵向(Y方向)变化的关系曲线图，并与常规SOI SiGe HBT进行比较。可以看出，与常规SOI SiGeHBT相比，本发明实施例集电结空间电荷区内载流子碰撞电离率的峰值降低了312.8cm-1，改善达48.3％，因此减少了单位距离内因碰撞而产生的载流子数量，从而使击穿电压BVCEO能够得到显著提高。
图4示例了本发明实施例的基极电流IB与工作电压VCE的关系曲线，并与常规SOISiGe HBT进行了比较。可以看出，本发明实施例的集电极-发射极间击穿电压BVCEO为4.55V，与常规的SOI SiGe HBT相比，本发明实施例的BVCEO提高了0.85V，改善达23.0％。
图5示例了本发明实施例的电子浓度随着器件纵向(Y方向)变化的关系曲线图，并与常规SOI SiGe HBT进行了比较。可以看出，与常规SOI SiGe HBT相比，本发明实施例中集电区电子浓度显著上升，而在p型超结处电子浓度稍有下降。
图6示例了本发明实施例的特征频率fT随集电极电流IC变化的关系曲线图，并与常规SOI SiGe HBT进行比较。可以看出，与常规SOI SiGe HBT相比，本发明实施例的特征频率提高了9.9GHz，改善达10.3％。
图7示例了本发明实施例的最大振荡频率fmax随集电极电流IC变化的关系曲线图，并与常规SOI SiGe HBT进行比较。可以看出，与常规SOI SiGe HBT相比，本发明实施例的最大振荡频率提高了12.1GHz，改善达8.3％。
表1示例了本发明实施例的主要性能参数，并与常规SOI SiGe HBT进行比较。可以看出，本发明实施例的特征频率-击穿电压优值fT×BVCEO为487.6GHz-V，与常规SOI SiGeHBT相比，本发明实施例的fT×BVCEO提高了135.4GHz-V，改善达38.4％。
表1两种SOI SiGe HBT的主要性能参数
上述结果均显示了本发明实施例的优越性，本发明对设计和制造一种具有高特征频率-击穿电压优值的可在高频大功率下稳定工作的SOI SiGe HBT具有重要的理论和实际意义。
Claims (1)
1.一种具有高特征频率-击穿电压优值的SOI SiGe异质结双极晶体管，其特征在于：
包括衬底(10)、埋氧层(11)、N+埋层(121)、N-集电区(12)、p型超结层(123)、SiGe基区(16)、发射区(18)；其中在所述发射区(18)的两侧设置有由SiO2层围成的侧墙(19)，多晶硅层(20)位于所述由SiO2层围成的侧墙(19)中并且与所述发射区(18)相接触，所述多晶硅层(20)上表面引出发射极电极(21)；SiO2层所围侧墙(19)的下表面一侧设置有多晶硅层(17)并与所述SiGe基区(16)相接触，所述多晶硅层(17)上表面一侧引出基极电极(22)；所述多晶硅层(17)正下方且位于所述SiGe基区(16)的两侧设置有SiO2隔离层(15)；在外集电区(14)上表面一侧引出集电极电极(23)，器件两侧设置浅槽隔离(13)结构；所述晶体管结构是沿发射区(18)中心位置的纵向方向呈轴对称；
所述埋氧层(11)位于衬底(10)正上方由SiO2层构成，其厚度介于50nm到100nm之间；
所述浅槽隔离(13)结构位于埋氧层(11)正上方，且与外集电区(14)相邻，其厚度介于130nm到160nm之间；
所述N+埋层(121)位于N-集电区(12)正下方，且与埋氧层(11)相邻，同时所述N+埋层(121)上表面与SiGe基区(16)下表面相距130nm至150nm；
所述p型超结层(123)位于N-集电区(12)中的集电结空间电荷区(122)内部，且平行于所述N+埋层(121)，所述p型超结层(123)掺杂浓度小于或等于所述N-集电区(12)的掺杂浓度；
所述p型超结层(123)与所述N+埋层(121)厚度相同，且厚度均不超过30nm。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711227122.4A CN108010962B (zh) | 2017-11-29 | 2017-11-29 | 具有高特征频率-击穿电压优值的SOI SiGe异质结双极晶体管 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711227122.4A CN108010962B (zh) | 2017-11-29 | 2017-11-29 | 具有高特征频率-击穿电压优值的SOI SiGe异质结双极晶体管 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN108010962A true CN108010962A (zh) | 2018-05-08 |
| CN108010962B CN108010962B (zh) | 2020-06-19 |
Family
ID=62054850
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201711227122.4A Active CN108010962B (zh) | 2017-11-29 | 2017-11-29 | 具有高特征频率-击穿电压优值的SOI SiGe异质结双极晶体管 |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108010962B (zh) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109742138A (zh) * | 2019-01-02 | 2019-05-10 | 北京工业大学 | 具有低温度敏感性的SOI SiGe异质结双极晶体管 |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1512595A (zh) * | 2002-12-24 | 2004-07-14 | 国际商业机器公司 | 具有多数载流子累积层作为子集电极的双极晶体管 |
| US20070278539A1 (en) * | 2006-06-02 | 2007-12-06 | Agere Systems Inc. | Junction field effect transistor and method for manufacture |
-
2017
- 2017-11-29 CN CN201711227122.4A patent/CN108010962B/zh active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1512595A (zh) * | 2002-12-24 | 2004-07-14 | 国际商业机器公司 | 具有多数载流子累积层作为子集电极的双极晶体管 |
| US20070278539A1 (en) * | 2006-06-02 | 2007-12-06 | Agere Systems Inc. | Junction field effect transistor and method for manufacture |
Non-Patent Citations (2)
| Title |
|---|
| PRASANNA KUMAR MISRA等: ""Epilayer Optimization of NPN SiGe HBT with n+ Buried Layer Compatible With Fully Depleted SOI CMOS Technology"", 《JORUNAL OF SEMICONDUTOR TECHNOLOGY AND SCIENCE》 * |
| 金冬月等: ""具有高频高压大电流优值的超结集电区SiGe HBT"", 《北京工业大学学报》 * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109742138A (zh) * | 2019-01-02 | 2019-05-10 | 北京工业大学 | 具有低温度敏感性的SOI SiGe异质结双极晶体管 |
| CN109742138B (zh) * | 2019-01-02 | 2022-12-16 | 北京工业大学 | 具有低温度敏感性的SOI SiGe异质结双极晶体管 |
Also Published As
| Publication number | Publication date |
|---|---|
| CN108010962B (zh) | 2020-06-19 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105742346B (zh) | 双分裂沟槽栅电荷存储型rc-igbt及其制造方法 | |
| US7566921B2 (en) | Silicon germanium emitter | |
| CN110504308B (zh) | 一种高速低损耗的多槽栅高压功率器件 | |
| CN108649067B (zh) | 一种太赫兹SOI复合应变Si/SiGe异质结双极晶体管及制备方法 | |
| US11322595B2 (en) | Heterojunction bipolar transistor and preparation method thereof | |
| CN109192771B (zh) | 一种电荷存储型绝缘栅双极型晶体管及其制备方法 | |
| CN108630748A (zh) | 全平面太赫兹复合应变Si/SiGe异质结双极晶体管及制备方法 | |
| CN108231878A (zh) | 一种双向沟槽栅电荷存储型igbt及其制作方法 | |
| CN109065608B (zh) | 一种横向双极型功率半导体器件及其制备方法 | |
| CN108054203B (zh) | 一种绝缘体上硅锗衬底的异质结双极晶体管及其制造方法 | |
| CN108010962A (zh) | 具有高特征频率-击穿电压优值的SOI SiGe异质结双极晶体管 | |
| US8546850B2 (en) | Superjunction collectors for transistors and semiconductor devices | |
| CN114975612A (zh) | 具有低电磁干扰噪声的SiC沟槽栅IGBT器件及制备方法 | |
| CN109830528A (zh) | 锗硅hbt器件及制造方法 | |
| CN110556420B (zh) | 一种掺杂浓度可调的横向SiGe异质结双极晶体管 | |
| Avenier et al. | Investigation of fully-and partially-depleted self-aligned SiGeC HBTs on thin film SOI | |
| CN103137676A (zh) | 一种锗硅异质结双极晶体管及其制造方法 | |
| CN113488540A (zh) | 一种具有垂直场板保护的SiC基槽栅MOSFET结构 | |
| Wang et al. | Novel Design of SOI SiGe HBTs with High Johnson's Figure-of-Merit | |
| Rucker et al. | Integration of high-performance SiGe: C HBTs with thin-film SOI CMOS | |
| CN107731906B (zh) | 一种多指发射极SiGe HBT器件 | |
| CN211182211U (zh) | 一种NPN型横向GaN/SiGe HBT器件结构 | |
| CN103178086B (zh) | 一种SiGe HBT工艺中的VPNP器件及其制造方法 | |
| Onai et al. | An NPN 30 GHz, PNP 32 GHz f/sub T/complementary bipolar technology | |
| Li et al. | Novel power MOS devices with SiGe/Si heterojunctions |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |