CN107993951B - Method for quickly positioning short circuit of three-dimensional memory array area - Google Patents
Method for quickly positioning short circuit of three-dimensional memory array area Download PDFInfo
- Publication number
- CN107993951B CN107993951B CN201711165507.2A CN201711165507A CN107993951B CN 107993951 B CN107993951 B CN 107993951B CN 201711165507 A CN201711165507 A CN 201711165507A CN 107993951 B CN107993951 B CN 107993951B
- Authority
- CN
- China
- Prior art keywords
- failure
- tested
- sample
- word line
- tungsten plug
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Tests Of Electronic Circuits (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Sampling And Sample Adjustment (AREA)
Abstract
The invention provides a method for quickly positioning a short circuit of a three-dimensional memory array area, which comprises the following steps: processing a sample to be tested to a tungsten plug layer; marking the failure block of the processed sample to be tested by using a focused ion beam machine; applying a certain voltage to the tungsten plug in the step area through the nanodot needle platform to find out a failure path between the word line layer and the array area or between the word line layer and the source electrode; leading out a circuit at a tungsten plug position of a step area corresponding to the failed word line layer by using a focused ion beam machine, and then depositing a metal pad body at the tail end of the circuit; applying a certain voltage to the metal pad body through a micro-light microscope so as to highlight a hot spot signal at the failure position; marking a laser mark at the failure point; cutting a section at the laser mark position by using a focused ion beam machine, and simultaneously observing a failure point to prepare a transmission electron microscope test piece; and characterizing the test piece using a transmission electron microscope. The method can quickly realize the positioning and characterization of the short-circuit point of the word line layer.
Description
Technical Field
The invention relates to a failure analysis method, in particular to a method for quickly positioning a short circuit of a three-dimensional memory array area.
Background
In the semiconductor development and production processes, failure analysis is an indispensable means for improving the process and increasing the yield. In the failure analysis process, the most important step is the positioning of a failure point, and the positioning precision directly influences the subsequent analysis, so that how to obtain an accurate failure position is particularly critical. However, in the current three-dimensional memory product, the memory array area structure is a word line layer stacking mode, and as the number of stacking layers is increased (greater than or equal to 32 layers), the array area range is increased (greater than or equal to 3mm by 6mm), and the failure of the array area becomes a main failure mode. For the failure of the short circuit type between word line layers and between the word line and the source, the failure point needs to be accurately positioned (within the range of less than or equal to 1 μm) so as to realize the failure analysis of the array area, and a set of flow needs to be designed to quickly realize the positioning and slice analysis of the short circuit point.
The prior art can not realize the accurate positioning and characterization of short circuit failure points between word line layers and between word lines and source electrodes of a three-dimensional memory array area. The unstable process of the three-dimensional memory causes short circuits between the word line layer and the array area and between the word line layer and the source, thereby affecting the performance of the product. Due to the large array area range, it is a great difficulty to accurately find the failure point and characterize the failure point.
The information disclosed in this background section is only for enhancement of understanding of the general background of the invention and should not be taken as an acknowledgement or any form of suggestion that this information forms the prior art already known to a person skilled in the art.
Disclosure of Invention
It is an object of the present invention to provide a method for rapidly locating a short in a three-dimensional memory array region, thereby overcoming the disadvantages of the prior art.
To achieve the above object, the present invention provides a method for rapidly positioning a short circuit in a three-dimensional memory array region, which is characterized in that: the method comprises the following steps: treating a sample to be tested to a tungsten plug layer to obtain a treated sample to be tested; marking the failure block of the processed sample to be tested by using a focused ion beam machine table, thereby facilitating the needle setting of the nano-point needle table; applying a certain voltage to the tungsten plug in the step area through the nanodot needle platform to find out a failure path between the word line layer and the array area or between the word line layer and the source electrode; leading out a circuit at a tungsten plug position of a step area corresponding to the failed word line layer by using a focused ion beam machine, and then depositing a metal pad body at the tail end of the circuit; applying a certain voltage to the metal pad body through a micro-light microscope so as to highlight a hot spot signal at the failure position; marking a laser mark at the failure point by a low-light microscope; cutting a section at the laser mark position by using a focused ion beam machine, and simultaneously observing a failure point to prepare a transmission electron microscope test piece; and characterizing the test piece using a transmission electron microscope.
Preferably, in the above technical scheme, the step of processing the sample to be tested to the tungsten plug layer to obtain the processed sample to be tested specifically includes: and treating the sample to be tested to the tungsten plug layer, keeping the cleanliness of the sample to be tested, and baking by using a heating table to remove moisture in the sample to be tested to obtain the treated sample to be tested.
Preferably, in the above technical solution, the marking laser mark at the failure point is specifically: the failure point is marked with a criss-cross laser mark with an accuracy of up to 1 μm.
Preferably, in the above technical solution, the failure is a short circuit.
Compared with the prior art, the invention has the following beneficial effects: firstly, processing a chip; then finding out a short circuit path between the word line layer and the array area or between the word line layer and a source electrode through the nano-dot needle platform; capturing a hot spot signal at the short circuit position through a low-light-level microscope and carrying out laser marking to reduce the target range; cutting a section of the laser mark by using a focused ion beam machine, observing failure points and preparing a transmission electron microscope test piece; and finally, characterizing the failure point by using a transmission electron microscope. Through the steps, the positioning and characterization of the short-circuit point of the word line layer can be quickly realized.
Drawings
Fig. 1 is a top view of a chip according to the present invention.
Fig. 2 is a schematic top view of a chip according to the present invention.
Fig. 3 is a schematic cross-sectional view of a chip according to the present invention.
Fig. 4 is a flow chart of a method according to the invention.
Detailed Description
The following detailed description of the present invention is provided in conjunction with the accompanying drawings, but it should be understood that the scope of the present invention is not limited to the specific embodiments.
Throughout the specification and claims, unless explicitly stated otherwise, the word "comprise", or variations such as "comprises" or "comprising", will be understood to imply the inclusion of a stated element or component but not the exclusion of any other element or component.
Fig. 1 is a top view of a chip according to the present invention. The chip of the invention comprises fig. 2 is a schematic top view of a chip according to the invention. Fig. 3 is a schematic cross-sectional view of a chip according to the present invention. As can be seen from the figure, the chip of the present invention includes an array region 101 and a step region 102. A short circuit path exists between the word line layer and the word line layer or between the word line layer and the source in the array region 101, wherein the WL is about 5.9 mm; and (3) leading out a circuit at the tungsten plug of the stepped area 102 corresponding to the failed word line layer by using a focused ion beam machine, and then depositing a metal pad at the tail end of the circuit.
Fig. 4 is a flow chart of a method according to the invention. The method comprises the steps of treating a sample to be tested to a tungsten plug layer to obtain a treated sample to be tested 401; marking the failure block of the processed sample to be tested by using a focused ion beam machine table, thereby facilitating the needle setting 402 of the nano-point needle table; applying a certain voltage to the step area tungsten plug through the nanodot needle platform to find out a failure path 403 between the array area word line layer and the word line layer or between the word line layer and the source electrode; a focused ion beam machine is used for leading out a circuit at a tungsten plug position of a step area corresponding to the failed word line layer, and then a metal pad body 404 is deposited at the tail end of the circuit; applying a certain voltage to the metal pad body through a micro-light microscope, so as to highlight a hot spot signal 405 at the failure position; marking laser marks 406 at the failure points by a micro-light microscope; cutting a section at the laser mark position by using a focused ion beam machine, and simultaneously observing a failure point to prepare a transmission electron microscope test piece 407; and characterizing 408 the test strip using transmission electron microscopy. Preferably, in the above technical scheme, the step of processing the sample to be tested to the tungsten plug layer to obtain the processed sample to be tested specifically includes: and treating the sample to be tested to the tungsten plug layer, keeping the cleanliness of the sample to be tested, and baking by using a heating table to remove moisture in the sample to be tested to obtain the treated sample to be tested. Preferably, in the above technical solution, the marking laser mark at the failure point is specifically: the failure point is marked with a criss-cross laser mark with an accuracy of up to 1 μm. Preferably, in the above technical solution, the failure is a short circuit.
The foregoing descriptions of specific exemplary embodiments of the present invention have been presented for purposes of illustration and description. It is not intended to limit the invention to the precise form disclosed, and obviously many modifications and variations are possible in light of the above teaching. The exemplary embodiments were chosen and described in order to explain certain principles of the invention and its practical application to enable one skilled in the art to make and use various exemplary embodiments of the invention and various alternatives and modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims and their equivalents.
Claims (4)
1. A method for rapidly locating a short in a three-dimensional memory array region, comprising: the method comprises the following steps:
treating a sample to be tested to a tungsten plug layer to obtain a treated sample to be tested;
marking the failure block of the processed sample to be tested by using a focused ion beam machine table, thereby facilitating the needle setting of the nano-point needle table;
applying a certain voltage to the tungsten plug in the step area through the nanodot needle platform to find out a failure path between the word line layer and the array area or between the word line layer and the source electrode;
leading out a circuit at a step area tungsten plug corresponding to the failed word line layer by using a focused ion beam machine, and then depositing a metal pad body at the tail end of the circuit;
applying a certain voltage to the metal pad body through a micro-light microscope so as to highlight a hot spot signal at a failure position;
marking a laser mark at the failure point by the low-light microscope;
cutting a section at the laser mark position by using the focused ion beam machine, and observing the failure point to prepare a transmission electron microscope test piece; and
the specimen was characterized using the transmission electron microscope.
2. The method for rapidly locating a three-dimensional memory array region short of claim 1, wherein: treating a sample to be tested to a tungsten plug layer, wherein the treated sample to be tested is specifically as follows: processing a sample to be tested to a tungsten plug layer, keeping the cleanliness of the sample to be tested, and baking by using a heating table to remove moisture in the sample to be tested to obtain the processed sample to be tested.
3. The method for rapidly locating a three-dimensional memory array region short of claim 1, wherein: the marking of the laser mark at the failure point is specifically: the failure points are marked with a criss-cross laser mark with an accuracy of up to 1 μm.
4. The method for rapidly locating a short in a three dimensional memory array region as recited in one of claims 1 to 3, wherein: the failure is a short circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711165507.2A CN107993951B (en) | 2017-11-21 | 2017-11-21 | Method for quickly positioning short circuit of three-dimensional memory array area |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711165507.2A CN107993951B (en) | 2017-11-21 | 2017-11-21 | Method for quickly positioning short circuit of three-dimensional memory array area |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107993951A CN107993951A (en) | 2018-05-04 |
| CN107993951B true CN107993951B (en) | 2020-09-25 |
Family
ID=62031910
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201711165507.2A Active CN107993951B (en) | 2017-11-21 | 2017-11-21 | Method for quickly positioning short circuit of three-dimensional memory array area |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107993951B (en) |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109920742B (en) * | 2019-02-13 | 2021-02-26 | 长江存储科技有限责任公司 | Semiconductor device failure detection method |
| CN109872766B (en) * | 2019-02-15 | 2021-07-16 | 长江存储科技有限责任公司 | Failure analysis method of three-dimensional memory |
| CN109935271B (en) * | 2019-03-29 | 2021-03-23 | 武汉新芯集成电路制造有限公司 | Memory and acquisition method and failure positioning method thereof |
| CN110690176B (en) * | 2019-10-14 | 2022-01-11 | 长江存储科技有限责任公司 | Method for distinguishing target crystal grains and failure analysis method of packaged chip |
| CN110718480B (en) * | 2019-10-18 | 2022-11-29 | 长江存储科技有限责任公司 | Method and system for judging leakage of word line layer |
| CN110987981A (en) * | 2019-11-11 | 2020-04-10 | 中国科学院上海技术物理研究所 | Method for representing correlation between InGaAs detector material defects and device performance |
| CN111243974B (en) * | 2020-01-16 | 2023-01-13 | 长江存储科技有限责任公司 | Method for calibrating short circuit between 3D NAND bit line and word line |
| CN113129989A (en) * | 2021-04-20 | 2021-07-16 | 苏州鲲腾智能科技有限公司 | Preparation method of three-dimensional memory failure analysis sample |
| CN113314542B (en) * | 2021-04-27 | 2022-01-25 | 长江存储科技有限责任公司 | Sample preparation method |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102253328A (en) * | 2010-05-21 | 2011-11-23 | 武汉新芯集成电路制造有限公司 | Method for analyzing failure of bit lines in memory chip |
| CN102854429A (en) * | 2011-06-28 | 2013-01-02 | 上海华碧检测技术有限公司 | Failure point positioning method for semiconductor power device failure analysis |
| CN103698179A (en) * | 2013-12-17 | 2014-04-02 | 武汉新芯集成电路制造有限公司 | Method for preparing planar sample for transmission electron microscope at specific failure point |
| CN103700603A (en) * | 2013-12-17 | 2014-04-02 | 武汉新芯集成电路制造有限公司 | Detection method of high resistance of tungsten contact plug |
| US9224502B1 (en) * | 2015-01-14 | 2015-12-29 | Sandisk Technologies Inc. | Techniques for detection and treating memory hole to local interconnect marginality defects |
| CN106154133A (en) * | 2015-04-24 | 2016-11-23 | 中芯国际集成电路制造(上海)有限公司 | The address method of testing of chip and the failure analysis method of chip |
| CN106206344A (en) * | 2015-05-08 | 2016-12-07 | 中芯国际集成电路制造(上海)有限公司 | A kind of method of the defect of the contact plug determined in connection memory element |
| CN107230649A (en) * | 2016-03-25 | 2017-10-03 | 日本株式会社日立高新技术科学 | Section processing observational technique, section processing observation device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9830998B2 (en) * | 2015-05-19 | 2017-11-28 | Sandisk Technologies Llc | Stress patterns to detect shorts in three dimensional non-volatile memory |
-
2017
- 2017-11-21 CN CN201711165507.2A patent/CN107993951B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102253328A (en) * | 2010-05-21 | 2011-11-23 | 武汉新芯集成电路制造有限公司 | Method for analyzing failure of bit lines in memory chip |
| CN102854429A (en) * | 2011-06-28 | 2013-01-02 | 上海华碧检测技术有限公司 | Failure point positioning method for semiconductor power device failure analysis |
| CN103698179A (en) * | 2013-12-17 | 2014-04-02 | 武汉新芯集成电路制造有限公司 | Method for preparing planar sample for transmission electron microscope at specific failure point |
| CN103700603A (en) * | 2013-12-17 | 2014-04-02 | 武汉新芯集成电路制造有限公司 | Detection method of high resistance of tungsten contact plug |
| US9224502B1 (en) * | 2015-01-14 | 2015-12-29 | Sandisk Technologies Inc. | Techniques for detection and treating memory hole to local interconnect marginality defects |
| CN106154133A (en) * | 2015-04-24 | 2016-11-23 | 中芯国际集成电路制造(上海)有限公司 | The address method of testing of chip and the failure analysis method of chip |
| CN106206344A (en) * | 2015-05-08 | 2016-12-07 | 中芯国际集成电路制造(上海)有限公司 | A kind of method of the defect of the contact plug determined in connection memory element |
| CN107230649A (en) * | 2016-03-25 | 2017-10-03 | 日本株式会社日立高新技术科学 | Section processing observational technique, section processing observation device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN107993951A (en) | 2018-05-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN107993951B (en) | Method for quickly positioning short circuit of three-dimensional memory array area | |
| CN103913358B (en) | The preparation method and failure analysis method of TEM sample | |
| Hayworth et al. | Ultrastructurally smooth thick partitioning and volume stitching for large-scale connectomics | |
| CN109920742B (en) | Semiconductor device failure detection method | |
| CN107167485B (en) | A kind of preparation method of the power-up transmission electron microscope cross-sectional sample in situ of hetero-junction thin-film | |
| CN107993948B (en) | Method for measuring word line resistance of three-dimensional memory | |
| CN105352768A (en) | TEM sample positioning method | |
| CN105241718A (en) | Transmission electron microscope (TEM) sample preparation method | |
| CN108010860B (en) | Self-positioning electromigration test structure and transmission electron microscope sample preparation method | |
| CN106323709A (en) | Preparation method and test method for test sample | |
| CN105806679A (en) | Preparation method for TEM sample | |
| CN106373905B (en) | A kind of localization method of gate oxide leakage point of electricity | |
| JP6979453B2 (en) | A device for measuring the minute potential of a sample, a method for manufacturing the device, and a method for using the device. | |
| CN106449465B (en) | Method for testing single bit on memory chip | |
| CN113740697B (en) | Method, equipment and system for testing semiconductor device | |
| CN104037107A (en) | Failure analysis method for through hole chain structure | |
| CN103280440B (en) | The semiconductor structure of preparation TEM sample and method | |
| JP2010276617A (en) | Method for manufacturing probe, probe, and scanning probe microscope | |
| JP5187677B2 (en) | Tool positioning method and tool positioning device | |
| CN108106890A (en) | The preparation method of the TEM sample of nickel metal silicide | |
| TW201404711A (en) | Method for manufacturing a probe of a scanning microscope and product thereof | |
| CN110436406B (en) | System and method for preparing solid-state nanopore array by automatic accurate positioning | |
| CN105403689A (en) | Method for processing biosensor test paper by using laser resistance adjusting system | |
| CN105845590B (en) | Method for detecting metal defects | |
| CN107958849A (en) | Without hindrance barrier metal layer power device IGSSFail independent positioning method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |