CN107991523B - A kind of three-state input detection circuit and its detection method - Google Patents
A kind of three-state input detection circuit and its detection method Download PDFInfo
- Publication number
- CN107991523B CN107991523B CN201711233375.2A CN201711233375A CN107991523B CN 107991523 B CN107991523 B CN 107991523B CN 201711233375 A CN201711233375 A CN 201711233375A CN 107991523 B CN107991523 B CN 107991523B
- Authority
- CN
- China
- Prior art keywords
- resistance
- pmos tube
- tube
- phase inverter
- nmos tube
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
- G01R19/0084—Arrangements for measuring currents or voltages or for indicating presence or sign thereof measuring voltage only
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Measuring Fluid Pressure (AREA)
- Measurement Of Resistance Or Impedance (AREA)
Abstract
The invention discloses a kind of three-state input detection circuits, wherein including detection circuit after sequentially connected bleeder circuit and partial pressure, the bleeder circuit connects an input signal Vin, for dividing input signal；Detection circuit after the partial pressure, the input state for checking input signal.A kind of three-state input detection circuit of the present invention has the characteristics that detection accuracy is high.The invention also discloses the detection methods of the detection circuit.
Description
Technical field
The present invention relates to a kind of circuit checkers, more specifically more particularly to a kind of three-state input detection circuit；This
Invention further relates to a kind of detection method of three-state input detection circuit.
Background technology
The input state of circuit includes that three kinds of high level, low level and high-impedance state (suspended state) are basic under normal circumstances
Logic state.Usually it can determine that input voltage is in high level, low level or height using detection circuit when designing circuit
Resistance state.
As shown in Figure 1, the composition input point in parallel with resistance R1 and resistance R2 of the input signal of traditional tri-state detection circuit
Volt circuit, input signal are also connected with the grid of the grid and transistor M2 of transistor M1, the other end of resistance R1 respectively with crystal
The drain electrode of pipe M1 is connected with the drain electrode of transistor M2, the other end of resistance R2 respectively with the source electrode of transistor M1 and transistor M2
Source electrode connects, and constitutes the different comparator of turn threshold, and when input is high level or low level, Vin is entered signal drawing
Height drags down, and compares the corresponding result of output.When input is high-impedance state, bleeder circuit provides Vin voltages, exports corresponding knot
Fruit.To achieve the purpose that detect input state.Traditional tri-state detection circuit will appear when strong noise, supply voltage are unstable
Mistake is detected, anti-interference ability is poor, while its bleeder circuit current drain is larger.Keep detection accurate it would therefore be highly desirable to invent one kind
The higher three-state input detection circuit of true property.
Invention content
The previous of the present invention is designed to provide a kind of three-state input detection circuit, which passes through input state control
The work of two NMOS and two PMOS transmission gates is made, tri-state input detection is realized, has the characteristics that detection accuracy is high.This hair
Bright latter purpose is to provide a kind of detection method of three-state input detection circuit.
The previous technical solution of the present invention is as follows：
A kind of three-state input detection circuit, wherein including sequentially connected bleeder circuit and partial pressure after detection circuit,
The bleeder circuit connects an input signal Vin, for dividing input signal；
Detection circuit after the partial pressure, the input state for checking input signal.
Preferably, the described partial pressure electricity 1 include resistance R1, resistance R2, resistance R3, resistance R4, resistance R5, PMOS tube PM1,
PMOS tube PM2, PMOS tube PM3, NMOS tube NM1, the input signal Vin by after resistance R5 respectively with PMOS tube PM3's
The source electrode connection of source electrode, NMOS tube NM1, the drain electrode of the NMOS tube NM1 are sequentially connected after resistance R3, resistance R1 and PMOS tube
The source electrode of PM1 connects, the grid of the PMOS tube PM1 be separately connected the drain electrode of PMOS tube PM1, PMOS tube PM2 source electrode and
The grid of the grid of NMOS tube NM1, the PMOS tube PM2 is connect with the grid of the drain electrode of PMOS tube PM2, PMOS tube PM3 respectively,
The drain electrode of the PMOS tube PM2 is connect after being sequentially connected resistance R2, resistance R4 with the drain electrode of PMOS tube PM3, the resistance R2 and
Resistance R4 indirectly, an operating voltage VDD is connected between the resistance R1 and resistance R3.
Preferably, after the partial pressure detection circuit include phase inverter U1, it is phase inverter U2, phase inverter U3, phase inverter U4, anti-
Phase device U5, phase inverter U6, phase inverter U7, PMOS tube PM4, PMOS tube PM5, NMOS tube NM2, NMOS tube NM3, the NMOS tube
The drain electrode of NM1 with the grid of phase inverter U2, the source electrode of PMOS tube PM4, PMOS tube PM5 by connecting respectively after phase inverter U1, institute
The output for stating phase inverter U2 is separately connected the grid of the source electrode of NMOS tube NM2, NMOS tube NM3, and the drain electrode of the PMOS tube PM3 is logical
Cross sources of the phase inverter U3 respectively with the grid of phase inverter U3, the source electrode of NMOS tube NM3, the grid of PMOS tube PM4, PMOS tube PM5
Pole and phase inverter U6 connections, the drain electrode of the NMOS tube NM2 and the drain electrode of NMOS tube NM3, the drain electrode of PMOS tube PM4 and
Connect output end OUT1 after the drain electrode parallel connection of PMOS tube PM5 after phase inverter U4, phase inverter U5 successively, the phase inverter U6's
Output end connects connection output end OUT2 after phase inverter U7.
Latter technique scheme of the present invention is as follows：
A kind of detection method of three-state input detection circuit, includes the following steps：
(1) input signal enters three-state input detection circuit, and detection is exported respectively from output end OUT1 and output end OUT2
Information judges the input state of input signal according to the inspection information of output；
(2) when input signal Vin is high level, PMOS tube PM3 conductings, resistance R4 pressure drops are high, output end OUT2 outputs
" 0 ", NMOS tube NM1 cut-offs, resistance R3 is without pressure drop, NMOS tube NM3 conductings, output end OUT1 outputs " 0 "；
(3) when input signal Vin is low level, PMOS tube PM3 cut-offs, resistance R4 is without pressure drop, output end OUT2 outputs
" 1 ", NMOS tube NM1 conductings, resistance R3 pressure drops are big, NMOS tube NM2 conductings, output end OUT1 outputs " 0 "；
(4) when input signal Vin is high-impedance state, PMOS tube PM3 conductings, resistance R4 pressure drops are small, output end OUT2 outputs
" 1 ", NMOS tube NM1 conductings, resistance R3 pressure drops are small, PMOS tube PM4 conductings, output end OUT1 outputs " 1 ".
Compared with prior art, the device have the advantages that being：
1. a kind of three-state input detection circuit of the present invention, wherein including being examined after sequentially connected bleeder circuit and partial pressure
Slowdown monitoring circuit, the bleeder circuit connects an input signal Vin, for dividing input signal；It is examined after the partial pressure
Slowdown monitoring circuit, the input state for checking input signal.When detecting, input signal Vin current potentials when low and high level is inputted by
Input signal determines, is determined by bleeder circuit in high-impedance state, meanwhile, input state controls the conducting of NM1 and PM3 pipes, determines
The pressure drop of pull-up resistor R3 and pull down resistor R4.NMOS transmits low level, and PMOS transmits high level；The output electricity of pull down resistor R4
Pressure obtains detection signal OUT2 after phase inverter is delayed；The output voltage of pull-up resistor R3 and pull down resistor R4, pass through reverse phase
Device so that only there are one transmission gates to work, and transmits corresponding level, obtains detection signal OUT1；Due in high-impedance state, NM1, PM3
Conducting, but it is much smaller when pull down resistor and pull-up resistor voltage drop value ratio input low and high level so that and output testing result will not weigh
It is multiple, have the characteristics that detection accuracy is high.
2. a kind of detection method of three-state input detection circuit of the present invention detects input state using this detection method
When, the different way of outputs, which is shown, to be realized to three kinds of input states, testing result is more acurrate clear.
Description of the drawings
Fig. 1 is the circuit diagram of traditional tri-state detection circuit；
Fig. 2 is the circuit diagram of the present invention.
Specific implementation mode
With reference to embodiment, technical scheme of the present invention is described in further detail, but do not constituted pair
Any restrictions of the present invention.
With reference to shown in Fig. 2, a kind of three-state input detection circuit of the invention, wherein including sequentially connected bleeder circuit 1
With detection circuit 2 after partial pressure,
The bleeder circuit 1 connects an input signal Vin, for dividing input signal；
Detection circuit 2 after the partial pressure, the input state for checking input signal.
The bleeder circuit 1 includes resistance R1, resistance R2, resistance R3, resistance R4, resistance R5, PMOS tube PM1, PMOS
Pipe PM2, PMOS tube PM3, NMOS tube NM1, the input signal Vin by after resistance R5 respectively with the source electrode of PMOS tube PM3,
The source electrode of NMOS tube NM1 connects, and the drain electrode of the NMOS tube NM1 is sequentially connected the source after resistance R3, resistance R1 with PMOS tube PM1
Pole connects, and the grid of the PMOS tube PM1 is separately connected the drain electrode of PMOS tube PM1, the source electrode of PMOS tube PM2 and NMOS tube
The grid of the grid of NM1, the PMOS tube PM2 is connect with the grid of the drain electrode of PMOS tube PM2, PMOS tube PM3 respectively, described
The drain electrode of PMOS tube PM2 is connect after being sequentially connected resistance R2, resistance R4 with the drain electrode of PMOS tube PM3, the resistance R2 and resistance
R4 indirectly, an operating voltage VDD is connected between the resistance R1 and resistance R3.The current potential of input signal Vin is inputting
Signal is to be determined by input signal when high level inputs or low level inputs, when input signal is high-impedance state, input signal
The current potential of Vin is determined by bleeder circuit 1；Meanwhile the conducting of the input state control NM1 and PM3 pipes of input signal Vin, to
Determine the pressure drop of resistance R3 and resistance R4.
Detection circuit 2 includes phase inverter U1, phase inverter U2, phase inverter U3, phase inverter U4, phase inverter after the partial pressure
U5, phase inverter U6, phase inverter U7, PMOS tube PM4, PMOS tube PM5, NMOS tube NM2, NMOS tube NM3, the NMOS tube NM1's
Drain electrode with the grid of phase inverter U2, the source electrode of PMOS tube PM4, PMOS tube PM5 by connecting respectively after phase inverter U1, the reverse phase
The output of device U2 is separately connected the grid of the source electrode of NMOS tube NM2, NMOS tube NM3, and the drain electrode of the PMOS tube PM3 passes through reverse phase
Device U3 respectively with the grid of NMOS tube NM2, the source electrode of NMOS tube NM3, the grid of PMOS tube PM4, PMOS tube PM5 source electrode and
Phase inverter U6 connections, the drain electrode of the NMOS tube NM2 and the drain electrode of NMOS tube NM3, the drain electrode of PMOS tube PM4 and PMOS tube
Connect output end OUT1, the output end of the phase inverter U6 after the drain electrode parallel connection of PM5 after phase inverter U4, phase inverter U5 successively
Output end OUT2 is connected after connecting phase inverter U7.4 metal-oxide-semiconductors transmit low electricity as transmission gate, NMOS tube NM2 and NMOS tube NM3
Flat, PMOS tube PM4 and PMOS tube PM5 transmit high level；It is defeated that the output voltage of resistance R4 obtains connection after phase inverter is delayed
Outlet OUT2；The output voltage of resistance R3 and resistance R4, by phase inverter so that only there are one transmission gates to work, transmission is corresponding
Level obtains connection output end OUT1；Since in high-impedance state, NMOS tube NM1 and PMOS tube PM3 are connected, but resistance R3 and electricity
It is much smaller when resistance R4 voltage drop values are inputted than input signal for high level or low level inputs so that output testing result will not weigh
It is multiple, have the characteristics that detection accuracy is high.
A kind of detection method of three-state input detection circuit, includes the following steps：
(1) input signal enters three-state input detection circuit, and detection is exported respectively from output end OUT1 and output end OUT2
Information judges the input state of input signal according to the detection information of output；
(2) when input signal Vin is high level, PMOS tube PM3 conductings, resistance R4 pressure drops are high, output end OUT2 outputs
" 0 ", NMOS tube NM1 cut-offs, resistance R3 is without pressure drop, NMOS tube NM3 conductings, output end OUT1 outputs " 0 "；
(3) when input signal Vin is low level, PMOS tube PM3 cut-offs, resistance R4 is without pressure drop, output end OUT2 outputs
" 1 ", NMOS tube NM1 conductings, resistance R3 pressure drops are big, NMOS tube NM2 conductings, output end OUT1 outputs " 0 "；
(4) when input signal Vin is high-impedance state, PMOS tube PM3 conductings, resistance R4 pressure drops are small, output end OUT2 outputs
" 1 ", NMOS tube NM1 conductings, resistance R3 pressure drops are small, PMOS tube PM4 conductings, output end OUT1 outputs " 1 ".
The results are shown in Table 1 for a kind of three-state input detection circuit of the present invention：
1 three-state input detection circuit of table exports result
| Input state | Output end OUT1 | Output end OUT2 |
| High level | 0 | 0 |
| Low level | 0 | 1 |
| High-impedance state | 1 | 1 |
As can be seen from Table 1, a kind of three-state input detection circuit of the invention, set bleeder circuit can be realized not
Transmission gate working condition when being inputted with low and high level, the characteristic of high-impedance state high resistant, when control is different and low and high level inputs
Transmission gate works, and realizes the output of three kinds of results, testing result accuracy higher.
The foregoing is merely presently preferred embodiments of the present invention, it is all within the scope of the spirit and principles in the present invention made by it is any
Modifications, equivalent substitutions and improvements etc., should all be included in the protection scope of the present invention.
Claims (2)
1. a kind of three-state input detection circuit, which is characterized in that including detecting electricity after sequentially connected bleeder circuit (1) and partial pressure
Road (2),
The bleeder circuit (1) connects an input signal (Vin), for dividing input signal；
The bleeder circuit (1) includes resistance R1, resistance R2, resistance R3, resistance R4, resistance R5, PMOS tube PM1, PMOS tube
PM2, PMOS tube PM3, NMOS tube NM1, the input signal (Vin) by after resistance R5 respectively with the source electrode of PMOS tube PM3,
The source electrode of NMOS tube NM1 connects, and the drain electrode of the NMOS tube NM1 is sequentially connected the source after resistance R3, resistance R1 with PMOS tube PM1
Pole connects, and the grid of the PMOS tube PM1 is separately connected the drain electrode of PMOS tube PM1, the source electrode of PMOS tube PM2 and NMOS tube
The grid of the grid of NM1, the PMOS tube PM2 is connect with the grid of the drain electrode of PMOS tube PM2, PMOS tube PM3 respectively, described
The drain electrode of PMOS tube PM2 is connect after being sequentially connected resistance R2, resistance R4 with the drain electrode of PMOS tube PM3, the resistance R2 and resistance
R4 indirectly, an operating voltage (VDD) is connected between the resistance R1 and resistance R3；
Detection circuit (2) after the partial pressure, the input state for checking input signal；
After the partial pressure detection circuit (2) include phase inverter U1, phase inverter U2, phase inverter U3, phase inverter U4, phase inverter U5,
Phase inverter U6, phase inverter U7, PMOS tube PM4, PMOS tube PM5, NMOS tube NM2, NMOS tube NM3, the drain electrode of the NMOS tube NM1
By being connect respectively with the grid of phase inverter U2, the source electrode of PMOS tube PM4, PMOS tube PM5 after phase inverter U1, the phase inverter U2
Output be separately connected the grid of the source electrode of NMOS tube NM2, NMOS tube NM3, the drain electrode of the PMOS tube PM3 passes through phase inverter U3
Respectively with the grid of NMOS tube NM2, the source electrode of NMOS tube NM3, the grid of PMOS tube PM4, the source electrode of PMOS tube PM5 and reverse phase
Device U6 connections, the drain electrode of the NMOS tube NM2 and the drain electrode of NMOS tube NM3, the drain electrode of PMOS tube PM4 and PMOS tube PM5
Connect the output end connection of output end OUT1, the phase inverter U6 after drain electrode is in parallel after phase inverter U4, phase inverter U5 successively
Output end OUT2 is connected after phase inverter U7.
2. a kind of detection method of three-state input detection circuit described in claim 1, which is characterized in that include the following steps：
(1) input signal enters three-state input detection circuit, and detection information is exported respectively from output end OUT1 and output end OUT2,
The input state of input signal is judged according to the detection information of output；
(2) when input signal (Vin) is high level, PMOS tube PM3 conductings, resistance R4 pressure drops are high, output end OUT2 outputs " 0 ",
NMOS tube NM1 cut-offs, resistance R3 is without pressure drop, NMOS tube NM3 conductings, output end OUT1 outputs " 0 "；
(3) when input signal (Vin) is low level, PMOS tube PM3 ends, and resistance R4 exports " 1 " without pressure drop, output end OUT2,
NMOS tube NM1 conductings, resistance R3 pressure drops are big, NMOS tube NM2 conductings, output end OUT1 outputs " 0 "；
(4) when input signal (Vin) is high-impedance state, PMOS tube PM3 conductings, resistance R4 pressure drops are small, output end OUT2 outputs " 1 ",
NMOS tube NM1 conductings, resistance R3 pressure drops are small, PMOS tube PM4 conductings, output end OUT1 outputs " 1 ".
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711233375.2A CN107991523B (en) | 2017-11-30 | 2017-11-30 | A kind of three-state input detection circuit and its detection method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711233375.2A CN107991523B (en) | 2017-11-30 | 2017-11-30 | A kind of three-state input detection circuit and its detection method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107991523A CN107991523A (en) | 2018-05-04 |
| CN107991523B true CN107991523B (en) | 2018-11-02 |
Family
ID=62034465
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201711233375.2A Expired - Fee Related CN107991523B (en) | 2017-11-30 | 2017-11-30 | A kind of three-state input detection circuit and its detection method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107991523B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112526581B (en) * | 2020-11-26 | 2024-10-18 | 南京模数智芯微电子科技有限公司 | Time discriminator suitable for radiation detection front end readout circuit |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4743842A (en) * | 1987-03-11 | 1988-05-10 | Grumman Aerospace Corporation | Tri-state circuit tester |
| CN102201807B (en) * | 2011-04-11 | 2012-09-19 | 长沙景嘉微电子股份有限公司 | Simple tristate input circuit |
| CN202404208U (en) * | 2011-10-27 | 2012-08-29 | 苏州路之遥科技股份有限公司 | Tri-state detection circuit based on I/O port |
| CN103018588B (en) * | 2012-11-23 | 2015-03-18 | 无锡中星微电子有限公司 | Low-power-consumption anti-interference three-state input detection circuit |
| TWI519072B (en) * | 2013-05-10 | 2016-01-21 | 盛群半導體股份有限公司 | Tri-state detection circuit with ultra-low power consumption and state detection method thereof |
-
2017
- 2017-11-30 CN CN201711233375.2A patent/CN107991523B/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| CN107991523A (en) | 2018-05-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102739224B (en) | Omnipolare magnetschalter and method for providing same | |
| CN103716034A (en) | Multiplex circuit for chip pins | |
| CN104236594B (en) | Safety edge state detection circuit | |
| CN204349432U (en) | A kind of Switching Power Supply thermal-shutdown circuit | |
| CN106325449B (en) | A kind of power-on-reset circuit with low power consumption | |
| CN106936414A (en) | Electrification reset circuit | |
| CN204465489U (en) | A kind of New Low Voltage electrify restoration circuit | |
| CN107991523B (en) | A kind of three-state input detection circuit and its detection method | |
| CN108022617A (en) | Variable resistance memory circuit and writing method of variable resistance memory circuit | |
| CN103018588B (en) | Low-power-consumption anti-interference three-state input detection circuit | |
| CN103178820A (en) | Power-on reset circuit | |
| CN104090226B (en) | Circuit for testing connectivity of chip pins | |
| CN101566645B (en) | Detection circuit for power supply voltage pulse interference | |
| CN204256086U (en) | A kind of open circuit short-circuit test device of wiring board | |
| CN109104182B (en) | Quick low-power consumption single-ended interface | |
| US20190235006A1 (en) | Wiring line abnormality detecting device | |
| CN104601162B (en) | A kind of reusable digital input-output interface circuit | |
| CN104716938B (en) | A kind of grid follow imput output circuit | |
| CN105591637A (en) | Automatic reset module in integrated circuit | |
| CN206135875U (en) | Many input data state detection circuitry that walks abreast with threshold value numerical control | |
| CN103954901A (en) | Device for detecting faults of CMOS integrated circuit of handheld device | |
| CN108932408A (en) | A kind of enable signal control circuit and a kind of chip | |
| CN203896318U (en) | Differential input circuit | |
| JP6859418B2 (en) | Semiconductor circuit, voltage detection circuit, and voltage judgment circuit | |
| CN200976574Y (en) | Single-ended input hysteresis comparator circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20210106 Address after: 528402 room 1217, Zhixian building, 3 Longjing South Road, Shiqi District, Zhongshan City, Guangdong Province (3) Patentee after: Zhongshan Hongxin Electronic Technology Co.,Ltd. Address before: 510640 Room 502, building 30, South China University of technology, Wushan, Tianhe District, Guangzhou City, Guangdong Province Patentee before: SOUTH CHINA University OF TECHNOLOGY |
|
| TR01 | Transfer of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20181102 Termination date: 20211130 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |