CN206135875U - Many input data state detection circuitry that walks abreast with threshold value numerical control - Google Patents
Many input data state detection circuitry that walks abreast with threshold value numerical control Download PDFInfo
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- CN206135875U CN206135875U CN201621047570.7U CN201621047570U CN206135875U CN 206135875 U CN206135875 U CN 206135875U CN 201621047570 U CN201621047570 U CN 201621047570U CN 206135875 U CN206135875 U CN 206135875U
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Abstract
The utility model discloses a many input data state detection circuitry that walks abreast with threshold value numerical control, include the detection shut that corresponds with a plurality of data input interface, this detects along separate routes including bias circuit and two threshold value comparing element, wherein bias circuit includes the resistance of two series connection, and the node between two resistance links to each other with data input interface, and this node is connected respectively with two threshold value comparing element's first input end, two threshold value comparing element's second input is connected with a threshold voltage generation unit respectively, and two input one -to -ones of two threshold value comparing element's output AND circuit are connected, and the output of this gate circuit is connected on the input of a AND gate, the utility model discloses an apply signal voltage to a plurality of data input interface compares respectively, and whether the input data who determines data input interface according to the output data of AND gate is effective to the whether effectual parallel detection to a plurality of data input interface's input data has been realized.
Description
Technical field
The utility model is related to integrated circuit fields, more particularly to a kind of multi input data mode with threshold value numerical control is simultaneously
Row detection circuit.
Background technology
Since mankind's nineteen forty-seven utility model transistor, semiconductor technology experienced silicon transistor, collection between more than 50 years
Into several generations such as circuit, super large-scale integration, very large scale integrations, development speed is soon that other industries are not had
's；Central processing unit refers to the part that computer-internal is processed data and is controlled to processing procedure, along with big
Scale integrated circuit technology is developed rapidly, and integrated chip density more and more higher, CPU can be integrated in a semiconductor chip
On, this LSI devices with central processing unit function are collectively referred to as " microprocessor "；Either record a video
The household appliances such as machine, intelligent washing machine, mobile phone, or car engine control, and Digit Control Machine Tool, guided missile precise guidance etc.
All kinds of different microprocessors will be embedded in；Microprocessor is not only the core component of microcomputer, is also various digitlizations
The critical component of smart machine.
And interface chip, it is that, for connecting a kind of electronic devices and components between microprocessor and memory, it includes number
According to the data buffer or bus buffer of temporary buffering, the bus driver for providing larger driving force for address signal etc.
Deng in brief, interface chip is for ensuring that the safety and stability of data transmission procedure.
However, during data transfer, the input interface of interface chip can cannot determine interface because of loose contact
Effectively whether, now, the output interface of interface chip but still can export the determination signal of " 0 " or " 1 " to the input data of chip,
And by the middle of its signal transmission to microprocessor；However, due to the loose contact of input interface, making the input data of interface chip
Real data can not be reflected, so as to the output data for causing interface chip is nonsensical.How interface chip is obtained
The validity of upper input data, so as to decide whether to accept and believe the output data on interface chip, becomes for people's research
Individual problem.
In digital circuit, digital circuit typically has three kinds of output states, is high level, low level and high-impedance state, wherein
High level is logical one, and low level is logical zero, and high-impedance state is equivalent to cut-off state；Wherein by logical one and logical zero group
Into binary signal, be the major way of current electronic chip data transfer inside, and if the input interface of interface chip
In the case of hanging or loose contact, high-impedance state will be formed, this is based on, if can carry out by the input of docking port chip
The test of high-impedance state obtaining the validity of input data on interface chip, so as to avoid cannot judging whether output data has
The technical problem of effect.
Therefore, it is necessary to provide the circuit that a kind of input energy detects input data validity.
Utility model content
The utility model is a kind of multi input data mode parallel detection with threshold value numerical control of offer that solves the above problems
Circuit, is respectively compared by the input voltage signal to multiple Data Input Interfaces, according to the output data of door sentencing
Whether whether the input data of disconnected Data Input Interface is effective, it is achieved thereby that having to the input data of multiple Data Input Interfaces
The parallel detection of effect.
For achieving the above object, the effect above is reached, the utility model is achieved through the following technical solutions：
A kind of multi input data mode parallel detection circuit with threshold value numerical control, the detection circuit includes and multiple data
Input interface detects correspondingly branch；The detection branch includes biasing circuit, first threshold comparing unit, Second Threshold ratio
Compared with unit；Wherein biasing circuit includes the resistance of two series connection, and node between the resistances is connected with Data Input Interface,
The node is connected with the first input end of first threshold comparing unit, Second Threshold comparing unit；First threshold comparing unit,
Second input of two threshold value comparing units is connected respectively with a threshold voltage signal generating unit, first threshold comparing unit,
The output end of two threshold value comparing units connects one to one with two inputs of gate circuit, the gate circuit in each detection branch
Output end be connected to one with the input of door on, according to the output data of door judging the input number of Data Input Interface
According to whether effective.
Used as preferred, gate circuit is same OR gate or XOR gate.
As preferred, in order to detect circuit output state for high level, low level or high-impedance state, threshold voltage generation
Unit includes high threshold voltage signal generating unit, low threshold voltage signal generating unit, high threshold voltage signal generating unit, low threshold voltage
Signal generating unit is connected with digital interface control unit, by the second input connection high threshold voltage life of first threshold comparing unit
Into unit, the second input connection low threshold voltage signal generating unit of Second Threshold comparing unit, generate from high threshold voltage single
Unit, low threshold voltage signal generating unit upload the benchmark for being input into next high and low level voltage threshold value as comparator.
Used as preferred, the output end of first threshold comparing unit or Second Threshold comparing unit is selected one and is connect with data output
Mouthful connection, will input data be transferred in next stage circuit.
As preferred, because the span of high and low level is two extreme, so the biasing circuit for producing takes centre
Scheme preferably, so making the resistance of two resistance equal, and makes one of resistance be connected with power supply during value, another resistance and
Ground connection, so that the bias voltage that intermediate node is produced is the median of circuit voltage.
Used as preferred, first threshold comparing unit, the first input end of Second Threshold comparing unit are in-phase end, first
Threshold value comparing unit, the second input of Second Threshold comparing unit are end of oppisite phase, i.e. first threshold comparing unit, Second Threshold
Comparing unit uses positive logic.
As preferred, control signal is received by digital interface control unit, generate high threshold voltage signal generating unit high
Level voltage threshold value, low threshold voltage signal generating unit generates low level voltage threshold value, and the node voltage between two resistance is less than
High level voltage threshold value, and more than low level voltage threshold value, i.e., high and low level voltage threshold value forms three voltage ranges, respectively
Three kinds of states of corresponding circuits output.
As preferred, in order to adapt to different working environment and demand, two resistance can equivalence replacement be two electric currents
Source, one of current source is connected with power supply, and another current source is connected to ground, the current direction of current source be power supply direction extremely
Ground, its objective is to produce bias voltage.
The beneficial effects of the utility model are：
A kind of multi input data mode parallel detection circuit, by detecting input electricity of the branch to multiple Data Input Interfaces
Pressure signal is respectively compared, and the input of the Data Input Interface is judged according to the output data for detecting the gate circuit in branch
Whether effectively the testing result of multiple detection branches, and is carried out computing by data by one with door, and according to the output with door
Whether end data is all effective come the input data for judging multiple Data Input Interfaces, so as to ensure the effective of data transmission procedure
Property, and one or more can occur to be found in time during hanging or loose contact in multiple input interfaces, it is to avoid because collection
Insignificant signal as data caused by failure and time for causing waste.
Described above is only the general introduction of technical solutions of the utility model, in order to better understand skill of the present utility model
Art means, and being practiced according to the content of specification, with preferred embodiment of the present utility model and coordinate accompanying drawing detailed below
Describe in detail it is bright as after, specific embodiment of the present utility model is shown in detail in by following examples and its accompanying drawing.
Description of the drawings
Accompanying drawing described herein is used for providing further understanding to of the present utility model, constitutes the part of the application,
Schematic description and description of the present utility model is used to explain the utility model, does not constitute to of the present utility model improper
Limit.In the accompanying drawings：
Fig. 1 is the physical circuit schematic diagram of the detection branch that the utility model first embodiment is related to；
Fig. 2 is the utility model first embodiment multiple detection branches being related to and the circuit signal being connected between door
Figure；
Fig. 3 is the chip interface containing multi input data mode parallel detection circuit of the utility model with threshold value numerical control
Schematic diagram；
Fig. 4 is the schematic diagram of each position voltage in the detection branch that the utility model first embodiment is related to；
Fig. 5 is the physical circuit schematic diagram that the utility model second applies the detection branch that example is related to；
Fig. 6 is the physical circuit schematic diagram of the detection branch that the utility model 3rd embodiment is related to；
Fig. 7 is the physical circuit schematic diagram of the detection branch that the utility model fourth embodiment is related to.
Wherein, 1 is high threshold voltage signal generating unit, and 2 is low threshold voltage signal generating unit, and 3 is digital interface control unit,
IN、IN1-IN4For Data Input Interface, Dout、Dout1- Dout4For data output interface, DINSConnect for data input State- output
Mouthful, VSFor threshold value control interface, VCCFor the power supply of circuit, GND is earth terminal, R1-R2For resistance, IS1、IS2For electric current
Source, A1For first threshold comparing unit, A2For Second Threshold comparing unit, DINS1For the first data input State- output interface,
DINSXFor X data input State- output interfaces, DINSNFor Nth data input state output interface, ST is many data input states
Total output interface.
Wherein, the voltage of each position is described as follows in Fig. 4：VINFor input voltage, VbiasFor bias voltage, VA1+For first
Threshold value comparing unit A1The input voltage of in-phase end, VA1-For first threshold comparing unit A1The input voltage of end of oppisite phase, VA2+For
Two threshold value comparing unit A2The input voltage of in-phase end, VA2-For Second Threshold comparing unit A2The input voltage of end of oppisite phase, Vouta
For first threshold comparing unit A1Output voltage, VoutbFor Second Threshold comparing unit A2Output voltage, VrefhFor high threshold
Input voltage, VreflFor Low threshold input voltage, VoutFor output voltage, VINSFor data input state-detection voltage.
Specific embodiment
Below with reference to the accompanying drawings and in conjunction with the embodiments describing the utility model in detail：
As shown in Figures 1 to 4 for first embodiment of the present utility model, wherein Fig. 1 is detection point in first embodiment
The physical circuit schematic diagram on road；The detection branch includes biasing circuit, first threshold comparing unit A1, Second Threshold comparing unit
A2；Wherein biasing circuit includes the resistance R of two series connection1、R2, resistance R1With the power supply V of circuitCCConnection, resistance R2With connect
Ground terminal GND connects, in resistance R1、R2Between node be connected with Data Input Interface IN.
As shown in figure 1, first threshold comparing unit A1, Second Threshold comparing unit A2Use positive logic so that with data
The node of input interface IN and first threshold comparing unit A1, Second Threshold comparing unit A2First input end connection, and two
The first input end of comparing unit is in-phase end；Second input of two comparing units is end of oppisite phase, wherein first threshold
Comparing unit A1The second input connection high threshold voltage signal generating unit 1, Second Threshold comparing unit A2The second input connect
Low threshold voltage signal generating unit 2 is connect, meanwhile, high threshold voltage signal generating unit 1, low threshold voltage signal generating unit 2 and digital interface
Control unit 3 connects, and digital interface control unit 3 is to being externally connected with threshold value control interface VS；First threshold comparing unit A1,
Two threshold value comparing unit A2Output end connect one to one with two inputs of same OR gate, with the output end and data of OR gate
Input state output interface DINSConnection, first threshold comparing unit A1Output end simultaneously with data output interface DoutConnection.
As shown in Fig. 2 the output end of the same OR gate in each detection branch be connected to one with the input of door on, and tie
Fig. 3 is closed, the detection object of first embodiment of the present utility model is 4 Data Input Interfaces, respectively Data Input Interface
IN1-IN4, i.e. N=4 in Fig. 2, after corresponding detection branch, the corresponding data output interface D of outputout1-Dout4, input
State- output interface DINS1- DINS4；Input state output interface DINS1- DINS4Be both connected to one with the input of door on, should
The total output interface ST of data input state more than is connected with the output end of door.
Wherein, by threshold value control interface VSThreshold control signal is transferred in digital interface control unit 3, so as to control
High threshold voltage signal generating unit 1 processed, low threshold voltage signal generating unit 2 generate respectively high level voltage threshold value Vrefh, low level electricity
Pressure threshold value Vrefl, wherein high level voltage threshold value VrefhIt is disposed proximate to but less than the lower limit of high level voltage, low level voltage
Threshold value VreflIt is disposed proximate to but more than the lower limit of low level voltage, resistance R1、R2Between node voltage less than high level electricity
Pressure threshold value Vrefh, and more than low level voltage threshold value Vrefl, that is, three voltage ranges are formed, respectively more than high level voltage threshold
Value VrefhInterval, in high level voltage threshold value VrefhWith low level voltage threshold value VreflBetween it is interval and less than low electricity
Flat voltage threshold VreflInterval, and respectively three kinds of states of corresponding circuits output.
Meanwhile, in order to ensure more preferably Detection results, make resistance R1、R2Resistance it is equal, and resistance R1、R2Resistance is very
Greatly, so as in the ideal case, the bias voltage V of generationbiasFor the power supply V of circuitCC1/2nd, and the biased electrical
Electric current very little on road so as to which the impact caused by the high and low level of input data is ignored.
In order to better illustrate the course of work of detection branch, coordinate each position voltage schematic diagram such as in Fig. 4, data are defeated
Circuit analysis under the upper three kinds of forms of incoming interface IN is as follows：
（1）, when Data Input Interface IN state in which be high level when, VA1+ =VA2+=VIN=VIH（Input high level）,
VA1- =Vrefh, VA2-=Vrefl, due to VIH> VrefhAnd VIH> Vrefl, so that first threshold comparing unit A1Output voltage
Vouta, Second Threshold comparing unit A2Output voltage VoutbHigh level is, after same OR gate computing, the data for obtaining are defeated
Enter state-detection voltage VINSFor high level, that is, the logical value for exporting is 1.
（2）, when Data Input Interface IN state in which be low level when, VA1+ =VA2+=VIN=VIL（Input low level）,
VA1- =Vrefh, VA2-=Vrefl, due to VIL<VrefhAnd VIL <Vrefl, so that first threshold comparing unit A1Output voltage
Vouta, Second Threshold comparing unit A2Output voltage VoutbLow level is, after same OR gate computing, the data for obtaining are defeated
Enter state-detection voltage VINSFor high level, that is, the logical value for exporting is 1.
（3）, when Data Input Interface IN state in which is high-impedance state, be equal on Data Input Interface IN without outer
Connect, now, VA1+ =VA2+=Vbias, due to Vrefl < Vbias < Vrefh, so that first threshold comparing unit A1Output voltage
VoutaFor low level, Second Threshold comparing unit A2Output voltage VoutbFor high level, i.e. first threshold comparing unit A1Output
Logical value be 0, Second Threshold comparing unit A2The logical value of output is 1, after same OR gate computing, the data input for obtaining
State-detection voltage VINSFor low level, that is, the logical value for exporting is 0.
In sum, as multiple data input state-detection voltage VINSOutput logical value when being 1, through and door
The output logical value obtained after computing is 1, and multiple Data Input Interface IN state in which are high level or low level, i.e., many
The input data logic of individual Data Input Interface IN is effectively, and logically, output voltage VoutWith input voltage VINPhase
Deng the output interface D therefore the next stage circuit being connected with the detection circuit is fetched dataoutOutput data as the next stage circuit
Input data；As multiple data input state-detection voltage VINSOutput logical value in have one for 0 when, Jing Guoyu
The output logical value obtained after the computing of door is 0, is had in multiple Data Input Interface IN residing for a Data Input Interface IN
State is high-impedance state, i.e., the input data logic of multiple Data Input Interface IN is invalid, therefore next with what the detection circuit was connected
Level circuit stops accepting and believing the output data.
Fig. 5 is that the utility model second applies the physical circuit schematic diagram that branch is detected in example, compared with first embodiment
Difference is：First threshold comparing unit A1, Second Threshold comparing unit A2First input end be end of oppisite phase；First threshold
Comparing unit A1, Second Threshold comparing unit A2The second input be in-phase end, when Data Input Interface IN state in which is
During high level, first threshold comparing unit A1, Second Threshold comparing unit A2The logical value of output is 0, works as Data Input Interface
When IN state in which is low level, first threshold comparing unit A1, Second Threshold comparing unit A2The logical value of output is 1,
I.e. export logical value with input logic value the output interface conversely, the next stage circuit being now connected with the detection circuit is fetched data
DoutOutput data NAND gate computing after result as the next stage circuit input data, remaining is with reference to above-mentioned pass
In the description of first embodiment.
Fig. 6 is the physical circuit schematic diagram that branch is detected in the utility model 3rd embodiment, and the detection branch includes inclined
Circuits, first threshold comparing unit A1, Second Threshold comparing unit A2；Wherein biasing circuit includes the current source of two series connection
IS1、IS2, current source IS1With the power supply V of circuitCCConnection, current source IS2It is connected with earth terminal GND, in current source IS1、
IS2Between node be connected with Data Input Interface IN, i.e., the utility model 3rd embodiment is on the basis of first embodiment
On, by the resistance R on biasing circuit1、R2Replace with current source IS1、IS2, remaining is with reference to above-mentioned retouching with regard to first embodiment
State.
Fig. 7 be the utility model fourth embodiment in detect branch physical circuit schematic diagram, first threshold comparing unit
A1, Second Threshold comparing unit A2Output end connect one to one with two inputs of XOR gate, the output end of XOR gate with
Data input State- output interface DINSConnection, now, as data input state-detection voltage VINSOutput logical value be 0 when,
The input data logical validity of Data Input Interface IN；As data input state-detection voltage VINSOutput logical value be 1 when,
The input data logic of Data Input Interface IN is invalid, i.e., fourth embodiment of the present utility model is on the basis of first embodiment
On, XOR gate will be replaced with OR gate so that the correspondence of output logical value and validity is with first embodiment conversely, remaining reference
The above-mentioned description with regard to first embodiment.
Meanwhile, by the exchange of in-phase end and end of oppisite phase in second embodiment, by resistance R in 3rd embodiment1、R2Replace with
Current source IS1、IS2, same OR gate is replaced with the form of XOR gate in fourth embodiment, it is on the basis of first embodiment
The replacement for carrying out, three kinds of substitute modes can freely form new embodiment, such as the 5th embodiment：In first embodiment
On the basis of, by resistance R1、R2Replace with current source IS1、IS2, XOR gate will be replaced with OR gate, the 5th enforcement for so being formed
Example be implement to the 3rd, the simple combination of fourth embodiment, it is such combine new embodiment be it is of the present utility model etc.
Effect embodiment；In addition, detection object is 4 Data Input Interfaces in the utility model first embodiment, can not constitute to this
The restriction of utility model, by 42 any of the above numeral is revised as, and is Equivalent embodiments of the present utility model.
The above, preferred embodiment only of the present utility model not makees any formal to the utility model
Restriction；The those of ordinary skill of all industry can shown in by specification accompanying drawing and the above and swimmingly implement this practicality
It is new；But, all those skilled in the art are taken off in the range of without departing from technical solutions of the utility model using more than
The technology contents that show and a little change, modification and the equivalent variations for developing made, are Equivalent embodiments of the present utility model；
Meanwhile, the change of all above example is made any equivalent variations according to substantial technological of the present utility model, modify and drill
Become etc., still fall within the protection domain of the technical solution of the utility model.
Claims (8)
1. a kind of multi input data mode parallel detection circuit with threshold value numerical control, it is characterised in that：The detection circuit includes
Branch is detected correspondingly with multiple Data Input Interfaces；The detection branch includes that biasing circuit, first threshold are more single
Unit, Second Threshold comparing unit；The biasing circuit includes the resistance of two series connection, the node and number between two resistance
It is connected according to input interface, the node for connecting the Data Input Interface compares with the first threshold comparing unit, Second Threshold
The first input end connection of unit；The first threshold comparing unit, Second Threshold comparing unit the second input respectively with
One threshold voltage signal generating unit connection, the first threshold comparing unit, the output end of Second Threshold comparing unit and door electricity
Two inputs on road connect one to one, and the output end of the gate circuit in each detection branch is connected to one with door
On input, according to whether effective to judge the input data of Data Input Interface with the output data of door.
2. the multi input data mode parallel detection circuit with threshold value numerical control according to claim 1, it is characterised in that：
The gate circuit is same OR gate or XOR gate, and the output end of the gate circuit is connected with data input State- output interface.
3. the multi input data mode parallel detection circuit with threshold value numerical control according to claim 1, it is characterised in that：
The threshold voltage signal generating unit includes high threshold voltage signal generating unit（1）, low threshold voltage signal generating unit（2）, the height
Threshold voltage signal generating unit（1）, low threshold voltage signal generating unit（2）With digital interface control unit（3）Connection, first threshold
The second input connection high threshold voltage signal generating unit of value comparing unit（1）, the second of the Second Threshold comparing unit be defeated
Enter end connection low threshold voltage signal generating unit（2）.
4. the multi input data mode parallel detection circuit with threshold value numerical control according to claim 1, it is characterised in that：
The output end of the first threshold comparing unit or the Second Threshold comparing unit is selected one and is connected with data output interface.
5. the multi input data mode parallel detection circuit with threshold value numerical control according to claim 1, it is characterised in that：
The resistance of two resistance is equal, and one of them described resistance is connected with power supply, and another described resistance is connected to ground.
6. the multi input data mode parallel detection circuit with threshold value numerical control according to claim 1, it is characterised in that：
The first threshold comparing unit, the first input end of Second Threshold comparing unit are in-phase end, and the first threshold is more single
Unit, the second input of Second Threshold comparing unit are end of oppisite phase.
7. the multi input data mode parallel detection circuit with threshold value numerical control according to claim 3, it is characterised in that：
Control signal is received by the digital interface control unit, the high threshold voltage signal generating unit is made（1）Generate high level voltage
Threshold value, the low threshold voltage signal generating unit（2）Low level voltage threshold value is generated, the node voltage between two resistance is little
In high level voltage threshold value, and more than low level voltage threshold value.
8. according to one of them described multi input data mode parallel detection circuit with threshold value numerical control of claim 1 to 7,
It is characterized in that：Two resistance can equivalence replacement be two current sources, one of them described current source is connected with power supply, separately
One current source is connected to ground, and the current direction of the current source is power supply direction to ground.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201621047570.7U CN206135875U (en) | 2016-09-10 | 2016-09-10 | Many input data state detection circuitry that walks abreast with threshold value numerical control |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201621047570.7U CN206135875U (en) | 2016-09-10 | 2016-09-10 | Many input data state detection circuitry that walks abreast with threshold value numerical control |
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| CN201621047570.7U Expired - Fee Related CN206135875U (en) | 2016-09-10 | 2016-09-10 | Many input data state detection circuitry that walks abreast with threshold value numerical control |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113743043A (en) * | 2021-09-18 | 2021-12-03 | 苏州盛科通信股份有限公司 | Data combination method, chip and device |
| CN116165471A (en) * | 2023-04-20 | 2023-05-26 | 泉州昆泰芯微电子科技有限公司 | Signal overload monitoring system, monitoring method and programmable gain amplifier |
-
2016
- 2016-09-10 CN CN201621047570.7U patent/CN206135875U/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113743043A (en) * | 2021-09-18 | 2021-12-03 | 苏州盛科通信股份有限公司 | Data combination method, chip and device |
| CN116165471A (en) * | 2023-04-20 | 2023-05-26 | 泉州昆泰芯微电子科技有限公司 | Signal overload monitoring system, monitoring method and programmable gain amplifier |
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