CN106452419A - Input data state detection circuit with switch control - Google Patents
Input data state detection circuit with switch control Download PDFInfo
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- CN106452419A CN106452419A CN201610814294.0A CN201610814294A CN106452419A CN 106452419 A CN106452419 A CN 106452419A CN 201610814294 A CN201610814294 A CN 201610814294A CN 106452419 A CN106452419 A CN 106452419A
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- threshold values
- input
- comparing unit
- data
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/017509—Interface arrangements
Abstract
The invention discloses an input data state detection circuit with switch control. The detection circuit comprises a bias circuit, a first threshold comparison unit and a second threshold comparison unit; wherein the bias circuit comprises two resistors connected in series, a node between the two resistors is connected with a data input interface, and the two resistors are separately connected with a switch on both sides of the node; the node is connected with first input ends of the first threshold comparison unit and the second threshold comparison unit; second input ends of the first threshold comparison unit and the second threshold comparison unit are separately connected with a threshold input interface, and output ends of the input ends of the first threshold comparison unit and the second threshold comparison unit are in one-to-one correspondence connection with two input ends of a gate circuit; and the input data state detection circuit disclosed by the invention compares input voltage signals of the data input interface and judges whether the input data of the data input interface are effective according to output data of the gate circuit so as to detect whether the input data of the data input interface are effective.
Description
Technical field
The present invention relates to integrated circuit fields, more particularly, to a kind of input data state-detection electricity with switch control rule
Road.
Background technology
Since mankind's nineteen forty-seven invention transistor, between more than 50 year, semiconductor technology experienced silicon transistor, integrated electricity
The several generations such as road, super large-scale integration, very large scale integration, development speed is that other industries are unexistent soon；In
Central processor refers to the part that computer-internal is processed to data and processing procedure is controlled, and collects along with extensive
Become the developing rapidly of circuit engineering, integrated chip density more and more higher, CPU can integrated on a semiconductor chip in a, this
There are the LSI devices of central processing unit function, be collectively referred to as " microprocessor "；Either video recorder, intelligence are washed
The household appliances such as clothing machine, mobile phone, or car engine controls, and Digit Control Machine Tool, guided missile precise guidance etc. will embed
All kinds of different microprocessors；Microprocessor is not only the core component of microcomputer, is also various digital intelligent equipment
Critical component.
And interface chip, it is for connecting a kind of electronic devices and components between microprocessor and memory, it includes number
According to the data buffer of temporary buffering or bus buffer, provide bus driver of larger driving force etc. for address signal
Deng in brief, interface chip is for ensuring that safety and the stability of data transmission procedure.
However, during data transfer, the input interface of interface chip can cannot determine interface because of loose contact
Effectively whether, now, the output interface of interface chip but still can export the determination signal of " 0 " or " 1 " to the input data of chip,
And by the middle of its signal transmission to microprocessor；However, due to the loose contact of input interface, making the input data of interface chip
Real data can not be reflected, thus leading to the output data of interface chip to be nonsensical.How to obtain interface chip
The validity of upper input data, thus deciding whether to accept and believe the output data on interface chip, becomes for people's research
Individual problem.
In digital circuit, digital circuit typically has three kinds of output states, is high level, low level and high-impedance state, wherein
High level is logical one, and low level is logical zero, and high-impedance state is equivalent to cut-off state；Wherein by logical one and logical zero group
The binary signal becoming, is the major way of current electronic chip data transfer inside, and if the input interface of interface chip
Vacantly or in the case of loose contact, high-impedance state will be formed, be based on this, if can be carried out by the input of docking port chip
The test of high-impedance state, to obtain the validity of input data on interface chip, thus avoiding judging whether output data has
The technical problem of effect.
Therefore, it is necessary to provide a kind of input energy to detect the circuit of input data validity.
Content of the invention
The present invention provides a kind of input data state detection circuit with switch control rule for solving the above problems, by right
The input voltage signal of Data Input Interface is compared, and the output data according to gate circuit is judging the defeated of Data Input Interface
Whether effectively enter data, thus detect Data Input Interface input data whether effective.
For achieving the above object, reach the effect above, the present invention is achieved through the following technical solutions：
A kind of input data state detection circuit with switch control rule, this testing circuit includes biasing circuit, the first threshold values ratio
Compared with unit, the second threshold values comparing unit；Wherein biasing circuit includes the resistance of two series connection, node between the resistances with
Data Input Interface is connected, and the both sides in node, and two described resistance are connected to a switch, and described switch is connected with out
Close control interface；This node is connected with the first input end of the first threshold values comparing unit, the second threshold values comparing unit；First threshold values
Comparing unit, the second input of the second threshold values comparing unit are connected with a threshold values input interface respectively, and the first threshold values compares
Two inputs of unit, the output end of the second threshold values comparing unit and gate circuit connect one to one, defeated according to gate circuit
Go out data whether effective come the input data to judge Data Input Interface.
As preferred, gate circuit is same OR gate or XOR gate.
As preferred, in order to detect that circuit output state is high level, low level or high-impedance state, threshold values input interface
Include high threshold values input interface, low valve valve input interface, the second input of the first threshold values comparing unit is connected high threshold values
Input interface, the second input of the second threshold values comparing unit connects low valve valve input interface, from high threshold values input interface, low valve
Value input interface uploads the benchmark being input into the high and low level voltage threshold values coming as comparator.
As preferred, the output end of the first threshold values comparing unit or the second threshold values comparing unit is selected one and is connect with data output
Mouth connects, and will input data be transferred in next stage circuit.
As preferred, when input data is effective, the next stage circuit being connected with this circuit will continue to gather this data
Signal；When input data is invalid, the next stage circuit being connected with this circuit will stop gathering this data-signal.
As preferred, because the span of high and low level is extreme for two, so the biasing circuit producing takes centre
During value scheme preferably, so make two resistance resistance equal, and so that one of resistance is connected with power supply, another resistance and
Ground connects, so that the bias voltage that intermediate node produces is the median of circuit voltage.
As preferred, the first threshold values comparing unit, the first input end of the second threshold values comparing unit are in-phase end, first
Threshold values comparing unit, the second input of the second threshold values comparing unit are end of oppisite phase, i.e. the first threshold values comparing unit, the second threshold values
Comparing unit is all using positive logic.
As preferred, high threshold values input interface putting high level voltage threshold values, low valve valve input interface input low level
Threshold voltage, the node voltage between two resistance is less than high level voltage threshold values, and is more than low level voltage threshold values, that is, high,
Low level voltage threshold values forms three voltage ranges, respectively three kinds of states of corresponding circuits output.
As preferred, in order to adapt to different working environments and demand, two resistance can equivalence replacement be two electric currents
Source, one of current source is connected with power supply, and another current source is connected to ground, and the current direction of current source is for power supply direction extremely
Ground, its objective is to produce bias voltage.
The invention has the beneficial effects as follows：
A kind of input data state detection circuit with switch control rule, by entering to the input voltage signal of Data Input Interface
Row compares, and whether the output data according to gate circuit is effective come the input data judging Data Input Interface, thus ensureing data
The validity of transmitting procedure, and can find in time when input interface occurs hanging or loose contact, it is to avoid because collection is no
The fault that the signal of meaning is led to as data.
Described above is only the general introduction of technical solution of the present invention, in order to better understand the technological means of the present invention,
And can be practiced according to the content of specification, below with presently preferred embodiments of the present invention and coordinate accompanying drawing describe in detail as after,
The specific embodiment of the present invention is shown in detail in by following examples and its accompanying drawing.
Brief description
Accompanying drawing described herein is used for providing a further understanding of the present invention, constitutes the part of the application, this
Bright schematic description and description is used for explaining the present invention, does not constitute inappropriate limitation of the present invention.In the accompanying drawings：
The physical circuit of the input data state detection circuit with switch control rule that Fig. 1 is related to for first embodiment of the invention shows
It is intended to；
Fig. 2 is the chip of input data state detection circuit and the showing of part peripheral circuit carrying switch control rule containing the present invention
It is intended to；
Each position voltage in the input data state detection circuit with switch control rule that Fig. 3 is related to for first embodiment of the invention
Schematic diagram；
The physical circuit that Fig. 4 applies, for the present invention second, the input data state detection circuit with switch control rule that example is related to is illustrated
Figure；
The physical circuit of the input data state detection circuit with switch control rule that Fig. 5 is related to for third embodiment of the invention shows
It is intended to；
The physical circuit of the input data state detection circuit with switch control rule that Fig. 6 is related to for fourth embodiment of the invention shows
It is intended to.
Wherein, IN is Data Input Interface, IKSFor switch control interface, DoutFor data output interface, DINSDefeated for data
Enter State- output interface, VHFor high threshold values input interface, VLFor low valve valve input interface, VCCFor the power supply of circuit, GND is
Earth terminal, R1-R6For resistance, IS1、IS2For current source, K1、K2For switch, A1For the first threshold values comparing unit, A2For the second threshold values
Comparing unit.
Wherein, in Fig. 3, the voltage of each position is described as follows：VINFor input voltage, VbiasFor bias voltage, VA1+For first
Threshold values comparing unit A1The input voltage of in-phase end, VA1-For the first threshold values comparing unit A1The input voltage of end of oppisite phase, VA2+For
Two threshold values comparing unit A2The input voltage of in-phase end, VA2-For the second threshold values comparing unit A2The input voltage of end of oppisite phase, Vouta
For the first threshold values comparing unit A1Output voltage, VoutbFor the second threshold values comparing unit A2Output voltage, VrefhFor high threshold values
Input voltage, VreflFor low valve valve input voltage, VoutFor output voltage, VINSFor data input state-detection voltage.
Specific embodiment
Below with reference to the accompanying drawings and in conjunction with the embodiments, to describe the present invention in detail：
As shown in Figure 1 to Figure 3 for the first embodiment of the present invention, wherein Fig. 1 is the physical circuit schematic diagram of first embodiment；
This testing circuit includes biasing circuit, the first threshold values comparing unit A1, the second threshold values comparing unit A2；Wherein biasing circuit includes
The resistance R of two series connection1、R2, resistance R1One end and circuit power supply VCCConnection, the other end and switch K1Connect, resistance
R2One end be connected with earth terminal GND, the other end with switch K2Connect, in switch K1、K2Between node and Data Input Interface
IN is connected.
As shown in figure 1, the first threshold values comparing unit A1, the second threshold values comparing unit A2All using positive logic so that and data
The node of input interface IN and the first threshold values comparing unit A1, the second threshold values comparing unit A2First input end connect, and two
The first input end of comparing unit is in-phase end；Second input of two comparing units is end of oppisite phase, the wherein first threshold values
Comparing unit A1Second input connect high threshold values input interface VH, the second threshold values comparing unit A2Second input connect
Low valve valve input interface VL；First threshold values comparing unit A1, the second threshold values comparing unit A2Output end defeated with two of same OR gate
Enter end to connect one to one, with output end and the data input State- output interface D of OR gateINSConnect, the first threshold values comparing unit
A1Output end simultaneously with data output interface DoutConnect.
Shown in Fig. 2 is the schematic diagram of the chip containing the present invention and part peripheral circuit, resistance R3、R4Between formed
Node and high threshold values input interface VHConnect, resistance R5、R6Between the node and the low valve valve input interface V that are formedLConnect, pass through
Resistance R3、R4Between, resistance R5、R6Between formed proportionate relationship, thus generate with this testing circuit voltage be adapted height,
Low level voltage threshold values, and using high and low level voltage threshold values as benchmark.
And among these, high level voltage threshold values VrefhIt is disposed proximate to but the lower limit less than high level voltage, low level
Threshold voltage VreflIt is disposed proximate to but the lower limit more than low level voltage, resistance R1、R2Between node voltage be less than high electricity
Flat threshold voltage Vrefh, and it is more than low level voltage threshold values Vrefl, that is, form three voltage ranges, be respectively more than high level electricity
Pressure valve value VrefhInterval, be in high level voltage threshold values VrefhWith low level voltage threshold values VreflBetween interval and be less than
Low level voltage threshold values VreflInterval, and three kinds of states of respectively corresponding circuits output.
Meanwhile, in order to ensure more preferably Detection results, make resistance R1、R2Resistance equal, and resistance R1、R2Resistance is very
Greatly, thus in the ideal case, the bias voltage V of generationbiasPower supply V for circuitCC1/2nd, and this biased electrical
Electric current very little on road is so as to ignore to the impact caused by the high and low level of input data.
In order to better illustrate the course of work of whole circuit, in switch K1、K2In the case of closure, every in cooperation Fig. 3
Put voltage schematic diagram such as, the circuit analysis under the upper three kinds of forms of Data Input Interface IN is as follows：
（1）, when Data Input Interface IN state in which be high level when, VA1+=VA2+=VIN=VIH（Input high level）, VA1-
=Vrefh, VA2-=Vrefl, due to VIH> VrefhAnd VIH> Vrefl, so that the first threshold values comparing unit A1Output voltage Vouta、
Second threshold values comparing unit A2Output voltage VoutbIt is high level, after same OR gate computing, the data input state that obtains
Detection voltage VINSFor high level, that is, the logical value exporting is 1.
（2）, when Data Input Interface IN state in which be low level when, VA1+=VA2+=VIN=VIL（Input low level）,
VA1-=Vrefh, VA2-=Vrefl, due to VIL<VrefhAnd VIL<Vrefl, so that the first threshold values comparing unit A1Output voltage
Vouta, the second threshold values comparing unit A2Output voltage VoutbIt is low level, after same OR gate computing, the data obtaining is defeated
Enter state-detection voltage VINSFor high level, that is, the logical value exporting is 1.
（3）, when Data Input Interface IN state in which is high-impedance state, be equal on Data Input Interface IN not outer
Connect, now, VA1+=VA2+=Vbias, due to Vrefl< Vbias< Vrefh, so that the first threshold values comparing unit A1Output voltage
VoutaFor low level, the second threshold values comparing unit A2Output voltage VoutbFor high level, i.e. the first threshold values comparing unit A1Output
Logical value be 0, the second threshold values comparing unit A2The logical value of output is 1, after same OR gate computing, the data input that obtains
State-detection voltage VINSFor low level, that is, the logical value exporting is 0.
In sum, as data input state-detection voltage VINSOutput logical value be 1 when, Data Input Interface IN institute
The state at place is high level or low level, i.e. the input data logical validity of Data Input Interface IN, and logically, output
Voltage VoutWith input voltage VINEqual, the output interface D therefore the next stage circuit being connected with this testing circuit is fetched dataoutOutput
Data is as the input data of this next stage circuit；As data input state-detection voltage VINSOutput logical value be 0
When, Data Input Interface IN state in which be high-impedance state, that is, the input data logic of Data Input Interface IN is invalid, thus with this
The next stage circuit that testing circuit connects stops accepting and believing this output data.
As switch K1、K2In the case of disconnecting, then close the detection function of input data validity.
Fig. 4 applies the physical circuit schematic diagram of example for the present invention second, and the difference compared with first embodiment is：First valve
Value comparing unit A1, the second threshold values comparing unit A2First input end be end of oppisite phase；First threshold values comparing unit A1, second
Threshold values comparing unit A2The second input be in-phase end, when Data Input Interface IN state in which be high level when, first
Threshold values comparing unit A1, the second threshold values comparing unit A2The logical value of output is 0, when Data Input Interface IN state in which
During for low level, the first threshold values comparing unit A1, the second threshold values comparing unit A2The logical value of output is 1, that is, export logical value
Contrary with input logic value, the next stage circuit that is now connected with this testing circuit is fetched data output interface DoutOutput data
As the input data of this next stage circuit, remaining is with reference to above-mentioned with regard to first embodiment for result after NAND gate computing
Description.
Fig. 5 is the physical circuit schematic diagram of third embodiment of the invention, and this testing circuit includes biasing circuit, the first threshold values
Comparing unit A1, the second threshold values comparing unit A2；Wherein biasing circuit includes the current source IS of two series connection1、IS2, current source IS1
Power supply V with circuitCCConnect, current source IS2It is connected with earth terminal GND, in current source IS1、IS2Between node and number
It is connected according to input interface IN, that is, third embodiment of the invention is on the basis of first embodiment, by the resistance on biasing circuit
R1、R2Replace with current source IS1、IS2, remaining is with reference to the above-mentioned description with regard to first embodiment.
Fig. 6 is the physical circuit schematic diagram of fourth embodiment of the invention, the first threshold values comparing unit A1, the second threshold values compares
Unit A2Output end connect one to one with two inputs of XOR gate, the output end of XOR gate is defeated with data input state
Outgoing interface DINSConnect, now, as data input state-detection voltage VINSOutput logical value be 0 when, Data Input Interface IN
Input data logical validity；As data input state-detection voltage VINSOutput logical value be 1 when, Data Input Interface IN
Input data logic invalid, that is, the fourth embodiment of the present invention is on the basis of first embodiment, will replace with OR gate
, so that the correspondence of output logical value and validity is contrary with first embodiment, remaining is with reference to above-mentioned with regard to the first enforcement for XOR gate
The description of example.
Meanwhile, by the exchange of in-phase end and end of oppisite phase in second embodiment, by resistance R in 3rd embodiment1、R2Replace with
Current source IS1、IS2, in fourth embodiment, same OR gate is replaced with the form of XOR gate, is all on the basis of first embodiment
The single replacement carrying out, this three kinds of substitute modes can freely form new embodiment, the such as the 5th embodiment：In the first enforcement
On the basis of example, by resistance R1、R2Replace with current source IS1、IS2, XOR gate, the 5th so being formed will be replaced with OR gate
Embodiment be implement to the 3rd, the simple combination of fourth embodiment, such combine new embodiment be the present invention etc.
Effect embodiment.
The above, only presently preferred embodiments of the present invention, not the present invention is made with any pro forma restriction；All
The those of ordinary skill of the industry all can shown in by specification accompanying drawing and the above and swimmingly implement the present invention；But, all
Those skilled in the art, in the range of without departing from technical solution of the present invention, are done using disclosed above technology contents
The a little change going out, the equivalent variations modified and develop, are the Equivalent embodiments of the present invention；Meanwhile, all according to the present invention
The change of any equivalent variations, modification and differentiation that substantial technological is made to above example etc., all still fall within the skill of the present invention
Within the protection domain of art scheme.
Claims (9)
1. a kind of input data state detection circuit with switch control rule it is characterised in that：This testing circuit includes biased electrical
Road, the first threshold values comparing unit, the second threshold values comparing unit；Described biasing circuit includes the resistance of two series connection, described in two
Node between resistance is connected with Data Input Interface, and the both sides in node, and two described resistance are connected to a switch,
Described switch is connected with switch control interface；Connect the node of described Data Input Interface and described first threshold values comparing unit,
The first input end of the second threshold values comparing unit connects；Described first threshold values comparing unit, the second of the second threshold values comparing unit
Input is connected with a threshold values input interface respectively, described first threshold values comparing unit, the output of the second threshold values comparing unit
End and two inputs of gate circuit connect one to one, and the output data according to described gate circuit is judging Data Input Interface
Input data whether effective.
2. the input data state detection circuit with switch control rule according to claim 1 it is characterised in that：Described door
Circuit is same OR gate or XOR gate, and the output end of described gate circuit is connected with data input State- output interface.
3. the input data state detection circuit with switch control rule according to claim 1 it is characterised in that：Described valve
Value input interface includes high threshold values input interface, low valve valve input interface, the second input of described first threshold values comparing unit
End connects high threshold values input interface, and the second input of described second threshold values comparing unit connects low valve valve input interface.
4. the input data state detection circuit with switch control rule according to claim 1 it is characterised in that：Described
The output end of one threshold values comparing unit or described second threshold values comparing unit is selected one and is connected with data output interface.
5. the input data state detection circuit with switch control rule according to claim 1 it is characterised in that：Work as input
When data is effective, the next stage circuit being connected with this circuit will continue to gather this data-signal；When input data is invalid, with this
The next stage circuit that circuit connects will stop gathering this data-signal.
6. the input data state detection circuit with switch control rule according to claim 1 it is characterised in that：Two institutes
The resistance stating resistance is equal, and so that one of described resistance is connected with power supply, and another described resistance is connected to ground.
7. the input data state detection circuit with switch control rule according to claim 1 it is characterised in that：Described
One threshold values comparing unit, the first input end of the second threshold values comparing unit are in-phase end, described first threshold values comparing unit, second
Second input of threshold values comparing unit is end of oppisite phase.
8. the input data state detection circuit with switch control rule according to claim 3 it is characterised in that：Described height
Threshold values input interface putting high level voltage threshold values, described low valve valve input interface input low level threshold voltage, described in two
Node voltage between resistance is less than high level voltage threshold values, and is more than low level voltage threshold values.
9. the input data state detection circuit with switch control rule according to one of claim 1 to 8, its feature
It is：Two described resistance can equivalence replacement be two current sources, and one of described current source is connected with power supply, another institute
State current source to be connected to ground, the current direction of described current source is power supply direction to ground.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201610814294.0A CN106452419A (en) | 2016-09-10 | 2016-09-10 | Input data state detection circuit with switch control |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610814294.0A CN106452419A (en) | 2016-09-10 | 2016-09-10 | Input data state detection circuit with switch control |
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| CN106452419A true CN106452419A (en) | 2017-02-22 |
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| CN201610814294.0A Pending CN106452419A (en) | 2016-09-10 | 2016-09-10 | Input data state detection circuit with switch control |
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Cited By (1)
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| CN109375100A (en) * | 2018-12-04 | 2019-02-22 | 深圳世格赛思医疗科技有限公司 | Scalpel switch condition detection circuit and operating table |
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| CN1714496A (en) * | 2002-11-25 | 2005-12-28 | 英特赛尔美国股份有限公司 | Method of setting bi-directional offset in a PWM controller using a single programming pin |
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