CN106341111A - Multiple-input data state parallel detection circuit with intelligent numerical control - Google Patents
Multiple-input data state parallel detection circuit with intelligent numerical control Download PDFInfo
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- CN106341111A CN106341111A CN201610814291.7A CN201610814291A CN106341111A CN 106341111 A CN106341111 A CN 106341111A CN 201610814291 A CN201610814291 A CN 201610814291A CN 106341111 A CN106341111 A CN 106341111A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/017509—Interface arrangements
Abstract
The invention discloses a multiple-input data state parallel detection circuit with intelligent numerical control. The circuit comprises a detection shunt which forms one-to-one correspondence with a plurality of data input interfaces. The detection shunt comprises a bias circuit and two threshold value comparison units. The bias circuit comprises two resistors which are connected in series. The two resistors are connected to one switch respectively. A node between the two switches is connected to data input interfaces. The node is connected to first input terminals of the two threshold value comparison units respectively. Second input terminals are connected to one threshold value voltage generation unit respectively. Output terminals are connected to two input terminals of a gate circuit in a one-to-one correspondence mode. An output terminal of the gate circuit is connected to an input terminal of one AND gate. Through comparing input voltage signals of the plurality of data input interfaces respectively, according to output data of the AND gate, whether input data of the data input interfaces is effective is determined so that whether the input data of the data input interfaces is effective is detected in a parallel mode.
Description
Technical field
The present invention relates to integrated circuit fields, more particularly, to a kind of multi input data mode with intelligent numerical control is examined parallel
Slowdown monitoring circuit.
Background technology
Since mankind's nineteen forty-seven invention transistor, between more than 50 year, semiconductor technology experienced silicon transistor, integrated electricity
The several generations such as road, super large-scale integration, very large scale integration, development speed is that other industries are unexistent soon；In
Central processor refers to the part that computer-internal is processed to data and processing procedure is controlled, and collects along with extensive
Become the developing rapidly of circuit engineering, integrated chip density more and more higher, cpu can integrated on a semiconductor chip in a, this
There are the LSI devices of central processing unit function, be collectively referred to as " microprocessor "；Either videocorder, intelligence are washed
The household appliances such as clothing machine, mobile phone, or car engine controls, and Digit Control Machine Tool, guided missile precise guidance etc. will embed
All kinds of different microprocessors；Microprocessor is not only the core component of microcomputer, is also various digital intelligent equipment
Critical component.
And interface chip, it is for connecting a kind of electronic devices and components between microprocessor and memorizer, it includes number
According to the data buffer of temporary buffering or bus buffer, provide bus driver of larger driving force etc. for address signal
Deng in brief, interface chip is for ensuring that safety and the stability of data transmission procedure.
However, during data transfer, the input interface of interface chip can cannot determine interface because of loose contact
Effectively whether, now, the output interface of interface chip but still can export the determination signal of " 0 " or " 1 " to the input data of chip,
And by the middle of its signal transmission to microprocessor；However, due to the loose contact of input interface, making the input data of interface chip
Real data can not be reflected, thus leading to the output data of interface chip to be nonsensical.How to obtain interface chip
The effectiveness of upper input data, thus deciding whether to accept and believe the output data on interface chip, becomes for people's research
Individual problem.
In digital circuit, digital circuit typically has three kinds of output states, is high level, low level and high-impedance state, wherein
High level is logical one, and low level is logical zero, and high-impedance state is equivalent to cut-off state；Wherein by logical one and logical zero group
The binary signal becoming, is the major way of current electronic chip data transfer inside, and if the input interface of interface chip
Vacantly or in the case of loose contact, high-impedance state will be formed, be based on this, if can be carried out by the input of docking port chip
The test of high-impedance state, to obtain the effectiveness of input data on interface chip, thus avoiding judging whether output data has
The technical problem of effect.
Therefore, it is necessary to provide a kind of input energy to detect the circuit of input data effectiveness.
Content of the invention
The present invention provides a kind of multi input data mode parallel detection circuit with intelligent numerical control for solving the above problems,
By being respectively compared to the input voltage signal of multiple Data Input Interfaces, judged multiple according to the output data with door
Whether the input data of Data Input Interface is all effective, it is achieved thereby that to the input data of multiple Data Input Interfaces whether
Effectively parallel detection.
For achieving the above object, reach the effect above, the present invention is achieved through the following technical solutions:
A kind of multi input data mode parallel detection circuit with intelligent numerical control, this testing circuit includes and multiple data inputs
Interface detects branch correspondingly；It is more single that this detection branch includes biasing circuit, the first threshold values comparing unit, the second threshold values
Unit；Wherein biasing circuit includes the resistance of two series connection, and node between the resistances is connected with Data Input Interface, and
The both sides of node, two described resistance are connected to a switch, and described switch is connected with switch control interface；This node and
One threshold values comparing unit, the first input end of the second threshold values comparing unit connect；First threshold values comparing unit, the second threshold values compare
Second input of unit is connected with a threshold voltage signal generating unit respectively, and the first threshold values comparing unit, the second threshold values compare
The outfan of unit is connected one to one with the two of gate circuit inputs, and the outfan of the gate circuit in each detection branch is even
Be connected on one with the input of door on, according to the fan-out of door according to judging whether the input data of Data Input Interface has
Effect.
As preferred, gate circuit is same OR gate or XOR gate.
As preferred, in order to detect that circuit output state is high level, low level or high-impedance state, threshold voltage generation
Unit includes high threshold value signal generating unit, low threshold voltage signal generating unit, high threshold value signal generating unit, low threshold voltage
Signal generating unit is connected with digital interface control unit, and the second input of the first threshold values comparing unit is connected high threshold value life
Become unit, the second input of the second threshold values comparing unit connects low threshold voltage signal generating unit, generates single from high threshold value
Unit, low threshold voltage signal generating unit upload the benchmark being input into the high and low level voltage threshold values coming as comparator.
As preferred, the outfan of the first threshold values comparing unit or the second threshold values comparing unit is selected one and is connect with data output
Mouth connects, and will input data be transferred in next stage circuit.
As preferred, when input data is effective, the next stage circuit being connected with this circuit will continue to gather this data
Signal；When input data is invalid, the next stage circuit being connected with this circuit will stop gathering this data signal.
As preferred, because the span of high and low level is extreme for two, so the biasing circuit producing takes centre
During value scheme preferably, so make two resistance resistance equal, and so that one of resistance is connected with power supply, another resistance and
Ground connects, so that the bias voltage that intermediate node produces is the intermediate value of circuit voltage.
As preferred, in order to adapt to different working environments and demand, two resistance can equivalence replacement be two electric currents
Source, one of current source is connected with power supply, and another current source is connected to ground, and the current direction of current source is for power supply direction extremely
Ground, its objective is to produce bias voltage.
As preferred, the first threshold values comparing unit, the first input end of the second threshold values comparing unit are in-phase end, first
Threshold values comparing unit, the second input of the second threshold values comparing unit are end of oppisite phase, i.e. the first threshold values comparing unit, the second threshold values
Comparing unit is all using positive logic.
As preferred, control signal is received by digital interface control unit, so that high threshold value signal generating unit is generated high
Level voltage threshold values, low threshold voltage signal generating unit generates low level voltage threshold values, and the node voltage between two resistance is less than
High level voltage threshold values, and it is more than low level voltage threshold values, that is, high and low level voltage threshold values forms three voltage ranges, respectively
Three kinds of states of corresponding circuits output.
The invention has the beneficial effects as follows:
A kind of multi input data mode parallel detection circuit with intelligent numerical control, by the input voltage to Data Input Interface
Signal is compared, and whether the output data according to gate circuit is effective come the input data judging Data Input Interface, thus protecting
The effectiveness of card data transmission procedure, and can find in time when input interface occurs hanging or loose contact, it is to avoid because
Gather the fault that insignificant signal is led to as data.
Described above is only the general introduction of technical solution of the present invention, in order to better understand the technological means of the present invention,
And can be practiced according to the content of description, below with presently preferred embodiments of the present invention and coordinate accompanying drawing describe in detail as after,
The specific embodiment of the present invention is shown in detail in by following examples and its accompanying drawing.
Brief description
Accompanying drawing described herein is used for providing a further understanding of the present invention, constitutes the part of the application, this
Bright schematic description and description is used for explaining the present invention, does not constitute inappropriate limitation of the present invention.In the accompanying drawings:
The physical circuit schematic diagram of the detection branch that Fig. 1 is related to for first embodiment of the invention；
The circuit diagram that multiple detection branches that Fig. 2 is related to for first embodiment of the invention are connected between door；
Fig. 3 is the chip interface schematic diagram of the multi input data mode parallel detection circuit carrying intelligent numerical control containing the present invention；
The schematic diagram of each position voltage in the detection branch that Fig. 4 is related to for first embodiment of the invention；
Fig. 5 applies the physical circuit schematic diagram of the detection branch that example is related to for the present invention second；
The physical circuit schematic diagram of the detection branch that Fig. 6 is related to for third embodiment of the invention；
The physical circuit schematic diagram of the detection branch that Fig. 7 is related to for fourth embodiment of the invention.
Wherein, 1 is high threshold value signal generating unit, and 2 is low threshold voltage signal generating unit, and 3 is digital interface control unit,
in、in1-in4For Data Input Interface, dout、dout1- dout4For data output interface, iksFor switch control interface, dinsFor number
According to input state output interface, vsFor threshold values control interface, vccFor the power supply of circuit, gnd is earth terminal, r1-r2For electricity
Resistance, is1、is2For current source, k1、k2For switch, a1For the first threshold values comparing unit, a2For the second threshold values comparing unit, dins1For
First data input State- output interface, dinsxFor xth data input State- output interface, dinsnDefeated for the n-th data input state
Outgoing interface, st is the total output interface of many data input state.
Wherein, in Fig. 4, the voltage of each position is described as follows: vinFor input voltage, vbiasFor bias voltage, va1+For first
Threshold values comparing unit a1The input voltage of in-phase end, va1-For the first threshold values comparing unit a1The input voltage of end of oppisite phase, va2+For
Two threshold values comparing unit a2The input voltage of in-phase end, va2-For the second threshold values comparing unit a2The input voltage of end of oppisite phase, vouta
For the first threshold values comparing unit a1Output voltage, voutbFor the second threshold values comparing unit a2Output voltage, vrefhFor high threshold values
Input voltage, vreflFor low valve valve input voltage, voutFor output voltage, vinsFor data input state-detection voltage.
Specific embodiment
Below with reference to the accompanying drawings and in conjunction with the embodiments, to describe the present invention in detail:
As shown in Figures 1 to 4 for the first embodiment of the present invention, wherein Fig. 1 is the concrete of detection branch in first embodiment
Circuit diagram；This detection branch includes biasing circuit, the first threshold values comparing unit a1, the second threshold values comparing unit a2；Wherein inclined
Circuits include the resistance r of two series connection1、r2, resistance r1One end and circuit power supply vccConnection, the other end and switch
k1Connect, resistance r2One end be connected with earth terminal gnd, the other end with switch k2Connect, in switch k1、k2Between node and number
It is connected according to input interface in.
As shown in figure 1, the first threshold values comparing unit a1, the second threshold values comparing unit a2All using positive logic so that and data
The node of input interface in and the first threshold values comparing unit a1, the second threshold values comparing unit a2First input end connect, and two
The first input end of comparing unit is in-phase end；Second input of two comparing units is end of oppisite phase, the wherein first threshold values
Comparing unit a1Second input connect high threshold value signal generating unit 1, the second threshold values comparing unit a2The second input even
Connect low threshold voltage signal generating unit 2, meanwhile, high threshold value signal generating unit 1, low threshold voltage signal generating unit 2 and digital interface
Control unit 3 connects, and digital interface control unit 3 is to being externally connected with threshold values control interface vs；First threshold values comparing unit a1,
Two threshold values comparing unit a2Outfan connect one to one with two inputs of same OR gate, with outfan and the data of OR gate
Input state output interface dinsConnect, the first threshold values comparing unit a1Outfan simultaneously with data output interface doutConnect.
As shown in Fig. 2 the outfan of the same OR gate in each detection branch be connected to one with the input of door on, and tie
Close Fig. 3, the detection object of the first embodiment of the present invention is 4 Data Input Interfaces, respectively Data Input Interface in1-in4,
I.e. n=4 in Fig. 2, after corresponding detection branch, exports corresponding data output interface dout1-dout4, input state output
Interface dins1- dins4；Input state output interface dins1- dins4Be both connected to one with the input of door on, should be defeated with door
Go out end and be connected with the total output interface st of data input state more than.
Wherein, by threshold values control interface vsThreshold values control signal is transferred in digital interface control unit 3, thus controlling
High threshold value signal generating unit 1 processed, low threshold voltage signal generating unit 2 generate high level voltage threshold values v respectivelyrefh, low level electricity
Pressure valve value vrefl, wherein high level voltage threshold values vrefhIt is disposed proximate to but the lower limit less than high level voltage, low level voltage
Threshold values vreflIt is disposed proximate to but the lower limit more than low level voltage, resistance r1、r2Between node voltage be less than high level electricity
Pressure valve value vrefh, and it is more than low level voltage threshold values vrefl, that is, form three voltage ranges, be respectively more than high level voltage valve
Value vrefhInterval, be in high level voltage threshold values vrefhWith low level voltage threshold values vreflBetween interval and be less than low electricity
Flat threshold voltage vreflInterval, and three kinds of states of respectively corresponding circuits output.
Meanwhile, in order to ensure more preferably Detection results, make resistance r1、r2Resistance equal, and resistance r1、r2Resistance is very
Greatly, thus in the ideal case, the bias voltage v of generationbiasPower supply v for circuitcc1/2nd, and this biased electrical
Electric current very little on road is so as to ignore to the impact caused by the high and low level of input data.
In order to better illustrate the work process of detection branch, in switch k1、k2In the case of closure, every in cooperation Fig. 4
Put voltage schematic diagram such as, the circuit analysis under the upper three kinds of forms of Data Input Interface in is as follows:
(1), when Data Input Interface in state in which is high level, va1+=va2+=vin=vih(input high level), va1-
=vrefh, va2-=vrefl, due to vih> vrefhAnd vih> vrefl, so that the first threshold values comparing unit a1Output voltage vouta、
Second threshold values comparing unit a2Output voltage voutbIt is high level, after same OR gate computing, the data input state that obtains
Detection voltage vinsFor high level, that is, the logical value exporting is 1.
(2), when Data Input Interface in state in which is low level, va1+=va2+=vin=vil(input low level),
va1-=vrefh, va2-=vrefl, due to vil<vrefhAnd vil<vrefl, so that the first threshold values comparing unit a1Output voltage
vouta, the second threshold values comparing unit a2Output voltage voutbIt is low level, after same OR gate computing, the data obtaining is defeated
Enter state-detection voltage vinsFor high level, that is, the logical value exporting is 1.
(3), when Data Input Interface in state in which is high-impedance state, it is equal on Data Input Interface in not outer
Connect, now, va1+=va2+=vbias, due to vrefl< vbias< vrefh, so that the first threshold values comparing unit a1Output voltage
voutaFor low level, the second threshold values comparing unit a2Output voltage voutbFor high level, i.e. the first threshold values comparing unit a1Output
Logical value be 0, the second threshold values comparing unit a2The logical value of output is 1, after same OR gate computing, the data input that obtains
State-detection voltage vinsFor low level, that is, the logical value exporting is 0.
In sum, as multiple data input state-detection voltage vinsOutput logical value when being 1, through and door
The output logical value obtaining after computing is 1, and multiple Data Input Interface in state in which are high level or low level, that is, many
The input data logic of individual Data Input Interface in is effectively, and logically, output voltage voutWith input voltage vinPhase
Deng the output interface d therefore the next stage circuit being connected with this testing circuit is fetched dataoutOutput data as this next stage circuit
Input data；As multiple data input state-detection voltage vinsOutput logical value in have one be 0 when, Jing Guoyu
The output logical value obtaining after the computing of door is 0, has residing for a Data Input Interface in multiple Data Input Interface in
State is high-impedance state, and that is, the input data logic of multiple Data Input Interface in is invalid, therefore next being connected with this testing circuit
Level circuit stops accepting and believing this output data.
As switch k1、k2In the case of disconnecting, then close the detection function of input data effectiveness.
Fig. 5 applies the physical circuit schematic diagram detecting branch in example, the difference compared with first embodiment for the present invention second
It is: the first threshold values comparing unit a1, the second threshold values comparing unit a2First input end be end of oppisite phase；First threshold values compares
Unit a1, the second threshold values comparing unit a2The second input be in-phase end, when Data Input Interface in state in which is high electricity
At ordinary times, the first threshold values comparing unit a1, the second threshold values comparing unit a2The logical value of output is 0, when Data Input Interface in institute
When the state at place is low level, the first threshold values comparing unit a1, the second threshold values comparing unit a2The logical value of output is 1, that is, defeated
Go out that logical value is contrary with input logic value, the next stage circuit being now connected with this testing circuit is fetched data output interface dout's
, as the input data of this next stage circuit, remaining is with reference to above-mentioned with regard to first for result after output data NAND gate computing
The description of embodiment.
Fig. 6 is the physical circuit schematic diagram detecting branch in third embodiment of the invention, and this detection branch includes biased electrical
Road, the first threshold values comparing unit a1, the second threshold values comparing unit a2；Wherein biasing circuit includes the current source is of two series connection1、
is2, current source is1Power supply v with circuitccConnect, current source is2It is connected with earth terminal gnd, in current source is1、is2It
Between node be connected with Data Input Interface in, that is, third embodiment of the invention is on the basis of first embodiment, will bias
Resistance r on circuit1、r2Replace with current source is1、is2, remaining is with reference to the above-mentioned description with regard to first embodiment.
Fig. 7 is the physical circuit schematic diagram detecting branch in fourth embodiment of the invention, the first threshold values comparing unit a1,
Two threshold values comparing unit a2Outfan connect one to one with two inputs of XOR gate, the outfan of XOR gate and data
Input state output interface dinsConnect, now, as data input state-detection voltage vinsOutput logical value be 0 when, data
The input data logical validity of input interface in；As data input state-detection voltage vinsOutput logical value be 1 when, data
The input data logic of input interface in is invalid, and that is, the fourth embodiment of the present invention is on the basis of first embodiment, will be with
OR gate replaces with XOR gate so that the correspondence of output logical value and effectiveness is contrary with first embodiment, and remaining is with reference to above-mentioned pass
Description in first embodiment.
Meanwhile, by the exchange of in-phase end and end of oppisite phase in second embodiment, by resistance r in 3rd embodiment1、r2Replace with
Current source is1、is2, in fourth embodiment, same OR gate is replaced with the form of XOR gate, is all on the basis of first embodiment
The replacement carrying out, this three kinds of substitute modes can freely form new embodiment, the such as the 5th embodiment: in first embodiment
On the basis of, by resistance r1、r2Replace with current source is1、is2, XOR gate will be replaced with OR gate, the 5th enforcement so being formed
Example be implement to the 3rd, the simple combination of fourth embodiment, such combine the equivalent reality that new embodiment is the present invention
Apply example；In addition, detection object is 4 Data Input Interfaces in first embodiment of the invention, the limit to the present invention can not be constituted
System, 4 is revised as 2 any of the above numerals, is the Equivalent embodiments of the present invention.
The above, only presently preferred embodiments of the present invention, not the present invention is made with any pro forma restriction；All
The those of ordinary skill of the industry all can shown in by specification accompanying drawing and the above and swimmingly implement the present invention；But, all
Those skilled in the art, in the range of without departing from technical solution of the present invention, are done using disclosed above technology contents
The a little change going out, the equivalent variations modified and develop, are the Equivalent embodiments of the present invention；Meanwhile, all according to the present invention
The change of any equivalent variations, modification and differentiation that substantial technological is made to above example etc., all still fall within the skill of the present invention
Within the protection domain of art scheme.
Claims (9)
1. a kind of multi input data mode parallel detection circuit with intelligent numerical control it is characterised in that: this testing circuit includes
Detect branch with multiple Data Input Interfaces correspondingly；It is more single that described detection branch includes biasing circuit, the first threshold values
Unit, the second threshold values comparing unit；Described biasing circuit includes resistance, the node between two described resistance and the number of two series connection
It is connected according to input interface, and both sides in node, two described resistance are connected to a switch, and described switch is connected with switch
Control interface；Connect the node of described Data Input Interface and described first threshold values comparing unit, the second threshold values comparing unit
First input end connects；Described first threshold values comparing unit, the second threshold values comparing unit the second input respectively with a valve
Threshold voltage signal generating unit connects, and the two of described first threshold values comparing unit, the outfan of the second threshold values comparing unit and gate circuit
Individual input connects one to one, and the outfan of the described gate circuit in each detection branch is connected to an input with door
On, according to the fan-out with door according to whether effective to judge the input data of Data Input Interface.
2. the multi input data mode parallel detection circuit with intelligent numerical control according to claim 1 it is characterised in that:
Described gate circuit is same OR gate or XOR gate, and the outfan of described gate circuit is connected with data input State- output interface.
3. the multi input data mode parallel detection circuit with intelligent numerical control according to claim 1 it is characterised in that:
Described threshold voltage signal generating unit includes high threshold value signal generating unit (1), low threshold voltage signal generating unit (2), described height
Threshold voltage signal generating unit (1), low threshold voltage signal generating unit (2) are connected with digital interface control unit (3), described first valve
Second input of value comparing unit connects high threshold value signal generating unit (1), and the second of described second threshold values comparing unit is defeated
Enter end and connect low threshold voltage signal generating unit (2).
4. the multi input data mode parallel detection circuit with intelligent numerical control according to claim 1 it is characterised in that:
The outfan of described first threshold values comparing unit or described second threshold values comparing unit is selected one and is connected with data output interface.
5. the multi input data mode parallel detection circuit with intelligent numerical control according to claim 1 it is characterised in that:
When input data is effective, the next stage circuit being connected with this circuit will continue to gather this data signal；When input data is invalid
When, the next stage circuit being connected with this circuit will stop gathering this data signal.
6. the multi input data mode parallel detection circuit with intelligent numerical control according to claim 1 it is characterised in that:
The resistance of two described resistance is equal, and so that one of described resistance is connected with power supply, and another described resistance is connected to ground.
7. the multi input data mode parallel detection circuit with intelligent numerical control according to claim 1 it is characterised in that:
Described first threshold values comparing unit, the first input end of the second threshold values comparing unit are in-phase end, and described first threshold values is more single
Unit, the second input of the second threshold values comparing unit are end of oppisite phase.
8. the multi input data mode parallel detection circuit with intelligent numerical control according to claim 3 it is characterised in that:
Control signal is received by described digital interface control unit, makes described high threshold value signal generating unit (1) generate high level voltage
Threshold values, described low threshold voltage signal generating unit (2) generates low level voltage threshold values, and the node voltage between two described resistance is little
In high level voltage threshold values, and it is more than low level voltage threshold values.
9. the multi input data mode parallel detection circuit with intelligent numerical control according to one of claim 1 to 8,
It is characterized in that: two described resistance can equivalence replacement be two current sources, and one of described current source is connected with power supply, separately
One described current source is connected to ground, and the current direction of described current source is power supply direction to ground.
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| CN201610814291.7A CN106341111A (en) | 2016-09-10 | 2016-09-10 | Multiple-input data state parallel detection circuit with intelligent numerical control |
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| CN201610814291.7A CN106341111A (en) | 2016-09-10 | 2016-09-10 | Multiple-input data state parallel detection circuit with intelligent numerical control |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN117498887A (en) * | 2024-01-02 | 2024-02-02 | 湖南慧明谦数字能源技术有限公司 | MBUS master node circuit driven by double-power operational amplifier |
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| CN117498887A (en) * | 2024-01-02 | 2024-02-02 | 湖南慧明谦数字能源技术有限公司 | MBUS master node circuit driven by double-power operational amplifier |
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Application publication date: 20170118 |
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| WD01 | Invention patent application deemed withdrawn after publication |