CN104932378B - Control method and circuit for special transformer acquisition terminal to prevent remote control false tripping - Google Patents
Control method and circuit for special transformer acquisition terminal to prevent remote control false tripping Download PDFInfo
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- CN104932378B CN104932378B CN201510322361.2A CN201510322361A CN104932378B CN 104932378 B CN104932378 B CN 104932378B CN 201510322361 A CN201510322361 A CN 201510322361A CN 104932378 B CN104932378 B CN 104932378B
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- nand gate
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
- G05B19/0428—Safety, monitoring
Abstract
The invention relates to a control method and circuit for a special transformer acquisition terminal to prevent remote control false tripping. According to the control method and circuit, when the terminal determines to emit tripping signals through a relay, the terminal can emit the tripping signals through the relay only by means of a complex logic sequence; high electric level signal output of a reset chip is adopted as a necessary condition of tripping signal emission; and the reset chip can output high electric level only when system voltage is normal and system program operates normally, and therefore, it can be ensured that no false tripping instructions are emitted.
Description
Technical field
The present invention relates to a kind of control method and circuit for preventing remote control mistrip for special transformer acquisition terminal.
Background technology
Special transformer acquisition terminal can realize the monitoring of the load to Electricity customers and electric flux, and electric company is jumped by remote control
Lock realizes the ordered electric of power customer and the adjustment of network load.According to existing remote control trip method, special transformer acquisition terminal
Directly pass through MCU（Micro-control unit）I O port line drive and realize that remote control is tripped, its major defect is：There is meaning in main control MCU
It is outer to run in winged, system electrification and MCU initialization procedures, remote control misoperation is easily caused, and then send error tripping order.
The content of the invention
The technical problem to be solved is to provide a kind of control for preventing remote control mistrip for special transformer acquisition terminal
Method processed and circuit, reset chip could export high level when being only used in normal system voltage, system program normal operation, to
Guarantee that inerrancy trip signal sends.
Technical scheme is as follows：
A kind of control method for preventing remote control mistrip for special transformer acquisition terminal, it is characterised in that：
1）, do using d type flip flop the input of prime remote signal, shaken with the I/O mouths for preventing CPU and cause relay misoperation
Make；
2）, using multiple control signal come the final output of control relay, only when reset signal is high level, YK_
EN1 connects high level and d type flip flop can be exported effectively when YK_EN2 connects low level；
3）, only multiple control signal change according to correct sequencing could control relay final output tripping operation letter
Number, YK_EN1 is first connect high level, YK_EN2 and connects low level by reset signal when stable, then the D of d type flip flop is connect into high level,
Sending a rising edge finally by the CLK of d type flip flop can just send trip signal.
Realize a kind of control circuit of the control method, it is characterised in that：It is touched including system CPU, reset chip and D
Send out device, also including the first NAND gate D2C, the second NAND gate D4B, the 3rd NAND gate D2A, the 4th NAND gate D2D and the 5th with it is non-
Door D2B, the 3rd NAND gate D2A and the 4th NAND gate D2D composition rest-set flip-flop circuit；Wherein, the RST pins difference of reset chip
One input pin of the reseting pin of welding system CPU and the first NAND gate D2C, the first NAND gate D2C output pin connects second
Two input pins of NAND gate D4B, the output pin of the second NAND gate D4B connects the input pin of rest-set flip-flop circuit, and RS is touched
The output pin for sending out device circuit connects two input pins of the 5th NAND gate D2B, and the output pin of the 5th NAND gate D2B meets D and touches
Send out the CLR pins of device；The I/O mouth First Line YK_EN1 of CPU connect another input pin and the drop-down electricity of Jing of the first NAND gate D2C
Resistance R4 meets GND；I/O mouths the second line YK_EN2 of CPU connects an input pin and Jing pull-up resistor R3 of the 4th NAND gate D2D and connects
VCC；Data in pin D1 to the D8 pins and CLK pins of d type flip flop connects respectively the remote control output control pin of CPU, and D is touched
Output pin Q1 to the Q8 for sending out device connects respectively photoelectric isolating circuit, photoelectric isolating circuit Jing drive circuits connection relay.
The positive effect of the present invention is：Must be by one when terminal determines to send trip signal by relay
Complicated logical order could send trip signal by relay.And high level signal is exported to send jump with reset chip
The necessary condition of lock signal.Reset chip could export high level when being only used in normal system voltage, system program normal operation,
So can determine that inerrancy trip signal sends.
Description of the drawings
Fig. 1 is the circuit theory diagrams of the present invention.
Specific embodiment
The present invention is further illustrated with reference to the accompanying drawings and examples.
As shown in figure 1, control circuit embodiment of the present invention includes system CPU 1, the and of reset chip 7 of model SAM9260
D type flip flop 2, also including the first NAND gate D2C, the second NAND gate D4B, the 3rd NAND gate D2A, the 4th NAND gate D2D and the 5th
NAND gate D2B, the 3rd NAND gate D2A and the 4th NAND gate D2D composition rest-set flip-flop circuit 3.
Wherein, the RST pins of reset chip 7 distinguish the reseting pin of welding system CPU1 and one of the first NAND gate D2C
Input pin, the first NAND gate D2C output pin connects two input pins of the second NAND gate D4B, the second NAND gate D4B it is defeated
Go out the input pin R that pin connects rest-set flip-flop circuit 3（That is an input pin of the 3rd NAND gate D2A）, rest-set flip-flop circuit 3
Output pin connect two input pins of the 5th NAND gate D2B, the output pin of the 5th NAND gate D2B connects d type flip flop 2
CLR pins, it is ensured that trip signal can be just sent only in the case of system mode is normal.
The I/O mouth First Line YK_EN1 of CPU1 connect another input pin and Jing pull down resistor R4 of the first NAND gate D2C
Meet GND；I/O mouths the second line YK_EN2 of CPU1 connects an input pin and Jing pull-up resistor R3 of the 4th NAND gate D2D and connects
VCC.During so as to ensure system electrification, when the I/O mouths of CPU are unstable, trip signal cannot send.
The present embodiment also includes photoelectric isolating circuit 4, drive circuit 6 and relay.The data in pin of d type flip flop 2
D1 to D8 pins and CLK pins connect respectively the remote control output control pin of CPU1, and output pin Q1 to the Q8 of d type flip flop 2 divides
Do not connect photoelectric isolating circuit 4（It is omissive representation in Fig. 1, only illustrates Q1 connections）, the Jing drive circuits 6 of photoelectric isolating circuit 4 connect
Relay 5.
The control method of the present invention includes following measures：
1）, do using d type flip flop the input of prime remote signal, the I/O mouths for preventing CPU are shaken and cause relay misoperation to make.
2）, using multiple control signal come the final output of control relay：Only when reset signal is completed, that is, reset letter
Number connect d type flip flop when high level, YK_EN2 connect low level and can effectively export for high level and YK_EN1.
3）, using multiple control signal according to correct sequencing change could control relay final output tripping operation
Signal.YK_EN1 is first connect high level, YK_EN2 and connects low level by reset signal when stable, then the D of d type flip flop is connect into high electricity
Flat, sending a rising edge finally by the CLK of d type flip flop can just send trip signal.The wrong any step of three above order
Can not send out trip signal.
In the present invention basic logic is realized with NAND gate, and wherein D2A and D2D realizes rest-set flip-flop function, D2C
The S inputs of rest-set flip-flop are extended with D4B, D2B realizes that the output end of rest-set flip-flop is anti-phase.Five NAND gate combinations of the above
Realize the main logic in the present invention.The output of above logic terminates to the clear terminal of d type flip flop, is understood only to work as by truth table
RST signal is high level with YK_EN1 signals, and the clear terminal side of d type flip flop is invalid when YK_EN2 is low level, trip signal
Can export.The D inputs of YK_EN1, YK_EN2 and d type flip flop and CLK are input into by system CPU control, first should be connect YK_EN1
High level, YK_EN2 connect low level, then the D of d type flip flop are connect into high level, send on one finally by the CLK of d type flip flop
Rising edge could finally send trip signal.YK_EN1 Jing pull down resistor R4 meet GND, YK_EN2 Jing pull-up resistor R3 and connect VCC guarantees
The clear terminal of d type flip flop when electric in system one（CLR）For low level, trip signal cannot send.When reset chip action
Reset signal is low level, and by truth table the clear terminal of now d type flip flop is understood（CLR）For low level, trip signal cannot be sent out
Go out.System electrification, if I/O port puts height in CPU initialization procedures, data keep when YK_EN1, YK_EN2 put high simultaneously, and D is touched
Send out the clear terminal of device（CLR）For low level, trip signal cannot send；If I/O port sets low in CPU initialization procedures, YK_
Zeros data EN1, YK_EN2 set low simultaneously when, the clear terminal of d type flip flop（CLR）For low level, trip signal cannot send.
In running system power supply by accidental destruction it is abnormal when, reset chip action output reset signal, by true
Value table understands the clear terminal of now d type flip flop（CLR）For low level, trip signal cannot send.
In a case where, circuit of the invention forbids tripping operation：
1st, when upper electric, YK_EN1 Jing pull down resistor R4 meet GND, YK_EN2 Jing pull-up resistor R3 and meet VCC, can by truth table
Know the clear terminal of d type flip flop（CLR）For low level, trip signal is forbidden sending.
2nd, when reset chip action, reset signal is low level, and by truth table the clear terminal of now d type flip flop is understood
（CLR）For low level, trip signal cannot send.When can avoid electrification reset and abnormal system power supply since so,
Send error tripping signal.
3rd, it is probably floating input in system initialization IO（High-impedance state）, it may be possible to put height, it is also possible to set low.If floating
Then such as [15], trip signal is forbidden sending for sky input；If putting height, data keep when YK_EN1, YK_EN2 put high, D triggerings
The clear terminal of device（CLR）Low level is still, trip signal is forbidden sending；If setting low, when YK_EN1, YK_EN2 set low
Zeros data, the clear terminal of d type flip flop（CLR）For low level, trip signal also cannot send.
During revocation trip signal, first YK_EN1 is set low, then YK_EN2 is put into height, the clear of d type flip flop is understood by truth table
Zero end（CLR）For low level, relay normally open contact disconnection, trip signal revocation.At the same time the output register of d type flip flop
It is cleared, when sending out trip signal again, it is necessary to re-operate fully according to original order, prevents trip signal cumulative error.
Claims (1)
1. a kind of control circuit for preventing remote control mistrip for special transformer acquisition terminal, it is characterised in that：It includes system CPU
（1）, reset chip（7）And d type flip flop（2）, also including the first NAND gate D2C, the second NAND gate D4B, the 3rd NAND gate D2A,
4th NAND gate D2D and the 5th NAND gate D2B, the 3rd NAND gate D2A and the 4th NAND gate D2D composition rest-set flip-flop circuit（3）；
Wherein, reset chip（7）RST pins difference welding system CPU（1）Reseting pin and one of the first NAND gate D2C input
Pin, the first NAND gate D2C output pin connects two input pins of the second NAND gate D4B, the efferent duct of the second NAND gate D4B
Pin connects rest-set flip-flop circuit（3）Input pin（R）, rest-set flip-flop circuit（3）Output pin connect the two of the 5th NAND gate D2B
Individual input pin, the output pin of the 5th NAND gate D2B connects d type flip flop（2）CLR pins；CPU（1）I/O mouth First Lines
YK_EN1 connects another input pin of the first NAND gate D2C and Jing pull down resistor R4 meet GND；CPU（1）The line of I/O mouths second
YK_EN2 connects an input pin of the 4th NAND gate D2D and Jing pull-up resistor R3 meet VCC；D type flip flop（2）Data input pipe
Pin D1 to D8 pins and CLK pins meet respectively CPU（1）Remote control output control pin, d type flip flop（2）Output pin Q1
Photoelectric isolating circuit is connect respectively to Q8（4）, photoelectric isolating circuit（4）Jing drive circuits（6）Connection relay（5）.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510322361.2A CN104932378B (en) | 2015-06-13 | 2015-06-13 | Control method and circuit for special transformer acquisition terminal to prevent remote control false tripping |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510322361.2A CN104932378B (en) | 2015-06-13 | 2015-06-13 | Control method and circuit for special transformer acquisition terminal to prevent remote control false tripping |
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| Publication Number | Publication Date |
|---|---|
| CN104932378A CN104932378A (en) | 2015-09-23 |
| CN104932378B true CN104932378B (en) | 2017-05-17 |
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| CN201510322361.2A Active CN104932378B (en) | 2015-06-13 | 2015-06-13 | Control method and circuit for special transformer acquisition terminal to prevent remote control false tripping |
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Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109258113B (en) * | 2018-11-16 | 2022-03-01 | 格力博(江苏)股份有限公司 | Grass cutter |
| CN110323712B (en) * | 2019-07-31 | 2021-10-08 | 西安天和防务技术股份有限公司 | Potential holding control method and overcurrent protection control method |
| CN111147046B (en) * | 2019-12-23 | 2023-02-28 | 陕西电器研究所 | Relay array control device and method |
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| CN102821274A (en) * | 2012-09-24 | 2012-12-12 | 长沙威胜信息技术有限公司 | Special transformer acquisition terminal |
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| GB0119300D0 (en) * | 2001-08-08 | 2001-10-03 | Koninkl Philips Electronics Nv | Delay fault test circuitry and related method |
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|---|---|---|---|---|
| CN2857270Y (en) * | 2005-07-14 | 2007-01-10 | 蒋曦韬 | Safety auto pretective socket when power failure |
| CN202363365U (en) * | 2010-06-24 | 2012-08-01 | 贠国保 | Circuit capable of preventing relay from running during power-on process |
| CN201811983U (en) * | 2010-07-27 | 2011-04-27 | 安徽中兴继远信息技术有限公司 | Collection terminal device of special transformer |
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| CN103647526A (en) * | 2013-11-15 | 2014-03-19 | 许继集团有限公司 | PWM locking control circuit |
| CN204189917U (en) * | 2014-12-03 | 2015-03-04 | 国家电网公司 | UPS storage battery long-distance intelligent management of charging and discharging system |
| CN104505809A (en) * | 2014-12-24 | 2015-04-08 | 国电南京自动化股份有限公司 | Multi-energy level spark detection system with locking function |
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| CN104932378A (en) | 2015-09-23 |
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Address after: 264003 Laishan City, Yantai province Venture Center, Shandong Applicant after: Yantai Dongfang Wisdom Electric Co., Ltd. Address before: 264003 Laishan City, Yantai province Venture Center, Shandong Applicant before: Yantai Dongfang Wisdom Electronic Co., Ltd. |
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