CN107991523A - A kind of three-state input detection circuit and its detection method - Google Patents
A kind of three-state input detection circuit and its detection method Download PDFInfo
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- CN107991523A CN107991523A CN201711233375.2A CN201711233375A CN107991523A CN 107991523 A CN107991523 A CN 107991523A CN 201711233375 A CN201711233375 A CN 201711233375A CN 107991523 A CN107991523 A CN 107991523A
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- pmos tube
- phase inverter
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
- G01R19/0084—Arrangements for measuring currents or voltages or for indicating presence or sign thereof measuring voltage only
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Abstract
The invention discloses a kind of three-state input detection circuit, wherein, including sequentially connected bleeder circuit and detection circuit, the bleeder circuit connects an input signal Vin, for input signal to be carried out partial pressure；The detection circuit, for checking the input state of input signal.A kind of three-state input detection circuit of the present invention has the characteristics that detection accuracy is high.The invention also discloses the detection method of the detection circuit.
Description
Technical field
The present invention relates to a kind of circuit checker, more specifically, more particularly to a kind of three-state input detection circuit；This
Invention further relates to a kind of detection method of three-state input detection circuit.
Background technology
It is basic that the input state of circuit includes three kinds of high level, low level and high-impedance state (suspended state) under normal circumstances
Logic state.It can determine that input voltage is in high level, low level or height using detection circuit usually when designing circuit
Resistance state.
As shown in Figure 1, the input signal of traditional tri-state detection circuit is in parallel with resistance R1 and resistance R2 to form input point
Volt circuit, input signal are also connected with the grid of transistor M1 and the grid of transistor M2, the other end of resistance R1 respectively with crystal
The drain electrode of pipe M1 is connected with the drain electrode of transistor M2, the other end of resistance R2 respectively with the source electrode of transistor M1 and transistor M2
Source electrode connects, and forms the different comparator of turn threshold, and when input is high level or low level, Vin is transfused to signal drawing
Height drags down, and compares the corresponding result of output.When input is high-impedance state, bleeder circuit provides Vin voltages, exports corresponding knot
Fruit.So as to achieve the purpose that to detect input state.Traditional tri-state detection circuit occurs when strong noise, supply voltage are unstable
Mistake is detected, antijamming capability is poor, while its bleeder circuit current drain is larger.Make detection accurate it would therefore be highly desirable to invent one kind
The three-state input detection circuit of true property higher.
The content of the invention
The present invention previous purpose be to provide a kind of three-state input detection circuit, which passes through input state control
The work of two NMOS and two PMOS transmission gates is made, tri-state input detection is realized, has the characteristics that detection accuracy is high.This hair
Bright latter purpose is to provide a kind of detection method of three-state input detection circuit.
The previous technical solution of the present invention is as follows：
A kind of three-state input detection circuit, wherein, including sequentially connected bleeder circuit and detection circuit,
The bleeder circuit connects an input signal Vin, for input signal to be carried out partial pressure；
The detection circuit, for checking the input state of input signal.
Preferably, described partial pressure electricity 1 include resistance R1, resistance R2, resistance R3, resistance R4, resistance R5, PMOS tube PM1,
PMOS tube PM2, PMOS tube PM3, NMOS tube NM1, the input signal Vin by after resistance R5 respectively with PMOS tube PM3's
The source electrode connection of source electrode, NMOS tube NM1, the drain electrode of the NMOS tube NM1 are sequentially connected after resistance R3, resistance R1 and PMOS tube
The source electrode connection of PM1, the grid of the PMOS tube PM1 connect respectively the drain electrode of PMOS tube PM1, PMOS tube PM2 source electrode and
The grid of NMOS tube NM1, the drain electrode with PMOS tube PM2, the grid of PMOS tube PM3 are connected the grid of the PMOS tube PM2 respectively,
The drain electrode of the PMOS tube PM2 is connected after being sequentially connected resistance R2, resistance R4 with the drain electrode of PMOS tube PM3, the resistance R2 and
Resistance R4 indirectly.
Preferably, the detection circuit includes phase inverter U1, phase inverter U2, phase inverter U3, phase inverter U4, phase inverter
U5, phase inverter U6, phase inverter U7, PMOS tube PM4, PMOS tube PM5, NMOS tube NM2, NMOS tube NM3, the NMOS tube NM1's
Drain electrode is connected with by the grid after phase inverter U1 respectively with phase inverter U2, the source electrode of PMOS tube PM4, PMOS tube PM5, described anti-
The output of phase device U2 connects source electrode, the grid of NMOS tube NM3 of NMOS tube NM2 respectively, and the drain electrode of the PMOS tube PM3 passes through anti-
Phase device U3 respectively the grid with phase inverter U3, the source electrode of NMOS tube NM3, the grid of PMOS tube PM4, PMOS tube PM5 source electrode with
And phase inverter U6 connections, the drain electrode of the NMOS tube NM2 and the drain electrode of NMOS tube NM3, the drain electrode of PMOS tube PM4 and PMOS tube
Connect output terminal OUT1, the output terminal of the phase inverter U6 after the drain electrode parallel connection of PM5 after phase inverter U4, phase inverter U5 successively
Output terminal OUT2 is connected after connecting phase inverter U7.
Latter technique scheme of the present invention is as follows：
A kind of detection method of three-state input detection circuit, includes the following steps：
(1) input signal enters detection circuit, and detection information is exported respectively from output terminal OUT1 and output terminal OUT2, according to
The inspection information of output judges the input state of input signal；
(2) when input signal Vin is high level, PMOS tube PM3 conductings, resistance R4 pressure drops are high, output terminal OUT2 outputs
" 0 ", NMOS tube NM1 cut-offs, resistance R3 is without pressure drop, NMOS tube NM3 conductings, output terminal OUT1 outputs " 0 "；
(3) when input signal Vin is low level, PMOS tube PM3 cut-offs, resistance R4 is without pressure drop, output terminal OUT2 outputs
" 1 ", NMOS tube NM1 conductings, resistance R3 pressure drops are big, NMOS tube NM2 conductings, output terminal OUT1 outputs " 0 "；
(4) when input signal Vin is high-impedance state, PMOS tube PM3 conductings, resistance R4 pressure drops are small, output terminal OUT2 outputs
" 1 ", NMOS tube NM1 conductings, resistance R3 pressure drops are small, NMOS tube NM4 conductings, output terminal OUT1 outputs " 1 ".
Compared with prior art, the device have the advantages that being：
1. a kind of three-state input detection circuit of the present invention, wherein, including sequentially connected bleeder circuit and detection circuit,
The bleeder circuit connects an input signal Vin, for input signal to be carried out partial pressure；The detection circuit, for examining
Look into the input state of input signal.When detecting, input signal Vin current potentials are determined when low and high level is inputted by input signal,
Determined in high-impedance state by bleeder circuit, meanwhile, input state controls the conducting of NM1 and PM3 pipes, determines pull-up resistor R3 with
The pressure drop of pull-up resistor R4.NMOS transmits low level, PMOS transmission high level；The output voltage of pull down resistor R4 prolongs by phase inverter
When after obtain detection signal OUT2；The output voltage of pull-up resistor R3 and pull down resistor R4, by phase inverter only one
Transmission gate works, and transmits corresponding level, obtains detection signal OUT1；Since in high-impedance state, NM1, PM3 are turned on, but pull down electricity
It is much smaller when resistance and pull-up resistor voltage drop value ratio input low and high level so that output testing result will not repeat, accurate with detection
The characteristics of really property is high.
2. a kind of detection method of three-state input detection circuit of the present invention, input state is detected using this detection method
When, the different way of outputs, which is shown, to be realized to three kinds of input states, testing result is more accurate clear.
Brief description of the drawings
Fig. 1 is the circuit diagram of traditional tri-state detection circuit；
Fig. 2 is the circuit diagram of the present invention.
Embodiment
With reference to embodiment, technical scheme is described in further detail, but is not formed pair
Any restrictions of the present invention.
With reference to shown in Fig. 2, a kind of three-state input detection circuit of the invention, wherein, including sequentially connected bleeder circuit 1
With detection circuit 2,
The bleeder circuit 1 connects an input signal Vin, for input signal to be carried out partial pressure；
The detection circuit 2, for checking the input state of input signal.
The bleeder circuit 1 includes resistance R1, resistance R2, resistance R3, resistance R4, resistance R5, PMOS tube PM1, PMOS
Pipe PM2, PMOS tube PM3, NMOS tube NM1, the input signal Vin by after resistance R5 respectively the source electrode with PMOS tube PM3,
The source electrode connection of NMOS tube NM1, the drain electrode of the NMOS tube NM1 are sequentially connected the source after resistance R3, resistance R1 with PMOS tube PM1
Pole connects, and the grid of the PMOS tube PM1 connects the drain electrode of PMOS tube PM1, the source electrode of PMOS tube PM2 and NMOS tube respectively
The grid of NM1, the drain electrode with PMOS tube PM2, the grid of PMOS tube PM3 are connected the grid of the PMOS tube PM2 respectively, described
The drain electrode of PMOS tube PM2 is connected after being sequentially connected resistance R2, resistance R4 with the drain electrode of PMOS tube PM3, the resistance R2 and resistance
R4 indirectly.The current potential of input signal Vin is when input signal inputs for high level or low level is inputted by input signal
Determine, when input signal is high-impedance state, the current potential of input signal Vin is determined by bleeder circuit 1；Meanwhile input signal Vin
Input state controls the conducting of NM1 and PM3 pipes, so as to determine the pressure drop of resistance R3 and resistance R4.
The detection circuit 2 includes phase inverter U1, phase inverter U2, phase inverter U3, phase inverter U4, phase inverter U5, anti-phase
Device U6, phase inverter U7, PMOS tube PM4, PMOS tube PM5, NMOS tube NM2, NMOS tube NM3, the drain electrode of the NMOS tube NM1 is with leading to
The grid after phase inverter U1 respectively with phase inverter U2, the source electrode of PMOS tube PM4, PMOS tube PM5 is crossed to be connected, the phase inverter U2's
Output connects source electrode, the grid of NMOS tube NM3 of NMOS tube NM2 respectively, and the drain electrode of the PMOS tube PM3 is divided by phase inverter U3
Grid, the source electrode of NMOS tube NM3, the grid of PMOS tube PM4, the source electrode and phase inverter of PMOS tube PM5 not with phase inverter U3
U6 connections, the drain electrode of the NMOS tube NM2 and the drain electrode of NMOS tube NM3, the drain electrode of PMOS tube PM4 and the leakage of PMOS tube PM5
The output terminal connection for extremely connecting output terminal OUT1, the phase inverter U6 after parallel connection after phase inverter U4, phase inverter U5 successively is anti-
Output terminal OUT2 is connected after phase device U7.4 metal-oxide-semiconductors are as transmission gate, NMOS tube NM2 and NMOS tube NM3 transmission low levels, PMOS
Pipe PM4 and PMOS tube PM5 transmission high level；The output voltage of resistance R4 obtains connection output terminal after phase inverter is delayed
OUT2；The output voltage of resistance R3 and resistance R4, are worked by a phase inverter only transmission gate, transmit corresponding electricity
It is flat, obtain connection output terminal OUT1；Since in high-impedance state, NMOS tube NM1 and PMOS tube PM3 are turned on, but resistance R3 and resistance
It is much smaller when R4 voltage drop values are inputted than input signal for high level or low level inputs so that output testing result will not weigh
It is multiple, have the characteristics that detection accuracy is high.
A kind of detection method of three-state input detection circuit, includes the following steps：
(1) input signal enters detection circuit, and detection information is exported respectively from output terminal OUT1 and output terminal OUT2, according to
The inspection information of output judges the input state of input signal；
(2) when input signal Vin is high level, PMOS tube PM3 conductings, resistance R4 pressure drops are high, output terminal OUT2 outputs
" 0 ", NMOS tube NM1 cut-offs, resistance R3 is without pressure drop, NMOS tube NM3 conductings, output terminal OUT1 outputs " 0 "；
(3) when input signal Vin is low level, PMOS tube PM3 cut-offs, resistance R4 is without pressure drop, output terminal OUT2 outputs
" 1 ", NMOS tube NM1 conductings, resistance R3 pressure drops are big, NMOS tube NM2 conductings, output terminal OUT1 outputs " 0 "；
(4) when input signal Vin is high-impedance state, PMOS tube PM3 conductings, resistance R4 pressure drops are small, output terminal OUT2 outputs
" 1 ", NMOS tube NM1 conductings, resistance R3 pressure drops are small, NMOS tube NM4 conductings, output terminal OUT1 outputs " 1 ".
The results are shown in Table 1 for a kind of three-state input detection circuit of the present invention：
1 three-state input detection circuit of table exports result
| Input state | Output terminal OUT1 | Output terminal OUT1 |
| High level | 0 | 0 |
| Low level | 0 | 1 |
| High-impedance state | 1 | 1 |
As can be seen from Table 1, a kind of three-state input detection circuit of the invention, set bleeder circuit can be realized not
Transmission gate working status when being inputted with low and high level, the characteristic of high-impedance state high resistant, when control is different and low and high level inputs
Transmission gate works, and realizes the output of three kinds of results, testing result accuracy higher.
The foregoing is merely presently preferred embodiments of the present invention, it is all made in the range of the spirit and principles in the present invention it is any
Modifications, equivalent substitutions and improvements etc., should all be included in the protection scope of the present invention.
Claims (4)
- A kind of 1. three-state input detection circuit, it is characterised in that including sequentially connected bleeder circuit (1) and detection circuit (2),The bleeder circuit (1) connects an input signal (Vin), for input signal to be carried out partial pressure；The detection circuit (2), for checking the input state of input signal.
- A kind of 2. three-state input detection circuit according to claim 1, it is characterised in that bleeder circuit (1) bag Include resistance (R1), resistance (R2), resistance (R3), resistance (R4), resistance (R5), PMOS tube (PM1), PMOS tube (PM2), PMOS tube (PM3), NMOS tube (NM1), the input signal (Vin) by after resistance (R5) respectively the source electrode with PMOS tube (PM3), The source electrode connection of NMOS tube (NM1), the drain electrode of the NMOS tube (NM1) are sequentially connected resistance (R3), resistance (R1) afterwards and PMOS The source electrode connection of (PM1) is managed, the grid of the PMOS tube (PM1) connects the drain electrode of PMOS tube (PM1), PMOS tube (PM2) respectively Source electrode and NMOS tube (NM1) grid, the grid of the PMOS tube (PM2) drain electrode with PMOS tube (PM2), PMOS respectively Manage the grid connection of (PM3), the drain electrode of the PMOS tube (PM2) is sequentially connected resistance (R2), resistance (R4) afterwards and PMOS tube (PM3) drain electrode connection, the resistance (R2) and resistance (R4) indirectly.
- A kind of 3. three-state input detection circuit according to claim 1 or 2, it is characterised in that the detection circuit (2) Including phase inverter (U1), phase inverter (U2), phase inverter (U3), phase inverter (U4), phase inverter (U5), phase inverter (U6), phase inverter (U7), PMOS tube (PM4), PMOS tube (PM5), NMOS tube (NM2), NMOS tube (NM3), the drain electrode of the NMOS tube (NM1) with It is connected by the grid after phase inverter (U1) respectively with phase inverter (U2), the source electrode of PMOS tube (PM4), PMOS tube (PM5), it is described The output of phase inverter (U2) connects the source electrode of NMOS tube (NM2), the grid of NMOS tube (NM3) respectively, the PMOS tube (PM3) Drain electrode by phase inverter (U3) respectively the grid with phase inverter (U3), the source electrode of NMOS tube (NM3), PMOS tube (PM4) grid, Source electrode and phase inverter (U6) connection of PMOS tube (PM5), the drain electrode of the NMOS tube (NM2) and the drain electrode of NMOS tube (NM3), Connect successively after phase inverter (U4), phase inverter (U5) after the drain electrode of PMOS tube (PM4) and the drain electrode parallel connection of PMOS tube (PM5) Output terminal (OUT1) is connect, the output terminal connection phase inverter (U7) of the phase inverter (U6) connects output terminal (OUT2) afterwards.
- 4. the detection method of a kind of three-state input detection circuit described in claim 1, it is characterised in that include the following steps：(1) input signal enters detection circuit, and detection information is exported respectively from output terminal (OUT1) and output terminal (OUT2), according to The inspection information of output judges the input state of input signal；(2) when input signal (Vin) is high level, PMOS tube (PM3) conducting, resistance (R4) pressure drop is high, and output terminal (OUT2) is defeated Go out " 0 ", NMOS tube (NM1) cut-off, resistance (R3) is without pressure drop, NMOS tube (NM3) conducting, output terminal (OUT1) output " 0 "；(3) when input signal (Vin) is low level, PMOS tube (PM3) is ended, and resistance (R4) is defeated without pressure drop, output terminal (OUT2) Go out " 1 ", NMOS tube (NM1) conducting, resistance (R3) pressure drop is big, NMOS tube (NM2) conducting, output terminal (OUT1) output " 0 "；(4) when input signal (Vin) is high-impedance state, PMOS tube (PM3) conducting, resistance (R4) pressure drop is small, and output terminal (OUT2) is defeated Go out " 1 ", NMOS tube (NM1) conducting, resistance (R3) pressure drop is small, NMOS tube (NM4) conducting, output terminal (OUT1) output " 1 ".
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| CN201711233375.2A CN107991523B (en) | 2017-11-30 | 2017-11-30 | A kind of three-state input detection circuit and its detection method |
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| CN201711233375.2A CN107991523B (en) | 2017-11-30 | 2017-11-30 | A kind of three-state input detection circuit and its detection method |
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| CN107991523A true CN107991523A (en) | 2018-05-04 |
| CN107991523B CN107991523B (en) | 2018-11-02 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112526581A (en) * | 2020-11-26 | 2021-03-19 | 重庆邮电大学 | Time discriminator suitable for radiation detection front-end reading circuit |
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| CN202404208U (en) * | 2011-10-27 | 2012-08-29 | 苏州路之遥科技股份有限公司 | Tri-state detection circuit based on I/O port |
| CN103018588A (en) * | 2012-11-23 | 2013-04-03 | 无锡中星微电子有限公司 | Low-power-consumption anti-interference three-state input detection circuit |
| CN104142442A (en) * | 2013-05-10 | 2014-11-12 | 盛群半导体股份有限公司 | Tri-state input detection circuit with extremely low power consumption and input state detection method thereof |
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2017
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| JPH01502534A (en) * | 1987-03-11 | 1989-08-31 | グラマン・アエロスペース・コーポレーション | 3-state circuit test equipment |
| CN102201807A (en) * | 2011-04-11 | 2011-09-28 | 长沙景嘉微电子有限公司 | Simple tristate input circuit |
| CN202404208U (en) * | 2011-10-27 | 2012-08-29 | 苏州路之遥科技股份有限公司 | Tri-state detection circuit based on I/O port |
| CN103018588A (en) * | 2012-11-23 | 2013-04-03 | 无锡中星微电子有限公司 | Low-power-consumption anti-interference three-state input detection circuit |
| CN104142442A (en) * | 2013-05-10 | 2014-11-12 | 盛群半导体股份有限公司 | Tri-state input detection circuit with extremely low power consumption and input state detection method thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112526581A (en) * | 2020-11-26 | 2021-03-19 | 重庆邮电大学 | Time discriminator suitable for radiation detection front-end reading circuit |
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| CN107991523B (en) | 2018-11-02 |
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