CN103954901A - Device for detecting faults of CMOS integrated circuit of handheld device - Google Patents
Device for detecting faults of CMOS integrated circuit of handheld device Download PDFInfo
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- CN103954901A CN103954901A CN201410145168.1A CN201410145168A CN103954901A CN 103954901 A CN103954901 A CN 103954901A CN 201410145168 A CN201410145168 A CN 201410145168A CN 103954901 A CN103954901 A CN 103954901A
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Abstract
The invention discloses a device for detecting faults of a CMOS integrated circuit of a handheld device. The device comprises a detected circuit, a reference circuit, an enabling circuit, a mirroring circuit, a differential amplification circuit, a totem-pole circuit and a phase inverting circuit. A to-be-detected CMOS static leak current is generated by the detected circuit, a reference current signal is generated by the reference circuit, and the reference circuit is connected with the mirroring circuit. The to-be-detected static leak current and a comparison current are received by the differential amplification circuit to generate an amplification signal, the amplification signal is connected with an I/O interface of a microprocessor through the totem-pole circuit and the phase inverting circuit, and the microprocessor can determine working characteristics of the to-be-detected CMOS circuit by detecting the output amplification signal. The device for detecting the faults is simple in structure and low in cost, the static current in the CMOS circuit can be effectively detected, the screening efficiency of the CMOS integrated circuit can be greatly improved, and the reliability of the integrated circuit can be improved.
Description
Technical field
The invention belongs to power electronics and detect applied technical field, relate in particular to a kind of COMS Fault of Integrated Circuits checkout equipment of handheld device, this fault detect electricity can effectively detect the quiescent current in cmos circuit, increase substantially the screening effeciency of CMOS integrated circuit, improve the reliability of integrated circuit.
Background technology
The advantages such as that CMOS integrated circuit has is low in energy consumption, good in anti-interference performance, supply voltage wide ranges, thereby in the every field such as computing machine, communication, Aero-Space, remote measuring and controlling and industrial automatic control, obtain application more and more widely.Because cmos circuit structurally has mutual symmetry, in the time that breaking down, circuit also has its singularity, be sometimes difficult to detect by classical logical method.Grasp correct and effective detection method, especially really, do not have in the situation of COMS circuit special inspecting equipment, for the construction cycle that shortens the new product that adopts cmos device, improve the efficiency of research work, guarantee that the normal operation tool of various device is of great significance.While utilizing cmos circuit normal, static power consumption is little.And the circuit feature that power consumption increases rapidly while breaking down, the fault that detects cmos circuit with power consumption mensuration can reach the effect of getting twice the result with half the effort.
The method of test CMOS circuit has a variety of, and the conventional method of test logic fault is to adopt logical response test, i.e. usually said functional test.Functional test diagnosable go out logic error, but can not check out that transistor often opens fault, the normally closed fault of transistor, the short circuit of gate oxide transistor layer, the fault that the physical imperfections such as interconnection bridge short circuit cause, these defects can't affect the logic function of circuit immediately, conventionally will after device work a period of time, just can affect its logic function.Functional test is the fault detect of logic-based level, determines logic level by the voltage of measuring original output, and therefore functional test is actually voltage tester.Voltage tester is for detecting stuck-at fault, particularly the stuck-at fault in bipolar technology is effective, but for detecting other types fault in CMOS technique some deficiency that seems, and these fault types are common in CMOS circuit test.For fairly large circuit, the generation of voltage tester test set is quite complicated and longer, needs a large amount of experimental data samples.
In cmos circuit, due to some story that metal-oxide-semiconductor short circuit, open circuit etc. causes, be difficult to detect by logic testing method, and adopt electric leakage mensuration effectively to test these faults.
Summary of the invention
The defect and the deficiency that exist for above-mentioned prior art, the object of the invention is to, a kind of COMS Fault of Integrated Circuits checkout equipment of handheld device is provided, failure detector circuit of the present invention can detect by tested static electric current I _ DDQ the fault that the physical imperfection in circuit causes, also can detect those and not yet cause logic error, whether the known circuit-under-test of numerical value of the voltage of exporting by observation test circuit has physical imperfection simultaneously.
In order to realize above-mentioned task, the present invention adopts following technical solution:
A COMS Fault of Integrated Circuits checkout equipment for handheld device, comprises circuit-under-test, reference circuit, enable circuits, mirror image circuit, differential amplifier circuit, totem-pote circuit, negative circuit; Described circuit-under-test is connected with power supply+V, differential amplifier circuit, mirror image circuit and enable circuits, described reference circuit is connected with mirror image circuit with power supply+V, described enable circuits is connected between circuit-under-test and ground, described mirror image circuit is connected with reference circuit, circuit-under-test and differential amplifier circuit, described differential amplifier circuit is connected with circuit-under-test, mirror image circuit and totem-pote circuit, and described negative circuit is connected between totem-pote circuit and microprocessor I/O port; Described circuit-under-test is made up of the field effect transistor of P raceway groove or the field effect transistor of N raceway groove, and this circuit is for generation of tested static leakage current signal I_DDQ, and is transported to mirror image circuit and differential amplifier circuit using this signal as input signal; Described reference circuit is made up of standard field effect transistor, and this circuit is for generation of reference current signal I_REF, and this signal is transported to mirror image circuit as input signal; Described mirror image circuit is made up of base image current source or the mirror current source that is made up of amplifier, by can produce the required comparison current signal of differential amplifier circuit to the coupling of internal resistance; Described differential amplifier circuit is made up of 2 precision resisters and 2 NPN type triodes; Described totem-pote circuit is made up of NPN type triode and positive-negative-positive triode, and described negative circuit is made up of N channel enhancement metal-oxide-semiconductor and P-channel enhancement type metal-oxide-semiconductor.
The invention has the beneficial effects as follows:
Electric current I _ DDQ refers to the power supply total current in the time that all pipes in CMOS integrated circuit all remain static.For middle small scale integrated circuit, when normal condition, trouble-free power supply total current is the microampere order of magnitude; In the time there is the fault such as bridge joint or grid source short circuit in circuit, can in Static CMOS Circuits, form a low impedance path from positive supply to ground, can cause power supply total current to exceed a milliampere order of magnitude.So quiescent power supply current in semiconductor integrated circuit I_DDQ test philosophy is: the leakage current of non-fault CMOS circuit under static condition is very little, and under fault condition, leakage current becomes very large, and can set a threshold value has trouble-free criterion as circuit.
Testing apparatus works in two kinds of patterns: normal mode of operation and test pattern.Circuit Enable Pin E is as the input of pipe T0, is used for controlling being connected and disconnection of test circuit and circuit-under-test, i.e. the mode of operation of test circuit.
In the time that enable circuits is worked, testing apparatus works in test pattern, the input detection signal I_DDQ of circuit-under-test is transported to mirror image circuit and differential amplifier circuit, reference circuit produces reference current accurately by the field effect transistor circuit of standard, this reference current is transported in mirror image circuit as the standard value that judges circuit-under-test, image current source circuit can be made up of base image current source, the mirror current source that also can be made up of amplifier forms, can produce accurately relatively current signal by quiescent power supply current in semiconductor integrated circuit I_DDQ and reference current signal I_REF by coupling internal resistance, this comparison current signal can comprehensive characterization goes out the health status of circuit-under-test, by differential amplifier circuit, the difference that compares current signal and quiescent power supply current in semiconductor integrated circuit I_DDQ is amplified to output, output amplifying signal is through totem-pote circuit, by the driving force of matching voltage and raising I/O, signal after processing outputs to the I/O mouth of microprocessor through negative circuit, the voltage signal of output is changed direction by the effect of negative circuit, consistent with actual steering logic, while exporting high level, illustrate that tested cmos circuit belongs to normal, tested cmos circuit existing problems are described when output low level.
In the time that enable circuits is not worked, testing apparatus works in non-operating mode, the input detection signal I_DDQ of circuit-under-test is through the direct ground connection of enable circuits, measured signal is without testing circuit, because test circuit is added between circuit-under-test and ground, so can cause the performance of circuit-under-test to decline to some extent.In order to eliminate this impact, add in addition and enable control end.In normal mode of operation situation, Enable Pin ground connection, test circuit separates with circuit-under-test, and test circuit has no effect to circuit-under-test.
This failure detector circuit is simple in structure, with low cost, can effectively detect the quiescent current in cmos circuit, increases substantially the screening effeciency of CMOS integrated circuit, improves the reliability of integrated circuit.
Brief description of the drawings
Below in conjunction with the drawings and specific embodiments, the present invention is further explained.
Fig. 1 is CMOS Fault of Integrated Circuits checkout equipment system chart;
Fig. 2 is a kind of example circuit diagram of CMOS Fault of Integrated Circuits checkout equipment.
In Fig. 1, I_DDQ is the static leakage current of tested CMOS circuit, and I_REF is circuit reference current.
In Fig. 2, Q1, Q2 are P-channel enhancement type metal-oxide-semiconductors, and Q3 is N channel enhancement metal-oxide-semiconductor, and T1, T3 and T4 are NPN type triodes, and T2 and T5 are positive-negative-positive triodes, and C1 ~ C3 is electric capacity, and R1 ~ R8 is resistance.
Embodiment
If Fig. 1 is CMOS Fault of Integrated Circuits checkout equipment system chart, the COMS Fault of Integrated Circuits checkout equipment of this handheld device, comprises circuit-under-test, reference circuit, enable circuits, mirror image circuit, differential amplifier circuit, totem-pote circuit, negative circuit; Described circuit-under-test is connected with power supply+V, differential amplifier circuit, mirror image circuit and enable circuits, described reference circuit is connected with mirror image circuit with power supply+V, described enable circuits is connected between circuit-under-test and ground, described mirror image circuit is connected with reference circuit, circuit-under-test and differential amplifier circuit, described differential amplifier circuit is connected with circuit-under-test, mirror image circuit and totem-pote circuit, and described negative circuit is connected between totem-pote circuit and microprocessor I/O port; Described circuit-under-test is made up of the field effect transistor of P raceway groove or the field effect transistor of N raceway groove, and this circuit is for generation of tested static leakage current signal I_DDQ, and is transported to mirror image circuit and differential amplifier circuit using this signal as input signal; Described reference circuit is made up of standard field effect transistor, and this circuit is for generation of reference current signal I_REF, and this signal is transported to mirror image circuit as input signal; Described mirror image circuit is made up of base image current source or the mirror current source that is made up of amplifier, by can produce the required comparison current signal of differential amplifier circuit to the coupling of internal resistance; Described differential amplifier circuit is made up of 2 precision resisters and 2 NPN type triodes; Described totem-pote circuit is made up of NPN type triode and positive-negative-positive triode, and described negative circuit is made up of N channel enhancement metal-oxide-semiconductor and P-channel enhancement type metal-oxide-semiconductor.
Can produce accurately relatively current signal by quiescent power supply current in semiconductor integrated circuit I_DDQ and reference current signal I_REF by coupling internal resistance, this comparison current signal can comprehensive characterization goes out the health status of circuit-under-test, by differential amplifier circuit, the difference that compares current signal and quiescent power supply current in semiconductor integrated circuit I_DDQ is amplified to output, output amplifying signal is through totem-pote circuit, by the driving force of matching voltage and raising I/O, signal after processing outputs to the I/O mouth of microprocessor through negative circuit, the voltage signal of output is changed direction by the effect of negative circuit, consistent with actual steering logic, while exporting high level, illustrate that tested cmos circuit belongs to normal, there is not defect in integrated circuit, tested cmos circuit existing problems are described when output low level.
Fig. 2 is a kind of example circuit diagram of CMOS Fault of Integrated Circuits checkout equipment, the enable circuits being made up of P-channel enhancement type metal-oxide-semiconductor Q1 and resistance R 1 can guarantee that circuit working is under test mode, by positive-negative-positive triode T2 and NPN type triode T1 and resistance R 4, the base image circuit of R3 composition, this mirror image circuit is used for producing relatively electric current of a standard, by positive-negative-positive triode T2 and NPN type triode T3 and resistance R 4, the current-differencing amplifying circuit of R5 composition, this differential amplifier circuit calculates the poor of reference current and circuit-under-test static leakage current, by positive-negative-positive triode T5 and NPN type triode T4, , the totem-pote circuit that resistance R 7 and R6 and capacitor C 3 form, can matching voltage and improve the driving force of I/O, signal after processing outputs to the I/O mouth of microprocessor through the negative circuit being made up of capacitor C 2 and field effect transistor Q3 and Q2, the voltage signal of output is changed direction by the effect of negative circuit, consistent with actual steering logic, while exporting high level, illustrate that tested cmos circuit belongs to normal, tested cmos circuit existing problems are described when output low level.In order to improve the precision of detection system, resistance R 4 should be consistent with the numerical value of R5, span 5k ~ 10K Ω, and the numerical value of filtering protection capacitor C 2 should be 220uF, and 10K ohm is got in the numerical value suggestion of resistance R 3, R6 and R7, and resistance R 8 values are 100K ohm.
Except above-mentioned, general technical staff of the technical field of the invention also can understand, can further change combination in this explanation and illustrated specific embodiment.For example, the base image current source being made up of 2 triodes can be changed to other type as the mirror current source being formed by 1 amplifier.
Although the present invention gives illustration with regard to its preferred embodiment, person skilled in the art is understood that, in the spirit and scope of the present invention defined in described claims, also can make all changes and variation to the present invention.
Claims (6)
1. a COMS Fault of Integrated Circuits checkout equipment for handheld device, is characterized in that, comprises circuit-under-test, reference circuit, enable circuits, mirror image circuit, differential amplifier circuit, totem-pote circuit, negative circuit; Described circuit-under-test is connected with power supply+V, differential amplifier circuit, mirror image circuit and enable circuits, described reference circuit is connected with mirror image circuit with power supply+V, described enable circuits is connected between circuit-under-test and ground, described mirror image circuit is connected with reference circuit, circuit-under-test and differential amplifier circuit, described differential amplifier circuit is connected with circuit-under-test, mirror image circuit and totem-pote circuit, and described negative circuit is connected between totem-pote circuit and microprocessor I/O port.
2. the COMS Fault of Integrated Circuits checkout equipment of a kind of handheld device as claimed in claim 1, it is characterized in that, described circuit-under-test is made up of the field effect transistor of P raceway groove or the field effect transistor of N raceway groove, this circuit is for generation of the static leakage current signal I_DDQ of tested CMOS, and is transported to mirror image circuit and differential amplifier circuit using this signal as input signal.
3. the COMS Fault of Integrated Circuits checkout equipment of a kind of handheld device as claimed in claim 1, it is characterized in that, described reference circuit is made up of standard field effect transistor, and this circuit is for generation of reference current signal I_REF, and this signal is transported to mirror image circuit as input signal.
4. the COMS Fault of Integrated Circuits checkout equipment of a kind of handheld device as claimed in claim 1, it is characterized in that, described mirror image circuit is made up of base image current source or the mirror current source that is made up of amplifier, by can produce the required comparison current signal of differential amplifier circuit to the coupling of internal resistance.
5. the COMS Fault of Integrated Circuits checkout equipment of a kind of handheld device as claimed in claim 1, is characterized in that, described differential amplifier circuit is made up of 2 precision resisters, 1 NPN type triode and 1 positive-negative-positive triode.
6. the COMS Fault of Integrated Circuits checkout equipment of a kind of handheld device as claimed in claim 1, it is characterized in that, described totem-pote circuit is made up of NPN type triode and positive-negative-positive triode, and described negative circuit is made up of N channel enhancement metal-oxide-semiconductor and P-channel enhancement type metal-oxide-semiconductor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410145168.1A CN103954901A (en) | 2014-04-12 | 2014-04-12 | Device for detecting faults of CMOS integrated circuit of handheld device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410145168.1A CN103954901A (en) | 2014-04-12 | 2014-04-12 | Device for detecting faults of CMOS integrated circuit of handheld device |
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| CN103954901A true CN103954901A (en) | 2014-07-30 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201410145168.1A Pending CN103954901A (en) | 2014-04-12 | 2014-04-12 | Device for detecting faults of CMOS integrated circuit of handheld device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110988440A (en) * | 2019-12-19 | 2020-04-10 | 上海微阱电子科技有限公司 | Current monitoring device and method of CMOS device |
| CN112305450A (en) * | 2019-07-26 | 2021-02-02 | 西安格易安创集成电路有限公司 | Electric leakage detection circuit |
Citations (3)
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|---|---|---|---|---|
| US5808476A (en) * | 1996-07-29 | 1998-09-15 | National Science Council | Built-in current sensor for IDDQ monitoring |
| CN1682122A (en) * | 2002-09-16 | 2005-10-12 | 皇家飞利浦电子股份有限公司 | Apparatus and method for measuring IDDQ |
| CN103261902A (en) * | 2010-12-17 | 2013-08-21 | 晶像股份有限公司 | IDDQ testing of CMOS devices |
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2014
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5808476A (en) * | 1996-07-29 | 1998-09-15 | National Science Council | Built-in current sensor for IDDQ monitoring |
| CN1682122A (en) * | 2002-09-16 | 2005-10-12 | 皇家飞利浦电子股份有限公司 | Apparatus and method for measuring IDDQ |
| CN103261902A (en) * | 2010-12-17 | 2013-08-21 | 晶像股份有限公司 | IDDQ testing of CMOS devices |
Non-Patent Citations (3)
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| H.WARD SLIVER: "《无线电基础电路实作》", 29 July 2011 * |
| 江耀曦等: "CMOS电路IDDQ测试电路设计", 《现代电子技术》 * |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112305450A (en) * | 2019-07-26 | 2021-02-02 | 西安格易安创集成电路有限公司 | Electric leakage detection circuit |
| CN110988440A (en) * | 2019-12-19 | 2020-04-10 | 上海微阱电子科技有限公司 | Current monitoring device and method of CMOS device |
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Application publication date: 20140730 |