CN110988440A - Current monitoring device and method of CMOS device - Google Patents

Current monitoring device and method of CMOS device Download PDF

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Publication number
CN110988440A
CN110988440A CN201911315347.4A CN201911315347A CN110988440A CN 110988440 A CN110988440 A CN 110988440A CN 201911315347 A CN201911315347 A CN 201911315347A CN 110988440 A CN110988440 A CN 110988440A
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power supply
current monitoring
module
resistor
cmos device
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姚清志
卢意飞
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Shanghai Weijing Electronic Technology Co ltd
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Shanghai Weijing Electronic Technology Co ltd
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/25—Arrangements for measuring currents or voltages or for indicating presence or sign thereof using digital measurement techniques

Abstract

The invention discloses a current monitoring device of a CMOS device, which comprises the CMOS device, a current monitoring module, a power supply module and a control module, wherein the control module is simultaneously connected with the power supply module and the current monitoring module; the power supply module supplies power to the CMOS device through the current monitoring module; the current monitoring module monitors the power supply current in the working state of the CMOS device in real time and sends a monitoring result to the control module, and when the monitoring result is abnormal, the control module controls the power supply module to stop supplying power. The current monitoring device and method of the CMOS device can conveniently and accurately monitor the current of the CMOS device in real time, and provide reference basis for stable work of the CMOS device, even chip design and process improvement.

Description

Current monitoring device and method of CMOS device
Technical Field
The invention relates to the field of integrated circuit testing, in particular to a current monitoring device and method of a CMOS device.
Background
In the working process of each CMOS device in the integrated circuit, the control module is usually used for controlling the power supply module to supply power to the CMOS device, however, in the working process of the CMOS device, an effective device or method is not available for monitoring the working state of the CMOS device, and the working state of the CMOS device can be judged according to the result after the CMOS device outputs the result.
Because of numerous occasions of application of the CMOS device, uncertainty of environmental parameters and the like, the working state of the CMOS device can be influenced, if the CMOS device is in a working process, the current of the CMOS device can be greatly changed due to changes of external environment, self configuration and the like, if the working current in the CMOS device is sharply increased, the power consumption of the CMOS device is increased to seriously influence the service life of the CMOS device, if the working current in the CMOS device is sharply increased, the CMOS device is burnt, even the whole set of application system is damaged, and therefore monitoring of the DC parameters of the CMOS device, particularly the current parameters, is more important.
Disclosure of Invention
The invention aims to provide a current monitoring device and a current monitoring method of a CMOS device, which can conveniently and accurately monitor each path of current of the CMOS device in real time and provide reference basis for stable work of the CMOS device, even chip design and process improvement.
In order to achieve the purpose, the invention adopts the following technical scheme: a current monitoring device of a CMOS device comprises the CMOS device, a current monitoring module, a power supply module and a control module, wherein the control module is simultaneously connected with the power supply module and the current monitoring module, and the power supply module is connected with the CMOS device through the current monitoring module;
the power supply module supplies power to the CMOS device through the current monitoring module; the current monitoring module monitors the power supply current in the working state of the CMOS device in real time and sends a monitoring result to the control module, and when the monitoring result is abnormal, the control module controls the power supply module to stop supplying power.
Furthermore, the current monitoring module comprises N current monitoring units, and each current monitoring unit comprises a sampling resistor, a matched filtering subunit and a current monitoring chip; two ends of the sampling resistor are respectively connected with the power supply module and the CMOS device, two ends of the sampling resistor are connected to the current monitoring chip through the matched filtering subunit, and the output end of the current monitoring chip is connected with the control module; n is a positive integer greater than 0.
Further, the matched filter subunit comprises a resistor I, a resistor II and a capacitor, two ends of the sampling resistor are respectively connected with one end of the resistor I and one end of the resistor II, two ends of the capacitor are respectively connected with the other end of the resistor I and the other end of the resistor II, and two ends of the capacitor are simultaneously connected to two input ends of the current monitoring chip.
Furthermore, the resistance values of the resistor I and the resistor II are the same.
Furthermore, the power supply module comprises N power supply units, and the N power supply units correspond to the N current monitoring units one by one; the power supply unit comprises a power supply chip and a voltage reduction resistor, wherein two input ends of the power supply chip are respectively connected with two ends of the voltage reduction resistor, and two ends of the voltage reduction resistor are respectively grounded and connected with the control module.
Furthermore, the current monitoring device also comprises an operation terminal, and the operation terminal is connected with the control module.
Further, the control module is an FPGA or a DSP or an ISP or a singlechip.
A current monitoring method of a CMOS device comprises the following steps:
s01: the control module sends an enabling signal to the power supply module, and the power supply module supplies power to the CMOS device through the current monitoring module;
s02: the CMOS device starts to work;
s03: the current monitoring module monitors the power supply current of the CMOS device in real time and transmits a monitoring result to the control module; if the monitoring result is normal, continuously monitoring the power supply current of the CMOS device until the CMOS device finishes working; if the monitoring result is abnormal, go to step S04;
s04: the control module controls the power supply module to stop supplying power; after waiting the set time, the process returns to step S01.
Further, the step S01 further includes: and the operation terminal sends an operation command to the control module, and the control module sends an enabling signal to the power supply module.
Further, the power supply module comprises N power supply units, and the current monitoring module comprises N current monitoring units; the N power supply units correspond to the N current monitoring units one by one;
in the step S01, the control module sends an enable signal to the N power supply units, and the N power supply units supply power to the CMOS device through the corresponding current monitoring units; in the step S03, when an abnormality occurs in one of the paths of the CMOS devices, the process proceeds to step S04.
The invention has the beneficial effects that: the power supply current of the CMOS device can be conveniently and accurately monitored in real time, and a reference basis is provided for stable work of the CMOS device, even chip design and process improvement; the device has simple circuit, lower cost and easy realization; the invention adopts the resistance-capacitance matching filter unit to collect the power supply current of the CMOS device, and has accurate monitoring result and high precision. In addition, the control center connected with the CMOS device can be integrated with the control module for current monitoring, and the arrangement of integrating the software and hardware resources of the CMOS device and the monitoring device thereof can effectively reduce the occupied area of the CMOS device and the monitoring device thereof and improve the integration level of the CMOS device and the monitoring device thereof.
Drawings
Fig. 1 is a schematic diagram of a current monitoring apparatus of a CMOS device according to the present invention.
FIG. 2 is a flow chart of a current monitoring method of a CMOS device according to the present invention.
Fig. 3 is a circuit diagram of a current monitoring device of the CMOS image sensor in embodiment 1.
Fig. 4 is a circuit diagram of a current monitoring apparatus of a CMOS memory device in embodiment 2.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention are described in detail below with reference to the accompanying drawings.
Referring to fig. 1, a current monitoring apparatus of a CMOS image sensor includes a CMOS device, a current monitoring module, a power module and a control module, wherein the control module is connected to the power module and the current monitoring module at the same time, and the power module is connected to the CMOS device through the current monitoring module. In addition, the current monitoring device can also comprise an operation terminal, and the control module is connected with the operation terminal. The operation terminal can be specifically an upper computer.
Specifically, the CMOS device is a working chip. The power supply module comprises N power supply units; for powering the various circuits in the CMOS device. The current monitoring module comprises N current monitoring units in one-to-one correspondence with the N power supply units, and can adopt a current monitoring chip or a high-precision operational amplifier circuit for carrying out current monitoring on the CMOS device. And the control module controls the switch of the power supply module, receives the output value of the current monitoring module in real time, communicates with the operation terminal, sends the monitoring result to the operation terminal, and receives the instruction of the operation terminal. Through the operation terminal, the staff can send various instructions to the control module. The operation terminal is used as an interaction medium of the whole monitoring device and workers, and can be provided with various command buttons such as start, end and pause. When the CMOS device works normally, a control center is also needed to transmit the control signal and output data of the CMOS device; the control center corresponding to the CMOS device can be integrated with the control module of the detection device or can be separately arranged; the invention focuses on introducing the structure and connection relationship of the monitoring device, and the arrangement modes of the control center and the operation terminal corresponding to the CMOS device do not limit the invention.
The output data is also connected with the operation terminal through the control center, wherein the control center can be integrated with the control module, the connection relation of the whole device is simplified, and the control center can also be independently arranged.
The control module can be specifically an FPGA, a DSP, an ISP, a singlechip or other control circuits, the control module is generally used for analyzing and processing digital signals, and the signals output by the current monitoring module are analog signals, so that the control module comprises an ADC (analog-to-digital converter) which is used for converting the analog signals into the digital signals, and the control module is convenient for analyzing and processing the output results of the current monitoring module.
The power module comprises N power units, each power unit comprises a power chip and a voltage reduction resistor, two input ends of each power chip are respectively connected with two ends of each voltage reduction resistor, and two ends of each voltage reduction resistor are respectively grounded and connected with the control module. The current monitoring module comprises N current monitoring units, and the N power supply units correspond to the N current monitoring units one by one; the current monitoring unit comprises a sampling resistor, a matched filtering subunit and a current monitoring chip; two ends of the sampling resistor are respectively connected with the power supply module and the CMOS device, two ends of the sampling resistor are connected to the current monitoring chip through the matched filtering subunit, and the output end of the current monitoring chip is connected with the control module; n is a positive integer greater than 0. The control module respectively controls each power supply unit, so that when the number of the power supply units is multiple, the control module can only control one power supply unit to supply power, and at the moment, a corresponding circuit in the CMOS device normally works.
Preferably, the matched filter subunit in the invention is a resistance-capacitance matched filter unit, and specifically includes a resistor i, a resistor ii and a capacitor, two ends of the sampling resistor are respectively connected to one end of the resistor i and one end of the resistor ii, two ends of the capacitor are respectively connected to the other end of the resistor i and the other end of the resistor ii, and two ends of the capacitor are simultaneously connected to two input ends of the current monitoring chip. Wherein, the resistance values of the resistor I and the resistor II are the same.
Referring to fig. 2, a method for monitoring a current of a CMOS device according to the present invention includes the following steps:
s01: the control module outputs a high-level enabling signal to an input pin of the power supply chip, and the power supply module supplies power to the CMOS device through the current monitoring module.
When the power supply module comprises N power supply units, the current monitoring module comprises N current monitoring units; the CMOS device also comprises N circuits, wherein the N power supply units, the N current monitoring units and the N circuits are in one-to-one correspondence; the control module respectively controls the N power supply units to start to supply power to the corresponding CMOS device circuits. The control module is connected with the operation terminal, and a worker sends an operation command through the operation terminal.
S02: the CMOS device operates.
S03: the current monitoring circuit monitors the power supply current in the CMOS device in real time and transmits the monitoring result to the control module; if the monitoring result is normal, continuously monitoring the power supply current of the CMOS device until the CMOS device finishes working, and at the moment, actively closing the operation terminal; if the monitoring result is abnormal, the process proceeds to step S04.
When the configuration of the register is changed or the working state of the CMOS device is suddenly changed, the power supply current in the CMOS device can be singly or simultaneously increased/decreased, after the set threshold value is exceeded, the control module records the event at the moment, records the parameters of the configuration of the register and judges that the monitoring result is abnormal.
S04: the control module enables the low level to be output to an input pin of the power supply chip, the power supply module is turned off, and the CMOS device stops working. After waiting the set time, the process returns to step S01.
In the invention, for the CMOS device, the waiting set time is the self error correction process of the CMOS device, and the specific waiting time can be set according to an empirical value or an experimental value. After the CMOS device finishes working, configuration parameters and environment parameters under high current are combined, then an internal circuit of the CMOS device is analyzed, and reliable basis can be provided for CMOS device chip design and subsequent process optimization.
The invention is further explained below with reference to the figures and the specific embodiments:
example 1
Referring to fig. 3, the CMOS device is a CMOS image sensor, the control module is an FPGA, and the FPGA includes an ADC; and the output end of the current monitoring module is connected to the ADC, and the analog signal output by the current monitoring module is subjected to digital signal conversion through the ADC. The power module includes analog power supply unit and digital power supply unit in this embodiment, and analog power supply unit includes power chip U1 and step-down resistor R0, and the both ends of step-down resistor R0 are connected respectively to two input terminals of power chip U1, and the both ends of step-down resistor R0 ground connection respectively and connection control module to make power chip U1's one end receive FPGA's enable signal, one end ground connection. The digital power supply unit comprises a power supply chip U2 and a voltage reduction resistor R1, two input ends of the power supply chip U2 are respectively connected with two ends of the voltage reduction resistor R1, and two ends of the voltage reduction resistor R1 are respectively grounded and connected with the control module, so that one end of the power supply chip U2 receives an enabling signal of the FPGA, and one end of the power supply chip U2 is grounded. When the analog power supply voltage VDDA _ IN and the digital power supply voltage VDDC _ IN need to be turned on, the FPGA outputs a high-level signal, and when the analog power supply voltage VDDA _ IN and the digital power supply voltage VDDC _ IN need to be turned off, the FPGA outputs a low-level signal. The voltage-reducing resistor R0 and the voltage-reducing resistor R1 are used for protecting the input pin EN of the power chip U1 and the power chip U2 and keeping the input pin EN in a pull-down state when the FPGA does not output a high-level signal.
The current monitoring module comprises an analog power supply current monitoring unit and a digital power supply current monitoring unit, wherein the analog power supply current monitoring unit comprises a sampling resistor R2, a first matching filter subunit and an analog power supply current monitoring chip; the two ends of the sampling resistor R2 are respectively connected to the power module and the CMOS device, that is, the two ends of the sampling resistor R2 are respectively the analog power voltage VDDA _ IN output by the power module and the analog power voltage VDDA _ LOAD of the CMOS image sensor, and the analog power current IN this embodiment is the voltage at the two ends of the sampling resistor R2 divided by the resistance of R2. Two ends of the sampling resistor R2 are connected to the analog power supply current monitoring chip through the first matching filtering subunit, and the output end of the analog power supply current monitoring chip is connected with the control module; the first matched filtering subunit comprises a resistor R4, a resistor R5 and a capacitor C1, two ends of a sampling resistor R2 are respectively connected with one end of a resistor R4 and one end of a resistor R5, two ends of a capacitor C1 are respectively connected with the other end of a resistor R4 and the other end of the resistor R5, and two ends of a capacitor C1 are simultaneously connected with two input ends of an analog power supply current monitoring chip U3.
The digital power supply current monitoring unit comprises a sampling resistor R3, a second matched filtering subunit and a digital power supply current monitoring chip; the two ends of the sampling resistor R3 are respectively connected to the power module and the CMOS device, that is, the two ends of the sampling resistor R3 are respectively the digital power supply voltage VDDC _ IN output by the power module and the digital power supply voltage VDDC _ LOAD of the CMOS image sensor, and IN this embodiment, the digital power supply current is the voltage at the two ends of the sampling resistor R3 divided by the resistance value of R3. The two ends of the sampling resistor R3 are connected to the digital power supply current monitoring chip through the second matching filtering subunit, and the output end of the digital power supply current monitoring chip is connected with the control module. The second matched filtering subunit comprises a resistor R6, a resistor R7 and a capacitor C2, two ends of the sampling resistor R3 are respectively connected with one end of the resistor R6 and one end of the resistor R7, two ends of the capacitor C2 are respectively connected with the other end of the resistor R6 and the other end of the resistor R7, and two ends of the capacitor C2 are simultaneously connected with two input ends of the digital power supply current monitoring chip U4. Preferably, R2 and R3 are high-precision sampling resistors with small resistance values, so that low loss of current on the sampling resistors is guaranteed; the resistance values of the resistor R4, the resistor R5, the resistor R6 and the resistor R7 are the same, and the capacitance values of the capacitor C1 and the capacitor C2 are the same. The first matched filtering subunit and the second matched filtering subunit are both resistor-capacitor matched filtering subunits, so that the analog power supply current monitoring chip U3 and the digital power supply current monitoring chip U4 can be ensured to accurately acquire the digital power supply current and the analog power supply current in the CMOS image sensor.
The ADC is connected with the output ends of the U3 and the U4 to complete the conversion of the analog quantity of the digital power supply current and the analog power supply current in the CMOS image sensor to the digital quantity, and preferably, the ADC selects a chip with high sampling rate and high digit.
The FPGA outputs an enabling signal to a pin EN of the power supply chip U1 and the power supply chip U2 through a GPIO (general Purpose Input output); meanwhile, the FPGA receives an instruction of an operation terminal and controls the level of an EN enabling signal; and obtaining the digital power supply current and the analog power supply current in the CMOS image sensor by analyzing the digital quantity converted by the ADC, and sending the current value to the operation terminal through the serial port communication circuit.
The current monitoring method of the CMOS image sensor provided by the present embodiment includes the following steps:
s01: and clicking an operation button on an interface of the operation terminal, sending an operation command by the operation terminal, outputting a high-level enabling signal to input pins of a power chip U1 and a power chip U2 by the control module, and supplying power to the CMOS image sensor by the power module through the current monitoring module.
S02: the CMOS image sensor operates.
S03: the current monitoring circuit monitors the analog power supply current and the digital power supply current in the CMOS image sensor in real time, transmits the monitoring result to the control module and then displays the monitoring result on an operation terminal interface; if the monitoring result is normal, continuously monitoring the power supply current of the CMOS image sensor until the CMOS image sensor finishes working; if the monitoring result is abnormal, the process proceeds to step S04.
S04: and the operation terminal sends a pause command, the control module outputs a low-level enable signal to input pins of the power chip U1 and the power chip U2, the power module is turned off, and the CMOS image sensor stops working. After waiting the set time, the process returns to step S01.
Example 2
Referring to fig. 4, the CMOS device is a CMOS memory device, the control module is a DSP, the DSP includes an ADC, an output terminal of the current monitoring module is connected to the ADC, and an analog signal output by the current monitoring module is converted into a digital signal by the ADC. The power module in this embodiment includes 4 power supply unit, and first power supply unit includes power chip U8 and step-down resistance R8, and the both ends of step-down resistance R8 are connected respectively to two input terminals of power chip U8, and the both ends of step-down resistance R8 ground connection respectively and connection control module to make power chip U8's one end receive DSP's enable signal, one end ground connection.
The second power supply unit comprises a power supply chip U9 and a voltage reduction resistor R9, two input ends of the power supply chip U9 are respectively connected with two ends of the voltage reduction resistor R9, and two ends of the voltage reduction resistor R9 are respectively grounded and connected with the control module, so that one end of the power supply chip U9 receives an enabling signal of the DSP, and one end of the power supply chip U9 is grounded.
The third power supply unit comprises a power supply chip U10 and a voltage reduction resistor R10, two input ends of the power supply chip U10 are respectively connected with two ends of the voltage reduction resistor R10, and two ends of the voltage reduction resistor R10 are respectively grounded and connected with the control module, so that one end of the power supply chip U10 receives an enabling signal of the DSP, and one end of the power supply chip U10 is grounded.
The fourth power supply unit comprises a power supply chip U11 and a voltage reduction resistor R11, two input ends of the power supply chip U11 are respectively connected with two ends of the voltage reduction resistor R11, and two ends of the voltage reduction resistor R11 are respectively grounded and connected with the control module, so that one end of the power supply chip U11 receives an enabling signal of the DSP, and one end of the power supply chip U11 is grounded.
The current monitoring module comprises 4 power supply current monitoring units which are respectively IN one-to-one correspondence with the 4 power supply units, the first power supply current monitoring unit comprises a sampling resistor R12, a resistor R13, a resistor R14, a capacitor C3 and a power supply current monitoring chip U12, two ends of the sampling resistor R12 are respectively connected with the power supply module and the CMOS device, namely two ends of the sampling resistor R12 are respectively the voltage VDDA _ IN output by the first power supply unit and the voltage VDDA _ LOAD of the CMOS memory device. The power current is the voltage across the sampling resistor R12 divided by the resistance of R12. Two ends of the sampling resistor R12 are respectively connected with one end of the resistor R13 and one end of the resistor R14, two ends of the capacitor C3 are respectively connected with the other end of the resistor R13 and the other end of the resistor R14, and two ends of the capacitor C3 are simultaneously connected with two input ends of the power supply current monitoring chip U3.
The second power supply current monitoring unit comprises a sampling resistor R15, a resistor R16, a resistor R17, a capacitor C4 and a power supply current monitoring chip U13, wherein two ends of the sampling resistor R15 are respectively connected with the power supply module and the CMOS device, namely two ends of the sampling resistor R15 are respectively the voltage VDDC _ IN output by the second power supply unit and the voltage VDDC _ LOAD of the CMOS memory device. The power current is the voltage across the sampling resistor R15 divided by the resistance of R15. Two ends of the sampling resistor R15 are respectively connected with one end of the resistor R16 and one end of the resistor R17, two ends of the capacitor C4 are respectively connected with the other end of the resistor R16 and the other end of the resistor R17, and two ends of the capacitor C4 are simultaneously connected with two input ends of the power supply current monitoring chip U13.
The third power supply current monitoring unit comprises a sampling resistor R18, a resistor R19, a resistor R20, a capacitor C5 and a power supply current monitoring chip U14, wherein two ends of the sampling resistor R18 are respectively connected with the power supply module and the CMOS device, namely two ends of the sampling resistor R18 are respectively the voltage VDDP _ IN output by the first power supply unit and the voltage VDDP _ LOAD of the CMOS memory device. The power current is the voltage across the sampling resistor R18 divided by the resistance of R18. Two ends of the sampling resistor R18 are respectively connected with one end of the resistor R19 and one end of the resistor R20, two ends of the capacitor C5 are respectively connected with the other end of the resistor R19 and the other end of the resistor R20, and two ends of the capacitor C5 are simultaneously connected with two input ends of the power supply current monitoring chip U14.
The fourth power supply current monitoring unit comprises a sampling resistor R21, a resistor R22, a resistor R23, a capacitor C6 and a power supply current monitoring chip U15, wherein two ends of the sampling resistor R21 are respectively connected with the power supply module and the CMOS device, namely two ends of the sampling resistor R21 are respectively the voltage VDD _ IN output by the first power supply unit and the voltage VDD _ LOAD of the CMOS memory device. The power current is the voltage across the sampling resistor R21 divided by the resistance of R21. Two ends of the sampling resistor R21 are respectively connected with one end of the resistor R22 and one end of the resistor R23, two ends of the capacitor C6 are respectively connected with the other end of the resistor R22 and the other end of the resistor R23, and two ends of the capacitor C6 are simultaneously connected with two input ends of the power supply current monitoring chip U15.
Preferably, R12, R15, R18 and R21 are high-precision sampling resistors with small resistance values, so that low loss of current on the sampling resistors is guaranteed; the resistance values of the resistor R13, the resistor R14, the resistor R16, the resistor R17, the resistor R19, the resistor R20, the resistor R22 and the resistor R23 are the same, and the capacitance values of the capacitor C3, the capacitor C4, the capacitor C5 and the capacitor C6 are the same. The resistor-capacitor matched filter subunit can ensure that the power supply current monitoring chip accurately acquires the corresponding power supply current in the CMOS memory device.
The ADC is connected with the output ends of the U12, the U13, the U14 and the U15 to complete the conversion of the analog quantity to the digital quantity of the four paths of power supply currents in the CMOS memory device, and preferably, the ADC selects a chip with high sampling rate and high digit.
The DSP outputs an enabling signal to a pin of the power supply chip; meanwhile, the DSP receives an instruction of the operation terminal and controls the high and low of the EN enabling signal; and analyzing the digital quantity converted by the ADC to obtain the power supply current of each circuit in the CMOS memory device, and transmitting the current value to the operation terminal through the serial port communication circuit.
The current monitoring method of the CMOS memory device provided by the embodiment comprises the following steps:
s01: and clicking an operation button on an operation terminal interface, sending an operation command by the operation terminal, outputting a high-level enable signal to input pins of a power chip U8, a power chip U9, a power chip U10 and a power chip U11 by a control module, and supplying power to the CMOS memory device by the power module through a current monitoring module.
S02: the CMOS memory device operates.
S03: the current monitoring circuit monitors the current of each power supply in the CMOS memory device in real time, transmits the monitoring result to the control module and displays the monitoring result on an operation terminal interface; if the monitoring result is normal, continuously monitoring the power supply current of the CMOS memory device until the CMOS memory device finishes working; if the monitoring result is abnormal, the process proceeds to step S04.
S04: the operation terminal sends a pause command, the control module outputs a low-level enable signal to input pins of the power chip U8, the power chip U9, the power chip U10 and the power chip U11, the power module is turned off, and the CMOS memory device stops working. After waiting the set time, the process returns to step S01.
The above description is only a preferred embodiment of the present invention, and the embodiment is not intended to limit the scope of the present invention, so that all equivalent structural changes made by using the contents of the specification and the drawings of the present invention should be included in the scope of the appended claims.

Claims (10)

1. The current monitoring device of the CMOS device is characterized by comprising the CMOS device, a current monitoring module, a power supply module and a control module, wherein the control module is simultaneously connected with the power supply module and the current monitoring module, and the power supply module is connected with the CMOS device through the current monitoring module;
the power supply module supplies power to the CMOS device through the current monitoring module; the current monitoring module monitors the power supply current in the working state of the CMOS device in real time and sends a monitoring result to the control module, and when the monitoring result is abnormal, the control module controls the power supply module to stop supplying power.
2. The current monitoring device of a CMOS device according to claim 1, wherein the current monitoring module comprises N current monitoring units, the current monitoring units comprising a sampling resistor, a matched filter subunit and a current monitoring chip; two ends of the sampling resistor are respectively connected with the power supply module and the CMOS device, two ends of the sampling resistor are connected to the current monitoring chip through the matched filtering subunit, and the output end of the current monitoring chip is connected with the control module; n is a positive integer greater than 0.
3. The current monitoring device of claim 2, wherein the matched filter subunit comprises a resistor i, a resistor ii and a capacitor, two ends of the sampling resistor are respectively connected to one end of the resistor i and one end of the resistor ii, two ends of the capacitor are respectively connected to the other end of the resistor i and the other end of the resistor ii, and two ends of the capacitor are simultaneously connected to two input ends of the current monitoring chip.
4. The current monitoring device of claim 3, wherein the resistance values of the resistor I and the resistor II are the same.
5. The current monitoring device of a CMOS device according to claim 2, wherein the power supply module includes N power supply units, and the N power supply units and the N current monitoring units correspond to each other one by one; the power supply unit comprises a power supply chip and a voltage reduction resistor, wherein two input ends of the power supply chip are respectively connected with two ends of the voltage reduction resistor, and two ends of the voltage reduction resistor are respectively grounded and connected with the control module.
6. The current monitoring device of claim 1, further comprising an operation terminal, wherein the operation terminal is connected to the control module.
7. The current monitoring device of a CMOS device according to claim 1, wherein the control module is an FPGA, a DSP, an ISP, or a single chip microcomputer.
8. A current monitoring method of a CMOS device is characterized by comprising the following steps:
s01: the control module sends an enabling signal to the power supply module, and the power supply module supplies power to the CMOS device through the current monitoring module;
s02: the CMOS device starts to work;
s03: the current monitoring module monitors the power supply current of the CMOS device in real time and transmits a monitoring result to the control module; if the monitoring result is normal, continuously monitoring the power supply current of the CMOS device until the CMOS device finishes working; if the monitoring result is abnormal, go to step S04;
s04: the control module controls the power supply module to stop supplying power; after waiting the set time, the process returns to step S01.
9. The method for monitoring current of a CMOS device according to claim 7, wherein said step S01 further comprises: and the operation terminal sends an operation command to the control module, and the control module sends an enabling signal to the power supply module.
10. The method of claim 8, wherein the power module comprises N power units, and the current monitoring module comprises N current monitoring units; the N power supply units correspond to the N current monitoring units one by one;
in the step S01, the control module sends an enable signal to the N power supply units, and the N power supply units supply power to the CMOS device through the corresponding current monitoring units; in the step S03, when an abnormality occurs in one of the paths of the CMOS devices, the process proceeds to step S04.
CN201911315347.4A 2019-12-19 2019-12-19 Current monitoring device and method of CMOS device Pending CN110988440A (en)

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