CN219245712U

CN219245712U - Verification device of voltage reference chip

Info

Publication number: CN219245712U
Application number: CN202320103635.9U
Authority: CN
Inventors: 赵云杰; 廖宏宾
Original assignee: Xi An Faraday Electronic Technology Co ltd
Current assignee: Xi An Faraday Electronic Technology Co ltd
Priority date: 2023-02-03
Filing date: 2023-02-03
Publication date: 2023-06-23
Anticipated expiration: 2033-02-03

Abstract

The utility model provides a verification device of a voltage reference chip, which comprises a verification board, a power supply and an upper computer, wherein the verification board comprises a control circuit and a test circuit, the control circuit comprises an STM32 chip and load control, the test circuit comprises an adjustable power supply, a chip to be tested, a current monitoring module for testing working current and voltage of the chip to be tested and a load network for realizing output resistance load of the chip to be tested, the control circuit is used for controlling three parameters of the power supply voltage, the output reference voltage and the load of the chip to be tested, the adjustable power supply is in signal connection with the current monitoring module, the current monitoring module is in signal connection with the chip to be tested and the STM32 chip, and the load network is in signal connection with the STM32 chip and the chip to be tested. The utility model simplifies the original chip verification device, so that the device has the characteristics of simple structure and convenient use.

Description

Verification device of voltage reference chip

Technical Field

The utility model mainly relates to the technical field of chip verification, in particular to a verification device of a voltage reference chip.

Background

The chip verification technology is to verify whether the chip design meets the requirement specification defined by the chip or not by adopting a corresponding verification language, a verification tool and a verification method before the chip is produced, and whether the risk is completely released or not, and the chip verification technology is a countermeasure against the problem in the aspect of the whole process.

At present, the technical threshold in the chip field is high, the investment is large, the return period is long, the failure risk is high, and the chip is easily changed into a so-called stone due to design defects or process defects, and the risks are not acceptable for commercial companies. The importance of verification is highlighted just because of the high risk of the chip.

The chip verification technology is mainly to design and realize verification environment according to the specification and characteristics of the chip; and according to the specification of the chip or the module, performing verification and regression by using the realized verification environment. The current verification device of the chip is complex in structure, so that the chip is difficult to manufacture and complicated to use.

Disclosure of Invention

The technical scheme of the utility model aims at the technical problem that the prior art is too single, provides a solution which is obviously different from the prior art, and mainly provides a verification device of a voltage reference chip, so as to solve the technical problems of complex structure and inconvenient use of the prior chip verification device in the prior art.

The technical scheme adopted for solving the technical problems is as follows:

the utility model provides a verifying attachment of voltage reference chip, includes verification board, power and host computer, the verification board includes control circuit and test circuit, control circuit includes STM32 chip and load control, test circuit includes adjustable power, awaits measuring the chip, is used for testing the current monitoring module of awaiting measuring chip working current and voltage and is used for realizing the load network of awaiting measuring the chip output resistance load, control circuit is used for controlling the power voltage of awaiting measuring the chip, output reference voltage and three kinds of parameters of load, adjustable power and current monitoring module signal connection, current monitoring module and awaiting measuring chip, STM32 chip signal connection, load network and STM32 chip, awaiting measuring chip signal connection, current monitoring module includes the charge monitor.

Preferably, the STM32 chip is in communication connection with the host computer through a network port.

Preferably, the working voltage range of the chip to be tested is 1.2V to 40V.

Preferably, the resistance load is connected to the output end of the chip to be tested, and the charge monitor is an analog-to-digital converter.

Preferably, the load network adopts a digital potentiometer resistor network with a resolution of 8 bits: 255 resistors.

Preferably, the charge monitor employs INA228, and INA228 integrates an amplifier, ADC and digital interface, and monitors the voltage and operating current of the chip to be tested by sampling the voltage drop across the resistor.

Preferably, the output of the voltage reference is led out to the data acquisition system by adopting an SMA connector and a coaxial shielding wire.

Preferably, the adjustable power supply is implemented by a linear voltage regulator that can adjust the output voltage.

Compared with the prior art, the utility model has the beneficial effects that:

the utility model discloses verifying plate comprises control circuit and test circuit, STM32 chip and load control constitute control circuit end, and adjustable power, current monitoring module, chip and the resistance load that awaits measuring constitute test circuit end, simplify original chip verifying attachment for this device has simple structure, convenient to use's characteristics.

The utility model will be explained in detail below with reference to the drawings and specific embodiments.

Drawings

FIG. 1 is a general explanatory view of a verification apparatus of the present utility model;

FIG. 2 is a circuit frame diagram of the present utility model;

FIG. 3 is a schematic diagram of an adjustable power supply of the present utility model;

FIG. 4 is a schematic diagram of a static circuit test circuit according to the present utility model;

fig. 5 is a schematic diagram of an adjustable load network of the present utility model.

Detailed Description

In order that the utility model may be more fully understood, a more particular description of the utility model will be rendered by reference to the appended drawings, in which several embodiments of the utility model are illustrated, but which may be embodied in different forms and are not limited to the embodiments described herein, which are, on the contrary, provided to provide a more thorough and complete disclosure of the utility model.

Referring to fig. 1 and 2, the present utility model provides a technical solution: the utility model provides a verifying attachment of voltage reference chip, includes verification board, power and host computer, the verification board includes control circuit and test circuit, control circuit includes STM32 chip and load control, STM32 chip passes through net gape and host computer telecommunication connection, control circuit is used for controlling the power supply voltage of the chip that awaits measuring, the three kinds of parameters of output reference voltage and load, adjustable power and current monitoring module signal connection, current monitoring module and chip that awaits measuring, STM32 chip signal connection, load network and STM32 chip, chip signal connection that awaits measuring, voltage reference output adopts SMA to connect and coaxial shield line to draw forth data acquisition system, reduces the interference and improves the test accuracy.

Referring to fig. 1-3, the test circuit includes an adjustable power supply, a chip to be tested, a current monitoring module for testing the working current and voltage of the chip to be tested, and a load network for realizing the output resistance load of the chip to be tested. The working voltage range of the chip to be tested is 1.2V to 40V, the output power range of the adjustable power supply is 1.8V to 5.5V, the power supply voltage is realized by adopting an adjustable output linear voltage stabilizer ADP7142, the ADP7142 can input the highest voltage of 40V, the current of 200mA is output, and the SOP8 is packaged. STM32 uses digital potentiometer MCP45HV51 as an output voltage setting resistor to control the output voltage. The output voltage is led out to a data acquisition system by a coaxial line to realize a self-checking function, and the principle is shown in figure 3 of the attached drawing.

Referring to fig. 1, 2 and 4, the current monitoring module includes a charge monitor, the charge monitor employs an INA228, the INA228 integrates an amplifier, an ADC and a digital interface, and the charge monitor monitors the voltage and the operating current of the chip to be tested through the voltage drop across the sampling resistor. The current monitoring module is formed by connecting a charge monitor with a DAC, and is mainly used for testing the static working current of a chip to be tested, the charge monitor adopts a high-resolution 20-bit delta-sigma analog-digital converter, and the current monitoring precision is as follows: offset voltage maximum 1uV; offset drift ± 0.01uV/°c; gain error ± 0.05%; gain error drift ± 20ppm/°c; common mode rejection 145dB, the charge monitor employs INA228, INA228 integrates an amplifier, ADC and digital interface, and voltage and operating current of the chip to be tested can be monitored by sampling voltage drop across the resistor, the principle being described with reference to figure 4 of the drawings.

Referring to fig. 1, 2 and 5, the load control and the resistive load are combined to form an adjustable load network, and the resolution of the digital potentiometer resistor network adopted by the adjustable load network is 8 bits: 255 resistors, the RAB resistance options can be divided into 5KΩ, 10KΩ, 50KΩ, 100KΩ. Having an I2C serial interface and volatile memory. The resistance load is connected to the output end of the chip to be tested, and the STM32 can control and modify the output current of the chip to be tested to 0mA/25mA. The load control and the resistance load are composed of a digital potentiometer and two SPST analog switches, as shown in figure 5 of the accompanying drawings.

The MCU controls the on and off of the analog switch through the GPIO, and the I2C bus controls the resistance of the digital potentiometer, so that the load of the JS3012 can be controlled. The analog switch was turned off and the load was 0mA. The analog switch is closed, and the specific digital potentiometer RW value is set, so that the load current can be set. Another analog switch is used for self-checking, and STM32 can detect whether the digital potentiometer fails by detecting the resistance value.

While the utility model has been described above with reference to the accompanying drawings, it will be apparent that the utility model is not limited to the embodiments described above, but is intended to be within the scope of the utility model, as long as such insubstantial modifications are made by the method concepts and technical solutions of the utility model, or the concepts and technical solutions of the utility model are applied directly to other occasions without any modifications.

Claims

1. The utility model provides a verifying attachment of voltage reference chip, includes verification board, power and host computer, its characterized in that: the verification board comprises a control circuit and a test circuit, wherein the control circuit comprises an STM32 chip and load control, the test circuit comprises an adjustable power supply, a chip to be tested, a current monitoring module for testing working current and voltage of the chip to be tested and a load network for realizing output resistance load of the chip to be tested, the control circuit is used for controlling three parameters of power supply voltage, output reference voltage and load of the chip to be tested, the adjustable power supply is in signal connection with the current monitoring module, the current monitoring module is in signal connection with the chip to be tested and the STM32 chip, the load network is in signal connection with the STM32 chip and the chip to be tested, and the current monitoring module comprises a charge monitor.

2. The device for verifying a voltage reference chip of claim 1, wherein: and the STM32 chip is in communication connection with the upper computer through a network port.

3. The device for verifying a voltage reference chip of claim 1, wherein: the working voltage range of the chip to be tested is 1.2V to 40V.

4. The device for verifying a voltage reference chip of claim 1, wherein: the resistance load is connected with the output end of the chip to be tested, and the charge monitor is an analog-digital converter.

5. The device for verifying a voltage reference chip of claim 1, wherein: the resolution of the digital potentiometer resistor network adopted by the load network is 8 bits: 255 resistors.

6. The device for verifying a voltage reference chip of claim 1, wherein: the charge monitor employs INA228, and INA228 integrates an amplifier, ADC and digital interface, and monitors the voltage and operating current of the chip to be tested by sampling the voltage drop across the resistor.

7. The device for verifying a voltage reference chip of claim 1, wherein: and the output of the voltage reference is led out to a data acquisition system by adopting an SMA connector and a coaxial shielding wire.

8. The device for verifying a voltage reference chip of claim 1, wherein: the adjustable power supply is realized by a linear voltage stabilizer capable of adjusting output voltage.