CN102064813A - Latching prevention circuit - Google Patents
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Abstract
The invention discloses a latching prevention circuit, which comprises a first comparator, a second comparator, an exclusive or gate, an even level series phase inverter and a first switch transistor, wherein the first comparator outputs a low level when the voltage of the core circuit is smaller than a predetermined voltage, otherwise, outputs a high level; the second comparator outputs a low level when the voltage of the core circuit is smaller than the lowest voltage thereof during normal work, otherwise, outputs a high level; two input ends of the exclusive or gate are connected with the output ends of the first comparator and the second comparator respectively, and the output end of the exclusive or gate is connected with the input end of the even level series phase inverter; and in the first switch transistor, the grid is connected with the output end of the even level series phase inverter, the source is connected with a working power supply, and the drain is connected with one end of the working voltage of the core circuit. The latching prevention circuit can prevent a complementary metal oxide semiconductor (CMOS) integrated circuit from being damaged due to the influence of latching effect.
Description
Technical Field
The present invention relates to integrated circuit design, and more particularly to a Latch-up (Latch-up) prevention circuit.
Background
Latch-up, also known as parasitic Silicon Controlled Rectifier (SCR) effect or parasitic PNPN effect. Under the CMOS Transistor of the whole body, PN junctions are formed among doped regions with different polarities, and two adjacent PN junctions in opposite directions form a Bipolar Junction Transistor (BJT). Therefore, the CMOS transistors are formed with transistors below, and the transistors themselves may form a circuit, which is the parasitic transistor effect of the MOS transistors. If the circuit occasionally has conditions, such as over-voltage, large current, ionizing radiation (ionization radiation), etc., which can make the transistor conduct, the parasitic circuit will greatly affect the normal operation of the circuit, and the core circuit (core circuit) containing the CMOS device will be exposed to much larger current than the normal operation, which may cause the circuit to burn out rapidly. In the latch-up state, a short circuit is formed between the operating power supply (VDD) and the ground power supply (GND or VSS), causing an instantaneous large current and an instantaneous drop in voltage.
The latch-up effect is not obvious in the process of large line width, and the smaller the line width is, the lower the reaction voltage of the parasitic triode is, and the more obvious the influence of the latch-up effect is. Therefore, CMOS integrated circuits manufactured today using deep sub-micron manufacturing processes are more susceptible to latch-up damage than large scale integrated circuits.
In the prior art, a method for preventing latch-up of Layout level (Layout) is shown in fig. 1, where P is added between a PMOS transistor and an NMOS transistor+Guard rings (guard-rings) G11 and N+Guard ring G12, which increases well contacts (well contacts) and increases the layout area between PMOS and NMOS transistors. Yet another process level method for preventing latch-up, as shown in fig. 2, uses Silicon-on-Insulator (SOI) technology, which introduces a Buried Oxide (Buried Oxide) B1 between the Silicon substrate S1 and the device layer L1, which increases the complexity of the process.
Disclosure of Invention
The invention solves the problem of providing a latch-up prevention circuit to prevent the CMOS integrated circuit from being damaged by the latch-up effect.
To solve the above problem, an embodiment of the present invention provides a circuit for preventing latch-up, including: a first comparator, a second comparator, an exclusive-or gate, an even-numbered stage of serially connected inverters and a first switching transistor, wherein,
the first comparator outputs a low level when the voltage of the core circuit (connected with one end of the working voltage) is less than a preset voltage, otherwise outputs a high level, and the second comparator outputs a low level when the voltage of the core circuit is less than the lowest voltage of the core circuit in normal working, otherwise outputs a high level; or,
the first comparator outputs a high level when the voltage of the core circuit is smaller than a preset voltage, otherwise outputs a low level, and the second comparator outputs a high level when the voltage of the core circuit is smaller than the lowest voltage of the core circuit in normal operation, otherwise outputs a high level;
two input ends of the exclusive-OR gate are respectively connected with output ends of the first comparator and the second comparator, an output end of the exclusive-OR gate is connected with an input end of the even-numbered serial phase inverter,
the grid electrode of the first switch transistor is connected with the output end of the even-level serial inverter, the source electrode of the first switch transistor is connected with a working power supply, and the drain electrode of the first switch transistor is connected with one end of the core circuit connected with the working voltage.
The technical scheme provides a circuit-level latch-up prevention method, which detects the voltage of a CMOS integrated circuit (core circuit) through a comparator, and closes a switch transistor connected between a working power supply and the CMOS integrated circuit when the detected voltage is lower than the lowest voltage during normal operation and higher than a preset voltage (namely, is instantly reduced), namely, closes a path from the working power supply to the CMOS integrated circuit, so as to cut off a current path of the CMOS integrated circuit, therefore, large current cannot flow into the CMOS integrated circuit, and the CMOS integrated circuit is prevented from being damaged due to the influence of the large current caused by latch-up effect.
Compared with the existing layout-level latch-up prevention method, the circuit of the technical scheme has the advantages of simple structure, small occupied layout area and no increase of well contact; the above solution does not increase the complexity of the process compared to the prior art process-level methods of preventing latch-up.
Drawings
FIG. 1 is a schematic diagram of a prior art arrangement for preventing latch-up;
FIG. 2 is a schematic diagram of a prior art stage latch prevention structure;
FIG. 3 is a schematic diagram of one embodiment of a latch prevention circuit of the present invention;
FIG. 4 is a schematic diagram of another embodiment of the latch prevention circuit of the present invention;
FIG. 5 is a schematic diagram of one embodiment of the latch prevention circuit of the present invention;
FIG. 6 is a schematic diagram of one embodiment of a discharge cell of the latch-up prevention circuit of the present invention;
FIG. 7 is a schematic diagram of another embodiment of a discharge cell of the latch-up prevention circuit of the present invention;
fig. 8 is a schematic diagram of another embodiment of the latch prevention circuit of the present invention.
Detailed Description
The embodiment of the invention provides a circuit-level latch-up prevention method, which is characterized in that when the voltage of a core circuit is detected to be reduced instantly, a path from a working power supply to the core circuit is closed, so that a power supply path from the working power supply to the core circuit is cut off, and thus, a large current cannot flow into the core circuit, the influence of the large current on the core circuit caused by a latch-up effect is prevented, and devices of the core circuit are prevented from being damaged.
The circuit for preventing latch-up according to the embodiment of the present invention includes: a voltage detection unit that detects a voltage of the core circuit; and the switch unit is controlled by the voltage detection unit and closes a path from a power supply to the core circuit when the detected voltage is lower than the lowest voltage of the core circuit during normal operation and higher than a preset voltage.
The core circuit is a CMOS integrated circuit, is connected between a working power supply and a grounding power supply, provides working voltage by the working power supply and the grounding power supply, and detects the voltage of the core circuit by a voltage detection unit, namely detects the voltage of a connection node of the working power supply and the core circuit. The minimum voltage of the core circuit during normal operation can be determined by the specification (Spec.) of the circuit, for example, in a 0.13 μm process, the minimum voltage can be 2.9-3V. The predetermined voltage is a holding voltage (voltage for triggering the parasitic SCR) of the core circuit, and is closely related to the structure, actual process condition and layout design of the parasitic SCR, for example, in a 0.13 μm process, the predetermined voltage is slightly greater than 1V, and may generally be 1.2-1.4V.
One embodiment of the latch-up prevention circuit of the present invention is shown in fig. 3, and includes a voltage detection unit 11 and a switch unit 21, wherein the voltage detection unit 11 detects a voltage VDD _ core of the core circuit 10, and the switch unit 21 closes a path from the operating power VDD to the core circuit 10 when the voltage VDD _ core detected by the voltage detection unit 11 is lower than a minimum voltage of the core circuit 10 during normal operation and higher than a predetermined voltage.
When the latch-up occurs, the parasitic SCR of the core circuit 10 is triggered (or the parasitic transistor of the MOS transistor is turned on), the voltage VDD _ core of the core circuit 10 is pulled down instantaneously (lower than the lowest voltage of the core circuit 10 during normal operation and higher than a predetermined voltage), and a large current is generated between the operating power supply VDD and the ground power supply GND, which flows from the operating power supply VDD to the ground power supply GND through the core circuit 10. The first control signal CT1 generated when the voltage detection unit 11 detects that the voltage VDD _ core is momentarily lowered triggers the switch unit 21 to close the path from the operating power VDD to the core circuit 10, and the large current is cut off in the path of the core circuit 10, thereby preventing the core circuit 10 from being affected or even damaged by the large current caused by the latch-up effect.
The latch-up prevention circuit of the present embodiment may further include a discharge unit 31 connected between the operating power supply VDD and the ground power supply GND, and discharging when a current between the operating power supply VDD and the ground power supply GND exceeds a predetermined current. The predetermined current may typically be greater than the transient maximum current for normal operation of the core circuitry, for example, 10 times the transient maximum current for normal operation of the core circuitry.
The discharge unit 31 can effectively conduct a large current from the operating power supply VDD (high voltage source) to the ground power supply GND (low voltage source) when a large current (exceeding a predetermined current) is generated between the operating power supply VDD and the ground power supply GND to quickly bypass the large current due to latch-up. Before the switching unit 21 turns off the path from the operating power supply VDD to the core circuit 10 due to the generation of a large current, the discharging unit 31 may shunt a portion of the large current, so as to protect the core circuit 10 from being damaged by the impact of the large current. In addition, when an electrostatic discharge occurs, the discharge unit 31 can be turned on rapidly to form a discharge path between the operating power supply VDD and the ground power supply GND, so as to further provide electrostatic protection for the core circuit 10 to prevent the core circuit from being impacted by the electrostatic discharge pulse.
In this embodiment, the switch unit 21 turns on a path from the operating power supply VDD to the core circuit 10 when the voltage VDD _ core detected by the voltage detection unit 11 is not lower than the lowest voltage or not higher than a predetermined voltage when the core circuit 10 normally operates. For example, when the voltage VDD _ core of the core circuit 10 is reduced to be less than the predetermined voltage or the core circuit 10 is in the normal operating state, the first control signal CT1 generated by the voltage detection unit 21 triggers the switch unit 21 to turn on the path from the operating power VDD to the core circuit 10, so that the core circuit 10 returns to the normal operating state. In other embodiments, the switch unit 21 may be triggered by other circuits having the same function as described above to turn on the path from the operating power supply VDD to the core circuit 10.
Another embodiment of the latch-up prevention circuit of the present invention is shown in fig. 4, and comprises a voltage detection unit 12, a first switch unit 22 and a second switch unit 23, wherein the voltage detection unit 12 detects the voltage VDD _ core of the core circuit 10 and outputs a first control signal CT1 and a second control signal CT 2; the first switching unit 22 is controlled by a first control signal CT1 to close the path from the operating power supply VDD to the core circuit 10 when the voltage VDD _ core detected by the voltage detection unit 12 is lower than the lowest voltage of the core circuit 10 during normal operation and higher than a predetermined voltage; the second switching unit 23 is controlled by the second control signal CT2 to close the path from the core circuit 10 to the ground power GND when the voltage VDD _ core detected by the voltage detecting unit 12 is lower than the lowest voltage of the core circuit 10 in normal operation and higher than a predetermined voltage.
In addition, the first switching unit 22 turns on a path from the operating power supply VDD to the core circuit 10 when the voltage VDD _ core detected by the voltage detecting unit 12 is not lower than the lowest voltage or not higher than a predetermined voltage when the core circuit 10 normally operates; the second switching unit 23 turns on a path from the core circuit 10 to the ground power GND when the voltage VDD _ core detected by the voltage detecting unit 12 is not lower than the lowest voltage at which the core circuit 10 normally operates or is not higher than a predetermined voltage.
When the latch-up occurs, the parasitic SCR of the core circuit 10 is triggered (or the parasitic transistor of the MOS transistor is turned on), the voltage VDD _ core of the core circuit 10 is pulled down instantaneously (lower than the lowest voltage of the core circuit 10 during normal operation and higher than a predetermined voltage), and a large current is generated between the operating power supply VDD and the ground power supply GND, which flows from the operating power supply VDD to the ground power supply GND through the core circuit 10. When the voltage detection unit 11 detects that the voltage VDD _ core is momentarily lowered, the first control signal CT1 and the second control signal CT2 respectively trigger the first switch unit 22 and the second switch unit 23, the first switch unit 22 will close the path from the operating power VDD to the core circuit 10, the second switch unit 22 will close the path from the core circuit 10 to the ground power GND, and the large current is cut off in the path of the core circuit 10, so as to prevent the core circuit 10 from being affected or even damaged by the large current caused by the latch-up effect.
The embodiments of the present invention will be described in further detail with reference to the drawings and examples.
One embodiment of the latch prevention circuit of the present invention is shown in fig. 5, which corresponds to the circuit of the embodiment shown in fig. 3. With reference to fig. 3 and 5, the circuit for preventing latch-up of the present embodiment includes: a voltage detection unit 11, a switching unit 21, and a discharge unit 31. The voltage detection unit 11 is connected to the first terminal a (connected to one end of the operating voltage) of the core circuit 10, and can detect the voltage of the core circuit 10 in real time, that is, the voltage VDD _ core of the first terminal a, the switch unit 21 is connected between the operating power VDD and the first terminal a of the core circuit 10, the discharge unit 31 is connected between the operating power VDD and the ground power GND, and the second terminal B of the core circuit 10 is connected to the ground power, that is, grounded.
The voltage detection unit 11 includes a first comparator 11a, a second comparator 11b, an exclusive or gate 11c, and an even-numbered stage of inverters connected in series, which are two-stage inverters in this embodiment, i.e., a first inverter Inv1 and a second inverter Inv 2.
The first comparator 11a compares the voltage VDD _ core of the core circuit 10 with the voltage value of the first reference voltage Vref1, outputs a low level when the voltage VDD _ core of the core circuit 10 is less than the first reference voltage Vref1, and outputs a high level when the voltage VDD _ core of the core circuit 10 is equal to or greater than the first reference voltage Vref 1. The first reference voltage Vref1 is a predetermined voltage, i.e., the holding voltage of the parasitic SCR of the core circuit, and in practical applications, the first reference voltage Vref1 is slightly higher than the holding voltage of the parasitic SCR. The second comparator 11b compares the voltage VDD _ core of the core circuit 10 with the voltage value of the second reference voltage Vref2, outputs a low level when the voltage VDD _ core of the core circuit 10 is less than the second reference voltage Vref2, and outputs a high level when the voltage VDD _ core of the core circuit 10 is equal to or greater than the second reference voltage Vref 2. The second reference voltage Vref2 is the lowest voltage of the core circuit 10 during normal operation, and in practical applications, the second reference voltage Vref2 is slightly lower than the lowest voltage of the core circuit 10 during normal operation.
In other embodiments, the first comparator 11a may output a high level when the voltage VDD _ core of the core circuit 10 is less than the first reference voltage Vref1, and output a low level when the voltage VDD _ core of the core circuit 10 is greater than or equal to the first reference voltage Vref 1. The second comparator 11b outputs a high level when the voltage VDD _ core of the core circuit 10 is less than the second reference voltage Vref2, and outputs a low level when the voltage VDD _ core of the core circuit 10 is equal to or greater than the second reference voltage Vref 2.
The inputs of the exclusive or gate 11c include the output of the first comparator 11a and the output of the second comparator 11b, i.e. two inputs of the exclusive or gate 11c are connected to the outputs of the first comparator 11a and the second comparator 11b, respectively. The exclusive or gate 11c outputs a high level when the output of the first comparator 11a and the output of the second comparator 11b are different, and outputs a low level when the output of the first comparator 11a and the output of the second comparator 11b are the same.
The output of the xor gate 11c passes through the first inverter Inv1 and the second inverter Inv2, and generates the first control signal CT 1. The output of the xor gate 11c may also be directly output as the first control signal CT 1.
The switch unit 21 includes a first switch transistor MP1, the first switch transistor MP1 is a PMOS transistor, the gate of which is connected to the output terminal of the even-numbered stage series-connected inverter, i.e., the output terminal of the second inverter Inv2 of the voltage detection unit 11 (i.e., controlled by the first control signal CT 1), the source of which is connected to the operating power supply VDD, and the drain of which is connected to the first terminal a of the core circuit 10.
In a normal operation state, the voltage VDD _ core of the core circuit 10 is greater than or equal to the lowest voltage during normal operation, i.e., greater than or equal to the first reference voltage Vref1, and greater than the second reference voltage Vref2, the first comparator 11a and the second comparator 11b output a high level, so that the xor gate 11c outputs a low level, the first switch transistor MP1 is turned on, and the power supply path of the core circuit 10 is in an on state.
When the latch-up occurs, the voltage VDD _ core of the core circuit 10 is momentarily pulled down to the holding voltage of the parasitic SCR, and when the voltage VDD _ core of the core circuit 10 is lowered to be less than the lowest voltage during normal operation and not lowered to the holding voltage of the parasitic SCR, i.e., greater than the first reference voltage Vref1 and less than the second reference voltage Vref2, the first comparator 11a outputs a high level, and the second comparator 11b outputs a low level, so that the xor gate outputs a high level, and the first switching transistor MP1 is turned off, thereby turning off the power supply path to the core circuit 10. That is, before the voltage VDD _ core of the core circuit 10 is pulled down to the holding voltage of the parasitic SCR, the power supply path of the core circuit 10 is cut off, and the large current generated by the latch-up effect does not flow through the core circuit 10, and the latch-up effect is eliminated.
Since the power supply path of the core circuit 10 is cut off, the voltage VDD _ core of the core circuit 10 is lowered to be less than the holding voltage of the parasitic SCR, i.e., less than the first reference voltage Vref1 and the second reference voltage Vref2, the first comparator 11a and the second comparator 11b output a low level, so that the xor gate 11c outputs a low level, the first switch transistor MP1 is turned on, and at this time, after the latch-up effect is eliminated, the core circuit 10 returns to the normal operation state.
The discharge unit 31 of the present embodiment may be an electrostatic discharge (ESD) circuit as shown in fig. 6, including: capacitor Ca, resistance Ra and discharge transistor MN4, discharge transistor MN4 is an NMOS transistor. One end of the capacitor Ca is connected to the operating power supply VDD, the other end of the capacitor Ca is connected to one end of the resistor Ra and the gate of the discharge transistor MN4, the other end of the resistor Ra is connected to the ground power supply GND, the drain of the discharge transistor MN4 is connected to the operating power supply VDD, and the source thereof is connected to the ground power supply GND.
In a normal operation state, the gate voltage of the discharge transistor MN4 is low, and the discharge transistor MN4 is turned off. When a large current (latch-up) occurs between the operating power supply VDD and the ground power supply GND or an electrostatic discharge occurs, the gate voltage of the discharging transistor MN4 rises rapidly, so that the parasitic transistor of the discharging transistor MN4 is turned on rapidly to discharge, and the large current is guided from the operating power supply VDD to the ground power supply GND.
Based on a similar operation principle, the discharge unit 31 may also be an electrostatic discharge circuit as shown in fig. 7, including: the capacitor Cb, the resistor Rb, the third inverter Inv3, and the discharge transistor MN4, where the discharge transistor MN4 is an NMOS transistor. One end of the capacitor Cb is connected to the ground power GND, the other end of the capacitor Cb is connected to one end of the resistor Rb and the input end of the third inverter Inv3, the output end of the third inverter Inv3 is connected to the gate of the discharge transistor MN4, the other end of the resistor Rb is connected to the operating power VDD, the drain of the discharge transistor MN4 is connected to the operating power VDD, and the source is connected to the ground power GND.
The discharging unit 31 can prevent the core circuit from being damaged by the impact of a large current when the large current is generated between the operating power supply VDD and the ground power supply GND. The discharge unit 31 (esd circuit) of the present embodiment has a protection effect on the core circuit 10 when a latch-up or an esd event occurs:
when the latch-up occurs, a large current is generated between the operating power supply VDD and the ground power supply GND, and before the path from the operating power supply VDD to the core circuit 10 is not closed, the discharging unit 31 may shunt a portion of the large current, so as to reduce the current flowing through the core circuit 10, thereby reducing the possibility that the core circuit 10 is damaged by the impact of the large current.
When an esd event occurs, an esd pulse occurs on the working power VDD or the ground power GND, and the discharge unit 31 can quickly form a discharge path to discharge a large esd current, so as to protect the core circuit 10 from being damaged by esd.
Another embodiment of the latch prevention circuit of the present invention is shown in fig. 8, which corresponds to the circuit of the embodiment shown in fig. 4. In conjunction with fig. 4 and 8, the circuit for preventing latch-up of the present embodiment includes: a voltage detection unit 12, a first switching unit 22, a second switching unit 23, and a discharge unit 31.
Compared with the voltage detection unit 11 shown in fig. 5, the voltage detection unit 12 shown in fig. 8 further includes an odd number of stages of inverters connected in series, and in this embodiment, the fourth inverter Inv4 is one stage of inverter. The input end of the inverter of the odd-numbered stage series is connected with the output end of the exclusive-or gate 11c, and the output end of the inverter of the odd-numbered stage series outputs the second control signal CT 1.
The first switching unit 22 shown in fig. 8 is the same as the switching unit 21 shown in fig. 5, and includes a first switching transistor MP 1. The second switch unit 23 includes a second switch transistor MN1, the second switch transistor MN1 is an NMOS transistor having a gate connected to the output terminal of the fourth inverter Inv4 of the voltage detection unit 12 (i.e., controlled by the second control signal CT 2), a source connected to the ground GND, and a drain connected to the second terminal B of the core circuit 10.
To sum up, the above technical solution detects the voltage of the core circuit through the comparator, and when the detected voltage is lower than the lowest voltage of the core circuit during normal operation and higher than a predetermined voltage, turns off the switch transistor connected between the power supply (the operating power supply and/or the ground power supply) and the core circuit, that is, turns off the path from the power supply to the core circuit, so as to cut off the power supply path from the power supply to the core circuit, so that a large current does not flow into the core circuit, thereby preventing the large current caused by the latch-up effect from affecting the core circuit, and avoiding the devices of the core circuit from being damaged.
In addition, when the discharging unit generates large current between the power supplies, partial large current can be shunted, so that the current flowing through the core circuit is reduced, and the core circuit can be prevented from being damaged due to the impact of the large current.
Although the present invention has been described with reference to the preferred embodiments, it is not intended to be limited thereto, and variations and modifications may be made by those skilled in the art without departing from the spirit and scope of the present invention.
Claims (7)
1. A circuit for preventing latch-up, comprising: a first comparator, a second comparator, an exclusive-or gate, an even-numbered stage of serially connected inverters and a first switching transistor, wherein,
the first comparator outputs a low level when the voltage of the core circuit is smaller than a preset voltage, otherwise outputs a high level, and the second comparator outputs a low level when the voltage of the core circuit is smaller than the lowest voltage of the core circuit in normal operation, otherwise outputs a high level; or,
the first comparator outputs a high level when the voltage of the core circuit is smaller than a preset voltage, otherwise outputs a low level, and the second comparator outputs a high level when the voltage of the core circuit is smaller than the lowest voltage of the core circuit in normal operation, otherwise outputs a high level;
two input ends of the exclusive-OR gate are respectively connected with output ends of the first comparator and the second comparator, and an output end of the exclusive-OR gate is connected with input ends of the even-level serial inverters;
the grid electrode of the first switch transistor is connected with the output end of the even-level serial inverter, the source electrode of the first switch transistor is connected with a working power supply, and the drain electrode of the first switch transistor is connected with one end of the core circuit connected with the working voltage.
2. The latch prevention circuit of claim 1, further comprising: an inverter and a second switching transistor connected in series in an odd-numbered stage, wherein,
the input end of the inverter connected in series with the odd-numbered stages is connected with the output end of the exclusive-OR gate;
and the grid electrode of the second switch transistor is connected with the output end of the odd-level serial inverter, the source electrode of the second switch transistor is connected with a grounding power supply, and the drain electrode of the second switch transistor is connected with one end of the core circuit, which is grounded.
3. The latch-up prevention circuit of claim 1 or 2, wherein the predetermined voltage is a holding voltage of a parasitic silicon controlled rectifier of the core circuit.
4. The latch prevention circuit of claim 2, further comprising: and a discharging unit that discharges when a current between the operating power supply and a ground power supply exceeds a predetermined current.
5. The latch up prevention circuit of claim 4 wherein the predetermined current is greater than a transient maximum current for normal operation of the core circuitry.
6. The latch prevention circuit according to claim 4, wherein the discharge unit comprises: the device comprises a capacitor, a resistor and a discharge transistor, wherein one end of the capacitor is connected with a working power supply, and the other end of the capacitor is connected with one end of the resistor and a grid electrode of the discharge transistor; the other end of the resistor is connected with a grounding power supply; the drain electrode of the discharge transistor is connected with a working power supply, and the source electrode of the discharge transistor is connected with a grounding power supply.
7. The latch prevention circuit according to claim 4, wherein the discharge unit comprises: the device comprises a capacitor, a resistor, a phase inverter and a discharge transistor, wherein one end of the capacitor is connected with a working power supply, and the other end of the capacitor is connected with one end of the resistor and the input end of the phase inverter; the output end of the inverter is connected with the grid electrode of the discharge transistor; the other end of the resistor is connected with a working power supply; the drain electrode of the discharge transistor is connected with a working power supply, and the source electrode of the discharge transistor is connected with a grounding power supply.
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| CN2009101992427A CN102064813A (en) | 2009-11-18 | 2009-11-18 | Latching prevention circuit |
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| CN2009101992427A CN102064813A (en) | 2009-11-18 | 2009-11-18 | Latching prevention circuit |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102364864A (en) * | 2011-10-28 | 2012-02-29 | 西安交通大学 | Pulse width modulation (PWM) control circuit and control method for peak current mode inverter |
| CN108270422A (en) * | 2018-03-20 | 2018-07-10 | 北京集创北方科技股份有限公司 | Anti- latch circuit and integrated circuit |
| CN110988440A (en) * | 2019-12-19 | 2020-04-10 | 上海微阱电子科技有限公司 | Current monitoring device and method of CMOS device |
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2009
- 2009-11-18 CN CN2009101992427A patent/CN102064813A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102364864A (en) * | 2011-10-28 | 2012-02-29 | 西安交通大学 | Pulse width modulation (PWM) control circuit and control method for peak current mode inverter |
| CN108270422A (en) * | 2018-03-20 | 2018-07-10 | 北京集创北方科技股份有限公司 | Anti- latch circuit and integrated circuit |
| CN110988440A (en) * | 2019-12-19 | 2020-04-10 | 上海微阱电子科技有限公司 | Current monitoring device and method of CMOS device |
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Application publication date: 20110518 |