CN203896318U - Differential input circuit - Google Patents
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- CN203896318U CN203896318U CN201420242075.6U CN201420242075U CN203896318U CN 203896318 U CN203896318 U CN 203896318U CN 201420242075 U CN201420242075 U CN 201420242075U CN 203896318 U CN203896318 U CN 203896318U
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Abstract
The utility model discloses a differential input circuit. A current-limiting resistor 1 and a current-limiting resistor 3 are connected in series between an input terminal 1 and an output terminal 1. A current-limiting resistor 2 and a current-limiting resistor 4 are connected in series between an input terminal 2 and an output terminal 2. A clamp resistor 1 and a reversed clamp diode 1 are connected in series between a direct current power supply and a node B. A reversed clamp diode 2 and a clamp resistor 2 are connected in series between the node B and the ground. A clamp resistor 3 and a reversed diode 3 are connected in series between the direct current power supply and a node A. A reversed clamp diode 4 is connected between the node A and the ground. A direct current bias resistor 1 is connected between the direct current power supply and the output terminal 2. A direct current bias resistor 2 is connected between an output terminal and the ground. A direct current bias resistor 3 is connected between the direct current power supply and the output terminal. A direct current bias resistor 4 is connected between the output terminal and the ground. According to the application provided by the utility model, anti-interference capability of differential input is increased under various faults, and the fault state is easy to be determined.
Description
Technical field
The application relates to a kind of Differential input circuit, particularly relates to a kind of Differential input circuit that is easy to failure judgement.
Background technology
Difference is inputted owing to possessing stronger anti-common mode disturbances ability, thereby is widely used in various circuit.Refer to Fig. 1, this is a kind of existing Differential input circuit.In parallel input equivalent resistance RI and input equivalent filter capacitor C I between two input in1, in2.In parallel divider resistance RD and EMC (Electro Magnetic Compatibility) filter capacitor CE between two output out1, out2.Current-limiting resistance one RL1 is connecting input one in1 and output one out1.Current-limiting resistance two RL2 are connecting input two in2 and output two out2.Outside input only provides heterodyne sub-signal, and its direct current syntype bias voltage is provided by rear coagulation chip completely.
Differential input circuit shown in Fig. 1 is when normal work, a pair of differential signal is entered by input in1, in2, input equivalent resistance RI and input equivalent filter capacitor C I flow through, again through current-limiting resistance one RL1 and current-limiting resistance two RL2, flow to divider resistance RD and EMC filter capacitor CE, the voltage on divider resistance RD is exported by output out1, out2 the most at last.Common two output out1, out2 are connected to two inputs of a block signal process chip.
The fault of Differential input circuit mainly comprises: two input in1, in2 short circuit; The outside high potential power (magnitude of voltage is higher than DC power supply voltage) of input one in1 short circuit; Input one in1 short circuit ground; Input one in1 short circuit negative supply; The outside high potential power of input two in2 short circuits; Input two in2 short circuit ground; Input two in2 short circuit negative supplies.General chip all can have inner clamper or have the maximum requirement that allows common-mode voltage at input, to protect port.When Differential input circuit breaks down, if exist disturbed or signal fluctuation causes clamp voltage shakiness or the common-mode rejection ratio of input of connected signal processing chip low, thereby the fault that this signal processing chip has Differential input circuit by None-identified so causes output abnormality.
At present Differential input circuit is carried out to failure diagnosis and have two schemes.Be to increase the fault that external sample circuit detects differential input end in1, in2, and this net mate can cause normally working time is uneven, affects the normal work of Differential input circuit.Another kind is to increase software Processing Algorithm the output signal of signal processing chip is carried out to failure diagnosis, and this can increase development cost, and has the defects such as flexibility is inadequate, software complexity is high.
Utility model content
The application's technical problem to be solved is to provide a kind of Differential input circuit, has both been easy to identify fault, can not cause again the output abnormality of connected signal processing chip when fault occurs.
For solving the problems of the technologies described above, the application's Differential input circuit, in parallel input equivalent resistance and input equivalent filter electric capacity between two inputs, EMC filter capacitor in parallel between two outputs; Between input one and output one, connecting current-limiting resistance one and current-limiting resistance three, between input two and output two, connecting current-limiting resistance two and current-limiting resistance four;
To between current-limiting resistance one and current-limiting resistance three, be called node A, will between current-limiting resistance two and current-limiting resistance four, be called Node B; Between DC power supply and Node B, connecting clamp resistance one and reverse clamp diode one, between Node B and ground, connecting reverse clamp diode two and clamp resistance two; Between DC power supply and node A, connecting clamp resistance three and reverse clamp diode three are connecting reverse clamp diode four between node A and ground;
The value of described clamp resistance one, clamp resistance two, clamp resistance three meets: at differential input signal, be zero, input is shorted under the prerequisite higher than DC power supply voltage and clamp diode one and clamp diode three conductings arbitrarily, and the magnitude of voltage of output one is higher than the magnitude of voltage of output two; At differential input signal, be zero, input is shorted under the prerequisite lower than earth potential and clamp diode two and clamp diode four conductings arbitrarily, and the magnitude of voltage of output one is higher than the magnitude of voltage of output two;
Between DC power supply and output two, be connected direct current biasing resistance one, between output two and ground, be connected direct current biasing resistance two; Between DC power supply and output one, be connected direct current biasing resistance three, between output one and ground, be connected direct current biasing resistance four;
The value of described four direct current biasing resistance meets: at differential input signal, be zero, and two input signals all do not have under the prerequisite of outside direct current biasing, the magnitude of voltage of output two is higher than the magnitude of voltage of output one, and the amplitude exceeding is less than the amplitude of normal input differential signal.
The application's Differential input circuit is to having improved the antijamming capability of difference input under various failure conditions.Under failure condition, guarantee the output state knowability of signal processing chip, thereby can eliminate fault mode because of the output abnormality problem of disturbing or signal fluctuation causes.Meanwhile, according to output state knowability, appearance that also can failure judgement, greatly reduces software and processes complexity.
Accompanying drawing explanation
Fig. 1 is a kind of schematic diagram of existing Differential input circuit;
Fig. 2 is the schematic diagram that the application is easy to the Differential input circuit of failure judgement.
Description of reference numerals in figure:
In1, in2 are input; RI is input equivalent resistance; CI is input equivalent filter electric capacity; RL1～RL4 is current-limiting resistance; RC1～RC3 is clamp resistance; DC1～DC4 is clamp diode; RD is divider resistance; CE is EMC filter capacitor; RB1～RB4 is direct current biasing resistance; Out1, out2 are output.
Embodiment
Refer to Fig. 2, this is the application's Differential input circuit.In parallel input equivalent resistance RI and input equivalent filter capacitor C I between two input in1, in2.EMC filter capacitor CE in parallel between two output out1, out2.Current-limiting resistance one RL1 and current-limiting resistance three RL3 are connecting between input one in1 and output one out1.Current-limiting resistance two RL2 and current-limiting resistance four RL4 are connecting between input two in2 and output two out2.These four current-limiting resistance RL1～RL4 have formed current limliting module.Described current limliting module is the current-limiting circuit to the asymmetric module of clamp voltage and two output out1, out2.
To between current-limiting resistance one RL1 and current-limiting resistance three RL3, be called node A, will between current-limiting resistance two RL2 and current-limiting resistance four RL4, be called Node B.Between DC power supply and Node B, connecting clamp resistance one RC1 and reverse clamp diode one DC1, reverse clamp diode two DC2 and clamp resistance two RC2 are connecting between Node B and ground.Between DC power supply and node A, connecting clamp resistance three RC3 and reverse clamp diode three DC3 are connecting reverse clamp diode four DC4 between node A and ground.These three clamp resistance RC1～RC3 and four clamp diode DC1～DC4 have formed the asymmetric module of clamp voltage.The asymmetric module of described clamp voltage refers to that difference input is all asymmetric to power supply or difference clamp voltage over the ground respectively.
The value of described clamp resistance one RC1, clamp resistance two RC2, clamp resistance three RC3 need meet following 2 points:
One, at differential input signal, be zero, any one or two input in1, in2 are shorted to the voltage higher than DC power supply, and under the prerequisite of clamp diode one DC1 and clamp diode three DC3 conductings, the magnitude of voltage of output one out1 is higher than the magnitude of voltage of output two out2.
They are two years old, at differential input signal, be zero, any one or two input in1, in2 are shorted to lower than earth potential, and under the prerequisite of clamp diode two DC2 and clamp diode four DC4 conductings, the magnitude of voltage of output one out1 is higher than the magnitude of voltage of output two out2.
For example, at differential input signal, be zero, when any one or two input in1, in2 are shorted to higher than the voltage of DC power supply or are shorted to lower than earth potential, the magnitude of voltage of output one out1 higher than the amplitude of the magnitude of voltage of output two out2 between 17～50mV.
Between DC power supply and output two out2, be connected direct current biasing resistance one RB1, between output two out2 and ground, be connected direct current biasing resistance two RB2.Between DC power supply and output one out1, be connected direct current biasing resistance three RB3, between output one out1 and ground, be connected direct current biasing resistance four RB4.These four direct current biasing resistance R B1～RB4 have formed direct current biasing module.Described direct current biasing module coordinates with the asymmetric module of clamp voltage, can be having, export signal specific state under non-failure conditions, guarantee that Differential input circuit has certain antijamming capability on the one hand, can realize in conjunction with control strategy the diagnosis of fault mode on the other hand.
The value of described direct current biasing resistance R B1～RB4 need meet: at two input in1, in2 differential input signal, be zero, and two input signals all do not have under the prerequisite of outside direct current biasing, the magnitude of voltage of output two out2 is higher than the magnitude of voltage of output one out1, the amplitude exceeding is less than the amplitude of normal input differential signal, and the amplitude exceeding is for example between 50～300mV.
Compare with the existing Differential input circuit shown in Fig. 1, the application's Differential input circuit has been deleted divider resistance RD, increased current limliting module, the asymmetric module of clamp voltage and direct current biasing module newly, its objective is and improve input signal signal to noise ratio, and be easy to fault mode to diagnose.
In use, two of the Differential input circuit of the application shown in Fig. 2 output out1, out2 connect respectively positive input terminal, the negative input end of a block signal process chip.Meanwhile, require two input in1, in2 of Differential input circuit only to provide heterodyne sub-signal and any DC offset voltage is not provided.Under normal work and various failure condition, the application's Differential input circuit or do not affect the normal output of connected signal processing chip, or can find in time fault.
One, when normal work, limit the voltage of input in1, any one input signal of in2 all between ground voltage and DC power supply voltage, four clamp diode DC1, DC2, DC3, DC4 all can conductings, according to two-port network equivalence, the difference input network of Fig. 2 is approximately equal to the difference input network of Fig. 1.But due to the value of direct current biasing module, make the magnitude of voltage of output two out2 can be higher than the magnitude of voltage of output one out1.This has increased a detection threshold with regard to being equivalent at the negative input end of this signal processing chip, and this thresholding is less than the amplitude of normal input differential signal, thereby has improved the antijamming capability of the application's Differential input circuit.
When the applied signal voltage of input one in1 is during lower than input two in2, further consider the thresholding that direct current biasing module increases, the negative input end voltage of the signal processing chip connecting is higher than its positive input terminal voltage, and this signal processing chip is exported the first level state (for example low level) all the time.When the applied signal voltage of input one in1 is during higher than input two in2, because input signal amplitude is greater than the threshold value that biasing module increases, the positive input terminal voltage of the signal processing chip connecting is higher than its negative input end voltage, and this signal processing chip is exported second electrical level state (for example high level) all the time.This has just guaranteed Output rusults normal of signal processing chip.
While two, there is short circuit fault between two input in1, in2, differential input signal is zero, four clamp diode DC1, DC2, DC3, DC4 all can conductings, due to the value of direct current biasing module, make the magnitude of voltage of output two out2 higher than output one out1.The negative input end voltage of the signal processing chip therefore connecting is forever higher than its positive input terminal voltage, and this signal processing chip is exported the first level state (for example low level) all the time.
Three, when input one in1 is shorted to earth fault, if the applied signal voltage of input two in2 is higher than the applied signal voltage of input one in1, the output signal voltage value of output two out2 exceeds the output signal voltage value of output one out1, the negative input end voltage of the signal processing chip connecting is higher than its positive input terminal voltage, and this signal processing chip is exported the first level state (for example low level) all the time.If the applied signal voltage of input two in2 is lower than the applied signal voltage of input one in1, because input signal amplitude is greater than the threshold value that direct current biasing module increases, the output signal voltage value of output two out2 is lower than the output signal voltage value of output one out1, the negative input end voltage of the signal processing chip connecting is lower than its positive input terminal voltage, and this signal processing chip is exported second electrical level state (for example high level) all the time.This has just guaranteed Output rusults normal of signal processing chip.
Four, when input two in2 are shorted to earth fault, if the applied signal voltage of input one in1 is higher than the applied signal voltage of input two in2, because input signal amplitude is greater than the threshold value that direct current biasing module increases, the output signal voltage value of output one out1 is higher than the output signal voltage value of output two out2, the positive input terminal voltage of the signal processing chip connecting is higher than its negative input end voltage, and this signal processing chip is exported second electrical level state (for example high level) all the time.If the applied signal voltage of input one in1 is lower than the applied signal voltage of input two in2, further consider the thresholding that direct current biasing module increases, the output signal voltage value of output one out1 is lower than the output signal voltage value of output two out2, the negative input end voltage of the signal processing chip connecting is higher than its positive input terminal voltage, and this signal processing chip is exported the first level state (for example low level) all the time.This has just guaranteed Output rusults normal of signal processing chip.
Five, at input one in1, be shorted to the fault of outside high potential power or be shorted to negative supply fault, and when differential input signal is zero, due to the value of the asymmetric module of clamp voltage, make the magnitude of voltage of output one out1 by the magnitude of voltage higher than output two out2.The positive input terminal voltage of the signal processing chip that connected is so forever higher than its negative input end voltage, and this signal processing chip is exported second electrical level state (for example high level) all the time.
Input one in1 is shorted to outside high potential power fault, is divided into following two kinds of situations:
At input one in1, be shorted to outside high potential power fault, and input two in2 inputs be negative voltage signal time, further consider the asymmetric module value of clamp voltage, the magnitude of voltage of output one out1 is higher than output two out2, the positive input terminal voltage of the signal processing chip connecting is higher than its negative input end voltage, and this signal processing chip is exported second electrical level state (for example high level).
At input one in1, be shorted to outside high potential power fault, and input two in2 inputs be positive voltage signal time, if input signal amplitude is less, the asymmetric module of clamp voltage plays a leading role to output, the magnitude of voltage of output one out1 is higher than output two out2, the positive input terminal voltage of the signal processing chip connecting is higher than its negative input end voltage, and this signal processing chip is exported second electrical level state (for example high level).If input signal amplitude is larger, input signal plays a leading role to output, the magnitude of voltage of output one out1 is lower than output two out2, the positive input terminal voltage of the signal processing chip connecting is lower than its negative input end voltage, and this signal processing chip is exported the first level state (for example low level).
Hence one can see that, at input one in1, is shorted to outside high potential power fault, and whether output signal is normally subject to the impact of input signal amplitude.In order detecting, to be shorted to power failure, can to make two input in1, in2 without input.Under normal circumstances, the magnitude of voltage of two input in1, in2 output two out2 during without input is higher than output one out1, and the signal processing chip therefore connecting is exported the first level state (for example low level).If when there are input two in1 and being shorted to power supply, the signal processing chip output second electrical level state (for example high level) connecting.
Input one in1 is shorted to outside negative supply fault, is divided into following two kinds of situations:
At input one in1, be shorted to outside negative supply fault, and input two in2 inputs be negative voltage signal time, further consider the asymmetric module of clamp voltage, the magnitude of voltage of output one out1 is higher than output two out2, the positive input terminal voltage of the signal processing chip connecting is higher than its negative input end voltage, and this signal processing chip is exported second electrical level state (for example high level).
At input one in1, be shorted to outside negative supply fault, and input two in2 inputs be positive voltage signal time, if input signal amplitude is less, the asymmetric module of clamp voltage plays a leading role to output, the magnitude of voltage of output one out1 is higher than output two out2, the positive input terminal voltage of the signal processing chip connecting is higher than its negative input end voltage, and this signal processing chip is exported second electrical level state (for example high level).If input signal amplitude is larger, input signal plays a leading role to output, the magnitude of voltage of output one out1 is lower than output two out2, the positive input terminal voltage of the signal processing chip connecting is lower than its negative input end voltage, and this signal processing chip is exported the first level state (for example low level).
Hence one can see that, at input one in1, is shorted to outside negative supply fault, and whether output signal is normally subject to the impact of differential input signal amplitude.In order detecting, to be shorted to power failure, can to make two input in1, in2 without input.Under normal circumstances, the magnitude of voltage of two input in1, in2 output two out2 during without input is higher than output one out1, and the signal processing chip therefore connecting is exported the first level state (for example low level).If when there are input two in1 and being shorted to power supply, the signal processing chip output second electrical level state (for example high level) connecting.
Six, at input two in2, be shorted to the fault of outside high potential power or be shorted to negative supply fault, and when differential input signal is zero, due to the value of the asymmetric module of clamp voltage, make the magnitude of voltage of output one out1 by the magnitude of voltage higher than output two out2.The positive input terminal voltage of the signal processing chip that connected is so forever higher than its negative input end voltage, and this signal processing chip is exported second electrical level state (for example high level) all the time.
Input two in2 are shorted to outside high potential power fault, are divided into following two kinds of situations:
At input two in2, be shorted to outside high potential power fault, and input one in1 input be positive voltage signal time, further consider the asymmetric module value of clamp voltage, the magnitude of voltage of output one out1 is higher than output two out2, the positive input terminal voltage of the signal processing chip connecting is higher than its negative input end voltage, and this signal processing chip is exported second electrical level state (for example high level).
At input two in2, be shorted to outside high potential power fault, and input one in1 input be negative voltage signal time, if input signal amplitude is less, the asymmetric module of clamp voltage plays a leading role to output, the magnitude of voltage of output one out1 is higher than output two out2, the positive input terminal voltage of the signal processing chip connecting is higher than its negative input end voltage, and this signal processing chip is exported second electrical level state (for example high level).If input signal amplitude is larger, input signal plays a leading role to output, the magnitude of voltage of output one out1 is lower than output two out2, the positive input terminal voltage of the signal processing chip connecting is lower than its negative input end voltage, and this signal processing chip is exported the first level state (for example low level).
Hence one can see that, at input two in2, is shorted to outside high potential power fault, and whether output signal is normally subject to the impact of input signal amplitude.In order detecting, to be shorted to power failure, can to make two input in1, in2 without input.Under normal circumstances, the magnitude of voltage of two input in1, in2 output two out2 during without input is higher than output one out1, and the signal processing chip therefore connecting is exported the first level state (for example low level).If when there are input two in2 and being shorted to power supply, the signal processing chip output second electrical level state (for example high level) connecting.
Input two in2 are shorted to outside negative supply fault, are divided into following two kinds of situations:
At input two in2, be shorted to outside negative supply fault, and input one in1 input be positive voltage signal time, further consider the asymmetric module of clamp voltage, the magnitude of voltage of output one out1 is higher than output two out2, the positive input terminal voltage of the signal processing chip connecting is higher than its negative input end voltage, and this signal processing chip is exported second electrical level state (for example high level).
At input two in2, be shorted to outside negative supply fault, and input one in1 input be negative voltage signal time, if input signal amplitude is less, the asymmetric module of clamp voltage plays a leading role to output, the magnitude of voltage of output one out1 is higher than output two out2, the positive input terminal voltage of the signal processing chip connecting is higher than its negative input end voltage, and this signal processing chip is exported second electrical level state (for example high level).If input signal amplitude is larger, input signal plays a leading role to output, the magnitude of voltage of output one out1 is lower than output two out2, the positive input terminal voltage of the signal processing chip connecting is lower than its negative input end voltage, and this signal processing chip is exported the first level state (for example high level).
Hence one can see that, at input two in2, is shorted to outside negative supply fault, and whether output signal is normally subject to the impact of differential input signal amplitude.In order detecting, to be shorted to power failure, can to make two input in1, in2 without input.Under normal circumstances, the magnitude of voltage of two input in1, in2 output two out2 during without input is higher than output one out1, and the signal processing chip therefore connecting is exported the first level state (for example low level).If when there are input two in2 and being shorted to power supply, the signal processing chip output second electrical level state (for example high level) connecting.
The size that all refers to the absolute value of voltage magnitude during the magnitude relationship comparison of above six kinds of situations, arranges as shown in the table by above six kinds of situations:
As can be seen here, under normal work and various failure condition, the application's Differential input circuit or do not affect the normal output of connected signal processing chip, or can find easily fault by simple operations (making the amplitude magnitude relationship of in1, in2 change or make input signal is zero).
These are only the application's preferred embodiment, and be not used in restriction the application.For a person skilled in the art, the application can have various modifications and variations.All within the application's spirit and principle, any modification of doing, be equal to replacement, improvement etc., within all should being included in the application's protection range.
Claims (3)
1. a Differential input circuit, in parallel input equivalent resistance and input equivalent filter electric capacity between two inputs, EMC filter capacitor in parallel between two outputs; It is characterized in that between input one and output one, connecting current-limiting resistance one and current-limiting resistance three, between input two and output two, connecting current-limiting resistance two and current-limiting resistance four;
To between current-limiting resistance one and current-limiting resistance three, be called node A, will between current-limiting resistance two and current-limiting resistance four, be called Node B; Between DC power supply and Node B, connecting clamp resistance one and reverse clamp diode one, between Node B and ground, connecting reverse clamp diode two and clamp resistance two; Between DC power supply and node A, connecting clamp resistance three and reverse clamp diode three are connecting reverse clamp diode four between node A and ground;
The value of described clamp resistance one, clamp resistance two, clamp resistance three meets: at differential input signal, be zero, input is shorted under the prerequisite higher than DC power supply voltage and clamp diode one and clamp diode three conductings arbitrarily, and the magnitude of voltage of output one is higher than the magnitude of voltage of output two; At differential input signal, be zero, input is shorted under the prerequisite lower than earth potential and clamp diode two and clamp diode four conductings arbitrarily, and the magnitude of voltage of output one is higher than the magnitude of voltage of output two;
Between DC power supply and output two, be connected direct current biasing resistance one, between output two and ground, be connected direct current biasing resistance two; Between DC power supply and output one, be connected direct current biasing resistance three, between output one and ground, be connected direct current biasing resistance four;
The value of described four direct current biasing resistance meets: at differential input signal, be zero, and two input signals all do not have under the prerequisite of outside direct current biasing, the magnitude of voltage of output two is higher than the magnitude of voltage of output one, and the amplitude exceeding is less than the amplitude of normal input differential signal.
2. Differential input circuit according to claim 1, it is characterized in that, the value of described clamp resistance one, clamp resistance two, clamp resistance three meets: at differential input signal, be zero, when arbitrarily input is shorted to higher than DC power supply current potential or is shorted to lower than earth potential, the magnitude of voltage of output one higher than the magnitude of voltage of output two between 17～50mV.
3. Differential input circuit according to claim 1, it is characterized in that, the value of described four direct current biasing resistance meets: at differential input signal, be zero, and when two input signals all do not have outside direct current biasing, the magnitude of voltage of output two higher than the magnitude of voltage of output one between 50～300mV.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420242075.6U CN203896318U (en) | 2014-05-13 | 2014-05-13 | Differential input circuit |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201420242075.6U CN203896318U (en) | 2014-05-13 | 2014-05-13 | Differential input circuit |
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| CN203896318U true CN203896318U (en) | 2014-10-22 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104022748B (en) * | 2014-05-13 | 2017-01-25 | 联合汽车电子有限公司 | Differential input circuit and method for obtaining differential input circuit |
| TWI788784B (en) * | 2020-02-20 | 2023-01-01 | 大陸商博世汽車部件（蘇州）有限公司 | Integrated interface circuit and manufacturing method of interface circuit |
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2014
- 2014-05-13 CN CN201420242075.6U patent/CN203896318U/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104022748B (en) * | 2014-05-13 | 2017-01-25 | 联合汽车电子有限公司 | Differential input circuit and method for obtaining differential input circuit |
| TWI788784B (en) * | 2020-02-20 | 2023-01-01 | 大陸商博世汽車部件（蘇州）有限公司 | Integrated interface circuit and manufacturing method of interface circuit |
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