CN102201807B - Simple tristate input circuit - Google Patents

Abstract

The invention discloses a tristate input circuit. In the circuit, the fact that bases and collectors of audions are in short circuit so as to have the characteristics of diodes is utilized, and one input end of two differential amplifiers is biased to two fixed voltages; the voltage D-value between the two fixed voltages is the conduction pressure drop Vbe of the diode; and the characteristic that the differential amplifiers are sensitive to a voltage difference is used to amplify the voltage D-value and output corresponding marking signals as well as detect that the input is in a high level, low level or suspension state, thus realizing the tristate input.

Description

A kind of simple ternary input circuit

Technical field

The present invention is mainly concerned with input IO circuit design field, refers in particular to a kind of ternary input circuit.

Background technology

Because the progress of manufacturing process and the continuous lifting of designing technique, increasing functional module is integrated in the middle of the same chip, and SOC is more and more general; Increasing of functional module; Must cause the signal of input and output to increase, for chip, this must cause the chip I number to increase.Owing to comprise driving and ESD logic, its area is bigger usually among the IO, and for a lot of controls type chips, because the IO number is a lot, its area is not the functional module area that is subject to itself, but is subject to the area of IO.Increasing of IO number must cause the increase of chip power-consumption, the problems such as cost increase of Chip Packaging simultaneously.

To the problems referred to above; In order to dwindle chip area, reduce power consumption, to practice thrift cost; A lot of chips have adopted the IO multiplex technique, and this technology solves the problem that chip area is subject to the IO number well, but it has also increased inner control logic and external control IO simultaneously.For some chip, ternary input IO is a better choice, in theory; One 2 value IO can only characterize two logic states, and characterizing 3 logic states needs two IO at least, and ternary input IO just can characterize 3 logic states with an IO; For chip; Can reduce by 1/3 input IO in theory, and the inner control logic being also very simple, is exactly in fact a simple decoding circuit; This has reduced the pressure that chip area is subject to the IO number to a great extent, has reduced chip area, has reduced power consumption, has practiced thrift cost.

Summary of the invention

The problem that the present invention will solve just is: to the prior art problem, a kind of simple ternary input circuit is provided.

The solution that the present invention proposes is: this circuit utilizes the base stage of triode, the diode characteristic that the collector electrode short circuit has; One of them input with two differential amplifiers is biased to two fixed voltages respectively, the conduction voltage drop V that its two voltage differences are diode _Be, utilize the differential amplifier characteristic responsive then to voltage difference, this voltage difference is amplified, export corresponding marking signal, detection is input as high level, low level still is unsettled, thereby realizes ternary input.

Compared with prior art, advantage of the present invention just is:

1, excellent performance: utilize the base stage of triode, the diode characteristic that the collector electrode short circuit has, a stable voltage difference is provided, be the reliable input signal of providing of amplifier, the PVT characteristic is good.

2, simple in structure: the circuit that proposes among the present invention is only used two differential amplifiers and a voltage offset electric circuit, and structure is very simple.

Description of drawings

Fig. 1 is circuit theory diagrams of the present invention;

Embodiment

Below will combine accompanying drawing and practical implementation that the present invention is explained further details.

As shown in Figure 1, circuit of the present invention is made up of four parts, biasing circuit BIAS1, BIAS2, and fully-differential amplifier AMP1, AMP2 form, and R1 is the input current-limiting resistance in addition.R2, R3 are identical, and resistance is very big, and its effect is when input In is unsettled, and a is biased to V _DD/ 2, V wherein _DDBe supply voltage; R7, triode Q4 and R8 form biasing circuit BIAS2, and this biasing circuit is biased to (V with node b point voltage _DD+ V _Be)/2 are biased to (V with node c point voltage _DD-V _Be)/2, promptly the voltage difference of b node and c node is V _BeThe fully-differential amplifier AMP1 that triode Q1, Q2, Q3 and resistance R 4, R5, R6 form; Input is respectively a and b, and output is respectively Z1 and Z1b, the fully-differential amplifier AMP2 that triode Q5, Q6, Q7 and resistance R 9, R10, R11 form; Input is respectively a and c; Output is Z2 and Z2b respectively, and these two amplifiers are just the same, and just one of them input signal is different.

For differential output signal Z1, Z1b and Z2, Z2b, our settled approximately Z1-Z1b＞0 o'clock is a high level, and Z1-Z1b＜0th is low level; When Z2-Z2b＞0 is high level, and Z2-Z2b＜0th is low level, and as shown in table 1, H representes high level, and L representes low level.Below just ternary input discuss respectively:

Table 1. truth table

?In	Z1-Z1b	Z2-Z2b
			H	L	H
L	H	L
			Unsettled, V DD/2	H	H

1), when input In is high level H, be assumed to be V _DD:

Because R2, R3 resistance are very big, can ignore, then this moment a voltage be V _DD, the input signal of AMP1 does so

$V_a-V_b=V_{\mathrm{DD}}-\frac{V_{\mathrm{DD}}+V_{\mathrm{be}}}{2}=\frac{V_{\mathrm{DD}}-V_{\mathrm{be}}}{2}>0---\left(1\right)$

The input signal of amplifier AMP2 does

$V_c-V_a=\frac{V_{\mathrm{DD}}-V_{\mathrm{be}}}{2}-V_{\mathrm{DD}}=-\frac{V_{\mathrm{DD}}+V_{\mathrm{be}}}{2}<0---\left(2\right)$

Because Amplifier Gain is bigger, and be negative value, make Z1-Z1b＜0, Z2-Z2b＞0, promptly AMP1 is output as low level, and AMP2 is output as high level.

2), when input In is low level L, be assumed to be 0:

Because R2, R3 resistance are very big, can ignore, then this moment a voltage be 0, the input signal of AMP1 does so

$V_a-V_b=0-\frac{V_{\mathrm{DD}}+V_{\mathrm{be}}}{2}=-\frac{V_{\mathrm{DD}}+V_{\mathrm{be}}}{2}<0---\left(3\right)$

The input signal of amplifier AMP2 does

$V_c-V_a=\frac{V_{\mathrm{DD}}-V_{\mathrm{be}}}{2}-0=\frac{V_{\mathrm{DD}}-V_{\mathrm{be}}}{2}>0---\left(4\right)$

Because Amplifier Gain is bigger, and be negative value, make Z1-Z1b＞0, Z2-Z2b＜0, promptly AMP1 is output as high level, and high level is hanged down in AMP2 output.

3), unsettled as input In, perhaps meet V _DD/ 2 o'clock:

If when input was unsettled, resistance R 2, R3 can be biased to V with node a _DD/ 2; When V is received in input _DD/ 2, the voltage of node a is similarly V _DD/ 2.This moment, the input signal of amplifier AMP1 did

$V_a-V_b=\frac{V_{\mathrm{DD}}}{2}-\frac{V_{\mathrm{DD}}+V_{\mathrm{be}}}{2}=-\frac{V_{\mathrm{be}}}{2}<0---\left(5\right)$

The input signal of amplifier AMP2 does

$V_c-V_a=\frac{V_{\mathrm{DD}}-V_{\mathrm{be}}}{2}-\frac{V_{\mathrm{DD}}}{2}=-\frac{V_{\mathrm{be}}}{2}<0---\left(6\right)$

Because Amplifier Gain is bigger, and is negative value, makes that Z1-Z1b＞0, Z2-Z2b＞0, the i.e. output of AMP1, AMP2 all are high level.

According to above-mentioned analysis, can find out, be high level, low level, unsettled or meet V to input signal _DD/ 2, corresponding meeting output various signals, thus realize ternary input.

Claims (1)

1. simple ternary input circuit is characterized in that:

This three-state input circuit is made up of resistance R 1, R2, R3, R4, R5, R6, R7, R8, R9 and triode Q1, Q2, Q3, Q4, Q5, Q6, Q7; In is an input port, is connected to resistance R 1, and resistance R 1, resistance R 2, resistance R 3 all are connected to a with the base stage of Q1, Q6; Triode Q1, triode Q2, triode Q3 and resistance R 4, resistance R 5, resistance R 6 are formed a fully-differential amplifier, and input is respectively the base stage a of Q1 and the base stage b of Q2, and output is respectively the collector electrode Z1 of Q1 and the collector electrode Z1b of Q2; Triode Q5, triode Q6, triode Q7 and resistance R 9, resistance R 10, resistance R 11 are formed another fully-differential amplifier, and input is respectively the base stage a of Q6 and the base stage c of Q5, and output is respectively the collector electrode Z2 of Q5 and the collector electrode Z2b of Q6; Resistance R 7, resistance R 8 and triode Q4 are biasing circuits; The base stage of Q4, collector electrode and resistance R 7 all are connected to the base stage b of Q2; The emitter of Q4 and resistance R 8 all are connected to the base stage c of Q5, and the tail current source offset signal of two differential amplifiers is Bias, is connected respectively to the base stage of Q3, Q7; The described ternary input of circuit is that input signal In is high level, low level or unsettled, corresponding differential output signal Z1, Z1b and Z2, Z2b, settled approximately Z1-Z1b>0 o'clock represent high level, Z1-Z1b the 0th, represent low level; As Z2-Z2b>represent high level 0 the time, < represented low level at 0 o'clock, promptly correspondence has following three kinds of outputs: when input signal In was low level, output signal Z1-Z1b was a high level to Z2-Z2b, and Z2-Z2b is a low level; When input signal In was high level, output Z1-Z1b was a low level, and Z2-Z2b is a high level; When input signal In was unsettled, output Z1-Z1b was a high level, and Z2-Z2b is a high level; Three kinds of input states of promptly corresponding input In, output Z1-Z1b, the corresponding output of Z2-Z2b various signals, thus realize ternary input circuit.

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